static_inst.cc revision 6192:6cd5f0282d8a
16019SN/A/* 26019SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 310037SARM gem5 Developers * All rights reserved. 410037SARM gem5 Developers * 510037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 610037SARM gem5 Developers * modification, are permitted provided that the following conditions are 710037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 810037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 910037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 1010037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 1110037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 1210037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 1310037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 1410037SARM gem5 Developers * this software without specific prior written permission. 156019SN/A * 166019SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019SN/A * 286019SN/A * Authors: Steve Reinhardt 296019SN/A * Nathan Binkert 306019SN/A */ 316019SN/A 326019SN/A#include <iostream> 336019SN/A#include "cpu/static_inst.hh" 346019SN/A#include "sim/core.hh" 356019SN/A 366019SN/AStaticInstPtr StaticInst::nullStaticInstPtr; 376019SN/A 386019SN/A// Define the decode cache hash map. 396019SN/AStaticInst::DecodeCache StaticInst::decodeCache; 406019SN/AStaticInst::AddrDecodeCache StaticInst::addrDecodeCache; 416019SN/AStaticInst::cacheElement StaticInst::recentDecodes[2]; 426019SN/A 436019SN/Ausing namespace std; 446019SN/A 456019SN/AStaticInst::~StaticInst() 466019SN/A{ 476019SN/A if (cachedDisassembly) 486019SN/A delete cachedDisassembly; 496019SN/A} 506019SN/A 516019SN/Avoid 526250SN/AStaticInst::dumpDecodeCacheStats() 5312616Sgabeblack@google.com{ 5412616Sgabeblack@google.com cerr << "Decode hash table stats @ " << curTick << ":" << endl; 556019SN/A cerr << "\tnum entries = " << decodeCache.size() << endl; 566019SN/A cerr << "\tnum buckets = " << decodeCache.bucket_count() << endl; 576019SN/A vector<int> hist(100, 0); 586019SN/A int max_hist = 0; 596019SN/A for (int i = 0; i < decodeCache.bucket_count(); ++i) { 608737Skoansin.tan@gmail.com int count = decodeCache.elems_in_bucket(i); 616019SN/A if (count > max_hist) 626019SN/A max_hist = count; 637848SAli.Saidi@ARM.com hist[count]++; 647848SAli.Saidi@ARM.com } 657848SAli.Saidi@ARM.com for (int i = 0; i <= max_hist; ++i) { 667848SAli.Saidi@ARM.com cerr << "\tbuckets of size " << i << " = " << hist[i] << endl; 677848SAli.Saidi@ARM.com } 686019SN/A} 696019SN/A 706019SN/Abool 7110037SARM gem5 DevelopersStaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const 7210184SCurtis.Dunham@arm.com{ 7310037SARM gem5 Developers if (isDirectCtrl()) { 7410037SARM gem5 Developers tgt = branchTarget(pc); 7510037SARM gem5 Developers return true; 7610037SARM gem5 Developers } 7710037SARM gem5 Developers 786019SN/A if (isIndirectCtrl()) { 796019SN/A tgt = branchTarget(tc); 806019SN/A return true; 8112234Sgabeblack@google.com } 8212234Sgabeblack@google.com 836019SN/A return false; 846019SN/A} 856019SN/A 866019SN/AStaticInstPtr 876019SN/AStaticInst::fetchMicroop(MicroPC micropc) 886019SN/A{ 896019SN/A panic("StaticInst::fetchMicroop() called on instruction " 906019SN/A "that is not microcoded."); 916019SN/A} 926019SN/A 936019SN/AAddr 946019SN/AStaticInst::branchTarget(Addr branchPC) const 956019SN/A{ 966019SN/A panic("StaticInst::branchTarget() called on instruction " 976019SN/A "that is not a PC-relative branch."); 986019SN/A M5_DUMMY_RETURN; 996019SN/A} 1006019SN/A 1016019SN/AAddr 1026019SN/AStaticInst::branchTarget(ThreadContext *tc) const 1036019SN/A{ 1046019SN/A panic("StaticInst::branchTarget() called on instruction " 1056019SN/A "that is not an indirect branch."); 1066019SN/A M5_DUMMY_RETURN; 107} 108 109const string & 110StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const 111{ 112 if (!cachedDisassembly) 113 cachedDisassembly = new string(generateDisassembly(pc, symtab)); 114 115 return *cachedDisassembly; 116} 117