static_inst.cc revision 8229
12SN/A/* 21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 322SN/A#include <iostream> 338229Snate@binkert.org 3456SN/A#include "cpu/static_inst.hh" 354167Sbinkertn@umich.edu#include "sim/core.hh" 362SN/A 372107SN/AStaticInstPtr StaticInst::nullStaticInstPtr; 382SN/A 392SN/A// Define the decode cache hash map. 402107SN/AStaticInst::DecodeCache StaticInst::decodeCache; 414572Sacolyte@umich.eduStaticInst::AddrDecodeCache StaticInst::addrDecodeCache; 424572Sacolyte@umich.eduStaticInst::cacheElement StaticInst::recentDecodes[2]; 432SN/A 445870Snate@binkert.orgusing namespace std; 455870Snate@binkert.org 465870Snate@binkert.orgStaticInst::~StaticInst() 475870Snate@binkert.org{ 485870Snate@binkert.org if (cachedDisassembly) 495870Snate@binkert.org delete cachedDisassembly; 505870Snate@binkert.org} 515870Snate@binkert.org 522SN/Avoid 532107SN/AStaticInst::dumpDecodeCacheStats() 542SN/A{ 557823Ssteve.reinhardt@amd.com cerr << "Decode hash table stats @ " << curTick() << ":" << endl; 562SN/A cerr << "\tnum entries = " << decodeCache.size() << endl; 572SN/A cerr << "\tnum buckets = " << decodeCache.bucket_count() << endl; 582SN/A vector<int> hist(100, 0); 592SN/A int max_hist = 0; 602SN/A for (int i = 0; i < decodeCache.bucket_count(); ++i) { 612SN/A int count = decodeCache.elems_in_bucket(i); 622SN/A if (count > max_hist) 632SN/A max_hist = count; 642SN/A hist[count]++; 652SN/A } 662SN/A for (int i = 0; i <= max_hist; ++i) { 672SN/A cerr << "\tbuckets of size " << i << " = " << hist[i] << endl; 682SN/A } 692SN/A} 702SN/A 712SN/Abool 727720Sgblack@eecs.umich.eduStaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, 737720Sgblack@eecs.umich.edu TheISA::PCState &tgt) const 742SN/A{ 752SN/A if (isDirectCtrl()) { 762SN/A tgt = branchTarget(pc); 772SN/A return true; 782SN/A } 792SN/A 802SN/A if (isIndirectCtrl()) { 812680Sktlim@umich.edu tgt = branchTarget(tc); 822SN/A return true; 832SN/A } 842SN/A 852SN/A return false; 862SN/A} 872SN/A 883271Sgblack@eecs.umich.eduStaticInstPtr 897720Sgblack@eecs.umich.eduStaticInst::fetchMicroop(MicroPC upc) const 903271Sgblack@eecs.umich.edu{ 914539Sgblack@eecs.umich.edu panic("StaticInst::fetchMicroop() called on instruction " 925870Snate@binkert.org "that is not microcoded."); 933271Sgblack@eecs.umich.edu} 943271Sgblack@eecs.umich.edu 957720Sgblack@eecs.umich.eduTheISA::PCState 967720Sgblack@eecs.umich.eduStaticInst::branchTarget(const TheISA::PCState &pc) const 975870Snate@binkert.org{ 985870Snate@binkert.org panic("StaticInst::branchTarget() called on instruction " 995870Snate@binkert.org "that is not a PC-relative branch."); 1005870Snate@binkert.org M5_DUMMY_RETURN; 1015870Snate@binkert.org} 1025870Snate@binkert.org 1037720Sgblack@eecs.umich.eduTheISA::PCState 1045870Snate@binkert.orgStaticInst::branchTarget(ThreadContext *tc) const 1055870Snate@binkert.org{ 1065870Snate@binkert.org panic("StaticInst::branchTarget() called on instruction " 1075870Snate@binkert.org "that is not an indirect branch."); 1085870Snate@binkert.org M5_DUMMY_RETURN; 1095870Snate@binkert.org} 1105870Snate@binkert.org 1115870Snate@binkert.orgconst string & 1125870Snate@binkert.orgStaticInst::disassemble(Addr pc, const SymbolTable *symtab) const 1135870Snate@binkert.org{ 1145870Snate@binkert.org if (!cachedDisassembly) 1155870Snate@binkert.org cachedDisassembly = new string(generateDisassembly(pc, symtab)); 1165870Snate@binkert.org 1175870Snate@binkert.org return *cachedDisassembly; 1185870Snate@binkert.org} 119