smt.hh revision 6221
12SN/A/* 213168Smatt.horsnell@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 37760SGiacomo.Gabrielli@arm.com * All rights reserved. 47760SGiacomo.Gabrielli@arm.com * 57760SGiacomo.Gabrielli@arm.com * Redistribution and use in source and binary forms, with or without 67760SGiacomo.Gabrielli@arm.com * modification, are permitted provided that the following conditions are 77760SGiacomo.Gabrielli@arm.com * met: redistributions of source code must retain the above copyright 87760SGiacomo.Gabrielli@arm.com * notice, this list of conditions and the following disclaimer; 97760SGiacomo.Gabrielli@arm.com * redistributions in binary form must reproduce the above copyright 107760SGiacomo.Gabrielli@arm.com * notice, this list of conditions and the following disclaimer in the 117760SGiacomo.Gabrielli@arm.com * documentation and/or other materials provided with the distribution; 127760SGiacomo.Gabrielli@arm.com * neither the name of the copyright holders nor the names of its 137760SGiacomo.Gabrielli@arm.com * contributors may be used to endorse or promote products derived from 141762SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A * 282SN/A * Authors: Nathan Binkert 292SN/A */ 302SN/A 312SN/A/** 322SN/A * @file 332SN/A * Defines SMT_MAX_THREADS. 342SN/A */ 352SN/A 362SN/A#ifndef __SMT_HH__ 372SN/A#define __SMT_HH__ 382SN/A 392665Ssaidi@eecs.umich.edu#ifndef SMT_MAX_THREADS 404762Snate@binkert.org/** The number of TPUs in any processor. */ 412SN/A#define SMT_MAX_THREADS 4 422SN/A#endif 432410SN/A 442410SN/A/** 452SN/A * The maximum number of active threads across all cpus. Used to 464762Snate@binkert.org * initialize per-thread statistics in the cache. 474762Snate@binkert.org * 484762Snate@binkert.org * NB: Be careful to only use it once all the CPUs that you care about 494762Snate@binkert.org * have been initialized 504762Snate@binkert.org */ 512SN/Aextern int maxThreadsPerCPU; 524762Snate@binkert.org 534762Snate@binkert.org/** 542SN/A * Changes the status and priority of the thread with the given number. 5510814Sandreas.hansson@arm.com * @param tid The thread to change. 5610814Sandreas.hansson@arm.com * @param activate The new active status. 5710814Sandreas.hansson@arm.com * @param priority The new priority. 5810814Sandreas.hansson@arm.com */ 5910814Sandreas.hansson@arm.comvoid change_thread_state(ThreadID tid, int activate, int priority); 6010814Sandreas.hansson@arm.com 6110814Sandreas.hansson@arm.com#endif // __SMT_HH__ 6211683Sfernando.endo2@gmail.com