smt.hh revision 2665
12131SN/A/* 22131SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32131SN/A * All rights reserved. 42131SN/A * 52131SN/A * Redistribution and use in source and binary forms, with or without 62131SN/A * modification, are permitted provided that the following conditions are 72131SN/A * met: redistributions of source code must retain the above copyright 82131SN/A * notice, this list of conditions and the following disclaimer; 92131SN/A * redistributions in binary form must reproduce the above copyright 102131SN/A * notice, this list of conditions and the following disclaimer in the 112131SN/A * documentation and/or other materials provided with the distribution; 122131SN/A * neither the name of the copyright holders nor the names of its 132131SN/A * contributors may be used to endorse or promote products derived from 142131SN/A * this software without specific prior written permission. 152131SN/A * 162131SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172131SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182131SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192131SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202131SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212131SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222131SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232131SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242131SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252131SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262131SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292131SN/A */ 302131SN/A 312239SN/A/** 322680Sktlim@umich.edu * @file 332447SN/A * Defines SMT_MAX_THREADS. 342447SN/A */ 352131SN/A 362447SN/A#ifndef __SMT_HH__ 372447SN/A#define __SMT_HH__ 382131SN/A 392479SN/A#ifndef SMT_MAX_THREADS 402447SN/A/** The number of TPUs in any processor. */ 412447SN/A#define SMT_MAX_THREADS 4 422131SN/A#endif 432479SN/A 442447SN/A/** 452447SN/A * The maximum number of active threads across all cpus. Used to 462447SN/A * initialize per-thread statistics in the cache. 472447SN/A * 482447SN/A * NB: Be careful to only use it once all the CPUs that you care about 492447SN/A * have been initialized 502447SN/A */ 512447SN/Aextern int maxThreadsPerCPU; 522447SN/A 532447SN/A/** 542447SN/A * Changes the status and priority of the thread with the given number. 552447SN/A * @param thread_number The thread to change. 562447SN/A * @param activate The new active status. 572447SN/A * @param priority The new priority. 582447SN/A */ 592447SN/Avoid change_thread_state(int thread_number, int activate, int priority); 602447SN/A 612447SN/A#endif // __SMT_HH__ 622447SN/A