simple_thread.hh revision 9428:029dfe6324d3
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 * Nathan Binkert 42 */ 43 44#ifndef __CPU_SIMPLE_THREAD_HH__ 45#define __CPU_SIMPLE_THREAD_HH__ 46 47#include "arch/decoder.hh" 48#include "arch/isa.hh" 49#include "arch/isa_traits.hh" 50#include "arch/registers.hh" 51#include "arch/tlb.hh" 52#include "arch/types.hh" 53#include "base/types.hh" 54#include "config/the_isa.hh" 55#include "cpu/thread_context.hh" 56#include "cpu/thread_state.hh" 57#include "debug/FloatRegs.hh" 58#include "debug/IntRegs.hh" 59#include "mem/page_table.hh" 60#include "mem/request.hh" 61#include "sim/byteswap.hh" 62#include "sim/eventq.hh" 63#include "sim/process.hh" 64#include "sim/serialize.hh" 65#include "sim/system.hh" 66 67class BaseCPU; 68class CheckerCPU; 69 70class FunctionProfile; 71class ProfileNode; 72 73namespace TheISA { 74 namespace Kernel { 75 class Statistics; 76 } 77} 78 79/** 80 * The SimpleThread object provides a combination of the ThreadState 81 * object and the ThreadContext interface. It implements the 82 * ThreadContext interface so that a ProxyThreadContext class can be 83 * made using SimpleThread as the template parameter (see 84 * thread_context.hh). It adds to the ThreadState object by adding all 85 * the objects needed for simple functional execution, including a 86 * simple architectural register file, and pointers to the ITB and DTB 87 * in full system mode. For CPU models that do not need more advanced 88 * ways to hold state (i.e. a separate physical register file, or 89 * separate fetch and commit PC's), this SimpleThread class provides 90 * all the necessary state for full architecture-level functional 91 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 92 * examples. 93 */ 94 95class SimpleThread : public ThreadState 96{ 97 protected: 98 typedef TheISA::MachInst MachInst; 99 typedef TheISA::MiscReg MiscReg; 100 typedef TheISA::FloatReg FloatReg; 101 typedef TheISA::FloatRegBits FloatRegBits; 102 public: 103 typedef ThreadContext::Status Status; 104 105 protected: 106 union { 107 FloatReg f[TheISA::NumFloatRegs]; 108 FloatRegBits i[TheISA::NumFloatRegs]; 109 } floatRegs; 110 TheISA::IntReg intRegs[TheISA::NumIntRegs]; 111 TheISA::ISA *const isa; // one "instance" of the current ISA. 112 113 TheISA::PCState _pcState; 114 115 /** Did this instruction execute or is it predicated false */ 116 bool predicate; 117 118 public: 119 std::string name() const 120 { 121 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 122 } 123 124 ProxyThreadContext<SimpleThread> *tc; 125 126 System *system; 127 128 TheISA::TLB *itb; 129 TheISA::TLB *dtb; 130 131 TheISA::Decoder decoder; 132 133 // constructor: initialize SimpleThread from given process structure 134 // FS 135 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 136 TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa, 137 bool use_kernel_stats = true); 138 // SE 139 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 140 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb, 141 TheISA::ISA *_isa); 142 143 virtual ~SimpleThread(); 144 145 virtual void takeOverFrom(ThreadContext *oldContext); 146 147 void regStats(const std::string &name); 148 149 void copyTC(ThreadContext *context); 150 151 void copyState(ThreadContext *oldContext); 152 153 void serialize(std::ostream &os); 154 void unserialize(Checkpoint *cp, const std::string §ion); 155 156 /*************************************************************** 157 * SimpleThread functions to provide CPU with access to various 158 * state. 159 **************************************************************/ 160 161 /** Returns the pointer to this SimpleThread's ThreadContext. Used 162 * when a ThreadContext must be passed to objects outside of the 163 * CPU. 164 */ 165 ThreadContext *getTC() { return tc; } 166 167 void demapPage(Addr vaddr, uint64_t asn) 168 { 169 itb->demapPage(vaddr, asn); 170 dtb->demapPage(vaddr, asn); 171 } 172 173 void demapInstPage(Addr vaddr, uint64_t asn) 174 { 175 itb->demapPage(vaddr, asn); 176 } 177 178 void demapDataPage(Addr vaddr, uint64_t asn) 179 { 180 dtb->demapPage(vaddr, asn); 181 } 182 183 void dumpFuncProfile(); 184 185 Fault hwrei(); 186 187 bool simPalCheck(int palFunc); 188 189 /******************************************* 190 * ThreadContext interface functions. 191 ******************************************/ 192 193 BaseCPU *getCpuPtr() { return baseCpu; } 194 195 TheISA::TLB *getITBPtr() { return itb; } 196 197 TheISA::TLB *getDTBPtr() { return dtb; } 198 199 CheckerCPU *getCheckerCpuPtr() { return NULL; } 200 201 TheISA::Decoder *getDecoderPtr() { return &decoder; } 202 203 System *getSystemPtr() { return system; } 204 205 Status status() const { return _status; } 206 207 void setStatus(Status newStatus) { _status = newStatus; } 208 209 /// Set the status to Active. Optional delay indicates number of 210 /// cycles to wait before beginning execution. 211 void activate(Cycles delay = Cycles(1)); 212 213 /// Set the status to Suspended. 214 void suspend(); 215 216 /// Set the status to Halted. 217 void halt(); 218 219 virtual bool misspeculating(); 220 221 void copyArchRegs(ThreadContext *tc); 222 223 void clearArchRegs() 224 { 225 _pcState = 0; 226 memset(intRegs, 0, sizeof(intRegs)); 227 memset(floatRegs.i, 0, sizeof(floatRegs.i)); 228 isa->clear(); 229 } 230 231 // 232 // New accessors for new decoder. 233 // 234 uint64_t readIntReg(int reg_idx) 235 { 236 int flatIndex = isa->flattenIntIndex(reg_idx); 237 assert(flatIndex < TheISA::NumIntRegs); 238 uint64_t regVal(readIntRegFlat(flatIndex)); 239 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 240 reg_idx, flatIndex, regVal); 241 return regVal; 242 } 243 244 FloatReg readFloatReg(int reg_idx) 245 { 246 int flatIndex = isa->flattenFloatIndex(reg_idx); 247 assert(flatIndex < TheISA::NumFloatRegs); 248 FloatReg regVal(readFloatRegFlat(flatIndex)); 249 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 250 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 251 return regVal; 252 } 253 254 FloatRegBits readFloatRegBits(int reg_idx) 255 { 256 int flatIndex = isa->flattenFloatIndex(reg_idx); 257 assert(flatIndex < TheISA::NumFloatRegs); 258 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); 259 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 260 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 261 return regVal; 262 } 263 264 void setIntReg(int reg_idx, uint64_t val) 265 { 266 int flatIndex = isa->flattenIntIndex(reg_idx); 267 assert(flatIndex < TheISA::NumIntRegs); 268 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 269 reg_idx, flatIndex, val); 270 setIntRegFlat(flatIndex, val); 271 } 272 273 void setFloatReg(int reg_idx, FloatReg val) 274 { 275 int flatIndex = isa->flattenFloatIndex(reg_idx); 276 assert(flatIndex < TheISA::NumFloatRegs); 277 setFloatRegFlat(flatIndex, val); 278 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 279 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 280 } 281 282 void setFloatRegBits(int reg_idx, FloatRegBits val) 283 { 284 int flatIndex = isa->flattenFloatIndex(reg_idx); 285 assert(flatIndex < TheISA::NumFloatRegs); 286 // XXX: Fix array out of bounds compiler error for gem5.fast 287 // when checkercpu enabled 288 if (flatIndex < TheISA::NumFloatRegs) 289 setFloatRegBitsFlat(flatIndex, val); 290 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 291 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 292 } 293 294 TheISA::PCState 295 pcState() 296 { 297 return _pcState; 298 } 299 300 void 301 pcState(const TheISA::PCState &val) 302 { 303 _pcState = val; 304 } 305 306 void 307 pcStateNoRecord(const TheISA::PCState &val) 308 { 309 _pcState = val; 310 } 311 312 Addr 313 instAddr() 314 { 315 return _pcState.instAddr(); 316 } 317 318 Addr 319 nextInstAddr() 320 { 321 return _pcState.nextInstAddr(); 322 } 323 324 MicroPC 325 microPC() 326 { 327 return _pcState.microPC(); 328 } 329 330 bool readPredicate() 331 { 332 return predicate; 333 } 334 335 void setPredicate(bool val) 336 { 337 predicate = val; 338 } 339 340 MiscReg 341 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 342 { 343 return isa->readMiscRegNoEffect(misc_reg); 344 } 345 346 MiscReg 347 readMiscReg(int misc_reg, ThreadID tid = 0) 348 { 349 return isa->readMiscReg(misc_reg, tc); 350 } 351 352 void 353 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 354 { 355 return isa->setMiscRegNoEffect(misc_reg, val); 356 } 357 358 void 359 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 360 { 361 return isa->setMiscReg(misc_reg, val, tc); 362 } 363 364 int 365 flattenIntIndex(int reg) 366 { 367 return isa->flattenIntIndex(reg); 368 } 369 370 int 371 flattenFloatIndex(int reg) 372 { 373 return isa->flattenFloatIndex(reg); 374 } 375 376 unsigned readStCondFailures() { return storeCondFailures; } 377 378 void setStCondFailures(unsigned sc_failures) 379 { storeCondFailures = sc_failures; } 380 381 void syscall(int64_t callnum) 382 { 383 process->syscall(callnum, tc); 384 } 385 386 uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } 387 void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } 388 389 FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; } 390 void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; } 391 392 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; } 393 void setFloatRegBitsFlat(int idx, FloatRegBits val) { 394 floatRegs.i[idx] = val; 395 } 396 397}; 398 399 400// for non-speculative execution context, spec_mode is always false 401inline bool 402SimpleThread::misspeculating() 403{ 404 return false; 405} 406 407#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 408