simple_thread.hh revision 8809:bb10807da889
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 * Nathan Binkert 42 */ 43 44#ifndef __CPU_SIMPLE_THREAD_HH__ 45#define __CPU_SIMPLE_THREAD_HH__ 46 47#include "arch/isa.hh" 48#include "arch/isa_traits.hh" 49#include "arch/registers.hh" 50#include "arch/tlb.hh" 51#include "arch/types.hh" 52#include "base/types.hh" 53#include "config/the_isa.hh" 54#include "config/use_checker.hh" 55#include "cpu/decode.hh" 56#include "cpu/thread_context.hh" 57#include "cpu/thread_state.hh" 58#include "debug/FloatRegs.hh" 59#include "debug/IntRegs.hh" 60#include "mem/page_table.hh" 61#include "mem/request.hh" 62#include "sim/byteswap.hh" 63#include "sim/eventq.hh" 64#include "sim/process.hh" 65#include "sim/serialize.hh" 66#include "sim/system.hh" 67 68class BaseCPU; 69 70 71class FunctionProfile; 72class ProfileNode; 73 74namespace TheISA { 75 namespace Kernel { 76 class Statistics; 77 }; 78}; 79 80/** 81 * The SimpleThread object provides a combination of the ThreadState 82 * object and the ThreadContext interface. It implements the 83 * ThreadContext interface so that a ProxyThreadContext class can be 84 * made using SimpleThread as the template parameter (see 85 * thread_context.hh). It adds to the ThreadState object by adding all 86 * the objects needed for simple functional execution, including a 87 * simple architectural register file, and pointers to the ITB and DTB 88 * in full system mode. For CPU models that do not need more advanced 89 * ways to hold state (i.e. a separate physical register file, or 90 * separate fetch and commit PC's), this SimpleThread class provides 91 * all the necessary state for full architecture-level functional 92 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 93 * examples. 94 */ 95 96class SimpleThread : public ThreadState 97{ 98 protected: 99 typedef TheISA::MachInst MachInst; 100 typedef TheISA::MiscReg MiscReg; 101 typedef TheISA::FloatReg FloatReg; 102 typedef TheISA::FloatRegBits FloatRegBits; 103 public: 104 typedef ThreadContext::Status Status; 105 106 protected: 107 union { 108 FloatReg f[TheISA::NumFloatRegs]; 109 FloatRegBits i[TheISA::NumFloatRegs]; 110 } floatRegs; 111 TheISA::IntReg intRegs[TheISA::NumIntRegs]; 112 TheISA::ISA isa; // one "instance" of the current ISA. 113 114 TheISA::PCState _pcState; 115 116 /** Did this instruction execute or is it predicated false */ 117 bool predicate; 118 119 public: 120 std::string name() const 121 { 122 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 123 } 124 125 ProxyThreadContext<SimpleThread> *tc; 126 127 System *system; 128 129 TheISA::TLB *itb; 130 TheISA::TLB *dtb; 131 132 Decoder decoder; 133 134 // constructor: initialize SimpleThread from given process structure 135 // FS 136 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 137 TheISA::TLB *_itb, TheISA::TLB *_dtb, 138 bool use_kernel_stats = true); 139 // SE 140 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 141 TheISA::TLB *_itb, TheISA::TLB *_dtb); 142 143 SimpleThread(); 144 145 virtual ~SimpleThread(); 146 147 virtual void takeOverFrom(ThreadContext *oldContext); 148 149 void regStats(const std::string &name); 150 151 void copyTC(ThreadContext *context); 152 153 void copyState(ThreadContext *oldContext); 154 155 void serialize(std::ostream &os); 156 void unserialize(Checkpoint *cp, const std::string §ion); 157 158 /*************************************************************** 159 * SimpleThread functions to provide CPU with access to various 160 * state. 161 **************************************************************/ 162 163 /** Returns the pointer to this SimpleThread's ThreadContext. Used 164 * when a ThreadContext must be passed to objects outside of the 165 * CPU. 166 */ 167 ThreadContext *getTC() { return tc; } 168 169 void demapPage(Addr vaddr, uint64_t asn) 170 { 171 itb->demapPage(vaddr, asn); 172 dtb->demapPage(vaddr, asn); 173 } 174 175 void demapInstPage(Addr vaddr, uint64_t asn) 176 { 177 itb->demapPage(vaddr, asn); 178 } 179 180 void demapDataPage(Addr vaddr, uint64_t asn) 181 { 182 dtb->demapPage(vaddr, asn); 183 } 184 185 void dumpFuncProfile(); 186 187 Fault hwrei(); 188 189 bool simPalCheck(int palFunc); 190 191 /******************************************* 192 * ThreadContext interface functions. 193 ******************************************/ 194 195 BaseCPU *getCpuPtr() { return baseCpu; } 196 197 TheISA::TLB *getITBPtr() { return itb; } 198 199 TheISA::TLB *getDTBPtr() { return dtb; } 200 201#if USE_CHECKER 202 BaseCPU *getCheckerCpuPtr() { return NULL; } 203#endif 204 205 Decoder *getDecoderPtr() { return &decoder; } 206 207 System *getSystemPtr() { return system; } 208 209 PortProxy* getPhysProxy() { return physProxy; } 210 211 /** Return a virtual port. This port cannot be cached locally in an object. 212 * After a CPU switch it may point to the wrong memory object which could 213 * mean stale data. 214 */ 215 FSTranslatingPortProxy* getVirtProxy() { return virtProxy; } 216 217 Status status() const { return _status; } 218 219 void setStatus(Status newStatus) { _status = newStatus; } 220 221 /// Set the status to Active. Optional delay indicates number of 222 /// cycles to wait before beginning execution. 223 void activate(int delay = 1); 224 225 /// Set the status to Suspended. 226 void suspend(); 227 228 /// Set the status to Halted. 229 void halt(); 230 231 virtual bool misspeculating(); 232 233 void copyArchRegs(ThreadContext *tc); 234 235 void clearArchRegs() 236 { 237 _pcState = 0; 238 memset(intRegs, 0, sizeof(intRegs)); 239 memset(floatRegs.i, 0, sizeof(floatRegs.i)); 240 isa.clear(); 241 } 242 243 // 244 // New accessors for new decoder. 245 // 246 uint64_t readIntReg(int reg_idx) 247 { 248 int flatIndex = isa.flattenIntIndex(reg_idx); 249 assert(flatIndex < TheISA::NumIntRegs); 250 uint64_t regVal = intRegs[flatIndex]; 251 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 252 reg_idx, flatIndex, regVal); 253 return regVal; 254 } 255 256 FloatReg readFloatReg(int reg_idx) 257 { 258 int flatIndex = isa.flattenFloatIndex(reg_idx); 259 assert(flatIndex < TheISA::NumFloatRegs); 260 FloatReg regVal = floatRegs.f[flatIndex]; 261 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 262 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 263 return regVal; 264 } 265 266 FloatRegBits readFloatRegBits(int reg_idx) 267 { 268 int flatIndex = isa.flattenFloatIndex(reg_idx); 269 assert(flatIndex < TheISA::NumFloatRegs); 270 FloatRegBits regVal = floatRegs.i[flatIndex]; 271 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 272 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 273 return regVal; 274 } 275 276 void setIntReg(int reg_idx, uint64_t val) 277 { 278 int flatIndex = isa.flattenIntIndex(reg_idx); 279 assert(flatIndex < TheISA::NumIntRegs); 280 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 281 reg_idx, flatIndex, val); 282 intRegs[flatIndex] = val; 283 } 284 285 void setFloatReg(int reg_idx, FloatReg val) 286 { 287 int flatIndex = isa.flattenFloatIndex(reg_idx); 288 assert(flatIndex < TheISA::NumFloatRegs); 289 floatRegs.f[flatIndex] = val; 290 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 291 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 292 } 293 294 void setFloatRegBits(int reg_idx, FloatRegBits val) 295 { 296 int flatIndex = isa.flattenFloatIndex(reg_idx); 297 assert(flatIndex < TheISA::NumFloatRegs); 298 // XXX: Fix array out of bounds compiler error for gem5.fast 299 // when checkercpu enabled 300 if (flatIndex < TheISA::NumFloatRegs) 301 floatRegs.i[flatIndex] = val; 302 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 303 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 304 } 305 306 TheISA::PCState 307 pcState() 308 { 309 return _pcState; 310 } 311 312 void 313 pcState(const TheISA::PCState &val) 314 { 315 _pcState = val; 316 } 317 318#if USE_CHECKER 319 void 320 pcStateNoRecord(const TheISA::PCState &val) 321 { 322 _pcState = val; 323 } 324#endif 325 326 Addr 327 instAddr() 328 { 329 return _pcState.instAddr(); 330 } 331 332 Addr 333 nextInstAddr() 334 { 335 return _pcState.nextInstAddr(); 336 } 337 338 MicroPC 339 microPC() 340 { 341 return _pcState.microPC(); 342 } 343 344 bool readPredicate() 345 { 346 return predicate; 347 } 348 349 void setPredicate(bool val) 350 { 351 predicate = val; 352 } 353 354 MiscReg 355 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 356 { 357 return isa.readMiscRegNoEffect(misc_reg); 358 } 359 360 MiscReg 361 readMiscReg(int misc_reg, ThreadID tid = 0) 362 { 363 return isa.readMiscReg(misc_reg, tc); 364 } 365 366 void 367 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 368 { 369 return isa.setMiscRegNoEffect(misc_reg, val); 370 } 371 372 void 373 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 374 { 375 return isa.setMiscReg(misc_reg, val, tc); 376 } 377 378 int 379 flattenIntIndex(int reg) 380 { 381 return isa.flattenIntIndex(reg); 382 } 383 384 int 385 flattenFloatIndex(int reg) 386 { 387 return isa.flattenFloatIndex(reg); 388 } 389 390 unsigned readStCondFailures() { return storeCondFailures; } 391 392 void setStCondFailures(unsigned sc_failures) 393 { storeCondFailures = sc_failures; } 394 395 void syscall(int64_t callnum) 396 { 397 process->syscall(callnum, tc); 398 } 399}; 400 401 402// for non-speculative execution context, spec_mode is always false 403inline bool 404SimpleThread::misspeculating() 405{ 406 return false; 407} 408 409#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 410