simple_thread.hh revision 8808:8af87554ad7e 
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa.hh"
36#include "arch/isa_traits.hh"
37#include "arch/registers.hh"
38#include "arch/tlb.hh"
39#include "arch/types.hh"
40#include "base/types.hh"
41#include "config/the_isa.hh"
42#include "cpu/decode.hh"
43#include "cpu/thread_context.hh"
44#include "cpu/thread_state.hh"
45#include "debug/FloatRegs.hh"
46#include "debug/IntRegs.hh"
47#include "mem/page_table.hh"
48#include "mem/request.hh"
49#include "sim/byteswap.hh"
50#include "sim/eventq.hh"
51#include "sim/process.hh"
52#include "sim/serialize.hh"
53#include "sim/system.hh"
54
55class BaseCPU;
56
57
58class FunctionProfile;
59class ProfileNode;
60
61namespace TheISA {
62    namespace Kernel {
63        class Statistics;
64    };
65};
66
67/**
68 * The SimpleThread object provides a combination of the ThreadState
69 * object and the ThreadContext interface. It implements the
70 * ThreadContext interface so that a ProxyThreadContext class can be
71 * made using SimpleThread as the template parameter (see
72 * thread_context.hh). It adds to the ThreadState object by adding all
73 * the objects needed for simple functional execution, including a
74 * simple architectural register file, and pointers to the ITB and DTB
75 * in full system mode. For CPU models that do not need more advanced
76 * ways to hold state (i.e. a separate physical register file, or
77 * separate fetch and commit PC's), this SimpleThread class provides
78 * all the necessary state for full architecture-level functional
79 * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
80 * examples.
81 */
82
83class SimpleThread : public ThreadState
84{
85  protected:
86    typedef TheISA::MachInst MachInst;
87    typedef TheISA::MiscReg MiscReg;
88    typedef TheISA::FloatReg FloatReg;
89    typedef TheISA::FloatRegBits FloatRegBits;
90  public:
91    typedef ThreadContext::Status Status;
92
93  protected:
94    union {
95        FloatReg f[TheISA::NumFloatRegs];
96        FloatRegBits i[TheISA::NumFloatRegs];
97    } floatRegs;
98    TheISA::IntReg intRegs[TheISA::NumIntRegs];
99    TheISA::ISA isa;    // one "instance" of the current ISA.
100
101    TheISA::PCState _pcState;
102
103    /** Did this instruction execute or is it predicated false */
104    bool predicate;
105
106  public:
107    std::string name() const
108    {
109        return csprintf("%s.[tid:%i]", cpu->name(), tc->threadId());
110    }
111
112    // pointer to CPU associated with this SimpleThread
113    BaseCPU *cpu;
114
115    ProxyThreadContext<SimpleThread> *tc;
116
117    System *system;
118
119    TheISA::TLB *itb;
120    TheISA::TLB *dtb;
121
122    Decoder decoder;
123
124    // constructor: initialize SimpleThread from given process structure
125    // FS
126    SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
127                 TheISA::TLB *_itb, TheISA::TLB *_dtb,
128                 bool use_kernel_stats = true);
129    // SE
130    SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
131                 TheISA::TLB *_itb, TheISA::TLB *_dtb);
132
133    SimpleThread();
134
135    virtual ~SimpleThread();
136
137    virtual void takeOverFrom(ThreadContext *oldContext);
138
139    void regStats(const std::string &name);
140
141    void copyTC(ThreadContext *context);
142
143    void copyState(ThreadContext *oldContext);
144
145    void serialize(std::ostream &os);
146    void unserialize(Checkpoint *cp, const std::string &section);
147
148    /***************************************************************
149     *  SimpleThread functions to provide CPU with access to various
150     *  state.
151     **************************************************************/
152
153    /** Returns the pointer to this SimpleThread's ThreadContext. Used
154     *  when a ThreadContext must be passed to objects outside of the
155     *  CPU.
156     */
157    ThreadContext *getTC() { return tc; }
158
159    void demapPage(Addr vaddr, uint64_t asn)
160    {
161        itb->demapPage(vaddr, asn);
162        dtb->demapPage(vaddr, asn);
163    }
164
165    void demapInstPage(Addr vaddr, uint64_t asn)
166    {
167        itb->demapPage(vaddr, asn);
168    }
169
170    void demapDataPage(Addr vaddr, uint64_t asn)
171    {
172        dtb->demapPage(vaddr, asn);
173    }
174
175    void dumpFuncProfile();
176
177    Fault hwrei();
178
179    bool simPalCheck(int palFunc);
180
181    /*******************************************
182     * ThreadContext interface functions.
183     ******************************************/
184
185    BaseCPU *getCpuPtr() { return cpu; }
186
187    TheISA::TLB *getITBPtr() { return itb; }
188
189    TheISA::TLB *getDTBPtr() { return dtb; }
190
191    Decoder *getDecoderPtr() { return &decoder; }
192
193    System *getSystemPtr() { return system; }
194
195    PortProxy* getPhysProxy() { return physProxy; }
196
197    /** Return a virtual port. This port cannot be cached locally in an object.
198     * After a CPU switch it may point to the wrong memory object which could
199     * mean stale data.
200     */
201    FSTranslatingPortProxy* getVirtProxy() { return virtProxy; }
202
203    Status status() const { return _status; }
204
205    void setStatus(Status newStatus) { _status = newStatus; }
206
207    /// Set the status to Active.  Optional delay indicates number of
208    /// cycles to wait before beginning execution.
209    void activate(int delay = 1);
210
211    /// Set the status to Suspended.
212    void suspend();
213
214    /// Set the status to Halted.
215    void halt();
216
217    virtual bool misspeculating();
218
219    void copyArchRegs(ThreadContext *tc);
220
221    void clearArchRegs()
222    {
223        _pcState = 0;
224        memset(intRegs, 0, sizeof(intRegs));
225        memset(floatRegs.i, 0, sizeof(floatRegs.i));
226        isa.clear();
227    }
228
229    //
230    // New accessors for new decoder.
231    //
232    uint64_t readIntReg(int reg_idx)
233    {
234        int flatIndex = isa.flattenIntIndex(reg_idx);
235        assert(flatIndex < TheISA::NumIntRegs);
236        uint64_t regVal = intRegs[flatIndex];
237        DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
238                reg_idx, flatIndex, regVal);
239        return regVal;
240    }
241
242    FloatReg readFloatReg(int reg_idx)
243    {
244        int flatIndex = isa.flattenFloatIndex(reg_idx);
245        assert(flatIndex < TheISA::NumFloatRegs);
246        FloatReg regVal = floatRegs.f[flatIndex];
247        DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
248                reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
249        return regVal;
250    }
251
252    FloatRegBits readFloatRegBits(int reg_idx)
253    {
254        int flatIndex = isa.flattenFloatIndex(reg_idx);
255        assert(flatIndex < TheISA::NumFloatRegs);
256        FloatRegBits regVal = floatRegs.i[flatIndex];
257        DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
258                reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
259        return regVal;
260    }
261
262    void setIntReg(int reg_idx, uint64_t val)
263    {
264        int flatIndex = isa.flattenIntIndex(reg_idx);
265        assert(flatIndex < TheISA::NumIntRegs);
266        DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
267                reg_idx, flatIndex, val);
268        intRegs[flatIndex] = val;
269    }
270
271    void setFloatReg(int reg_idx, FloatReg val)
272    {
273        int flatIndex = isa.flattenFloatIndex(reg_idx);
274        assert(flatIndex < TheISA::NumFloatRegs);
275        floatRegs.f[flatIndex] = val;
276        DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
277                reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
278    }
279
280    void setFloatRegBits(int reg_idx, FloatRegBits val)
281    {
282        int flatIndex = isa.flattenFloatIndex(reg_idx);
283        assert(flatIndex < TheISA::NumFloatRegs);
284        floatRegs.i[flatIndex] = val;
285        DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
286                reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
287    }
288
289    TheISA::PCState
290    pcState()
291    {
292        return _pcState;
293    }
294
295    void
296    pcState(const TheISA::PCState &val)
297    {
298        _pcState = val;
299    }
300
301    Addr
302    instAddr()
303    {
304        return _pcState.instAddr();
305    }
306
307    Addr
308    nextInstAddr()
309    {
310        return _pcState.nextInstAddr();
311    }
312
313    MicroPC
314    microPC()
315    {
316        return _pcState.microPC();
317    }
318
319    bool readPredicate()
320    {
321        return predicate;
322    }
323
324    void setPredicate(bool val)
325    {
326        predicate = val;
327    }
328
329    MiscReg
330    readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
331    {
332        return isa.readMiscRegNoEffect(misc_reg);
333    }
334
335    MiscReg
336    readMiscReg(int misc_reg, ThreadID tid = 0)
337    {
338        return isa.readMiscReg(misc_reg, tc);
339    }
340
341    void
342    setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
343    {
344        return isa.setMiscRegNoEffect(misc_reg, val);
345    }
346
347    void
348    setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
349    {
350        return isa.setMiscReg(misc_reg, val, tc);
351    }
352
353    int
354    flattenIntIndex(int reg)
355    {
356        return isa.flattenIntIndex(reg);
357    }
358
359    int
360    flattenFloatIndex(int reg)
361    {
362        return isa.flattenFloatIndex(reg);
363    }
364
365    unsigned readStCondFailures() { return storeCondFailures; }
366
367    void setStCondFailures(unsigned sc_failures)
368    { storeCondFailures = sc_failures; }
369
370    void syscall(int64_t callnum)
371    {
372        process->syscall(callnum, tc);
373    }
374};
375
376
377// for non-speculative execution context, spec_mode is always false
378inline bool
379SimpleThread::misspeculating()
380{
381    return false;
382}
383
384#endif // __CPU_CPU_EXEC_CONTEXT_HH__
385