simple_thread.hh revision 8799:dac1e33e07b0 
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa.hh"
36#include "arch/isa_traits.hh"
37#include "arch/registers.hh"
38#include "arch/tlb.hh"
39#include "arch/types.hh"
40#include "base/types.hh"
41#include "config/the_isa.hh"
42#include "cpu/decode.hh"
43#include "cpu/thread_context.hh"
44#include "cpu/thread_state.hh"
45#include "debug/FloatRegs.hh"
46#include "debug/IntRegs.hh"
47#include "mem/page_table.hh"
48#include "mem/request.hh"
49#include "sim/byteswap.hh"
50#include "sim/eventq.hh"
51#include "sim/process.hh"
52#include "sim/serialize.hh"
53#include "sim/system.hh"
54
55class BaseCPU;
56
57
58class FunctionProfile;
59class ProfileNode;
60class PhysicalPort;
61class TranslatingPort;
62
63namespace TheISA {
64    namespace Kernel {
65        class Statistics;
66    };
67};
68
69/**
70 * The SimpleThread object provides a combination of the ThreadState
71 * object and the ThreadContext interface. It implements the
72 * ThreadContext interface so that a ProxyThreadContext class can be
73 * made using SimpleThread as the template parameter (see
74 * thread_context.hh). It adds to the ThreadState object by adding all
75 * the objects needed for simple functional execution, including a
76 * simple architectural register file, and pointers to the ITB and DTB
77 * in full system mode. For CPU models that do not need more advanced
78 * ways to hold state (i.e. a separate physical register file, or
79 * separate fetch and commit PC's), this SimpleThread class provides
80 * all the necessary state for full architecture-level functional
81 * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
82 * examples.
83 */
84
85class SimpleThread : public ThreadState
86{
87  protected:
88    typedef TheISA::MachInst MachInst;
89    typedef TheISA::MiscReg MiscReg;
90    typedef TheISA::FloatReg FloatReg;
91    typedef TheISA::FloatRegBits FloatRegBits;
92  public:
93    typedef ThreadContext::Status Status;
94
95  protected:
96    union {
97        FloatReg f[TheISA::NumFloatRegs];
98        FloatRegBits i[TheISA::NumFloatRegs];
99    } floatRegs;
100    TheISA::IntReg intRegs[TheISA::NumIntRegs];
101    TheISA::ISA isa;    // one "instance" of the current ISA.
102
103    TheISA::PCState _pcState;
104
105    /** Did this instruction execute or is it predicated false */
106    bool predicate;
107
108  public:
109    std::string name() const
110    {
111        return csprintf("%s.[tid:%i]", cpu->name(), tc->threadId());
112    }
113
114    // pointer to CPU associated with this SimpleThread
115    BaseCPU *cpu;
116
117    ProxyThreadContext<SimpleThread> *tc;
118
119    System *system;
120
121    TheISA::TLB *itb;
122    TheISA::TLB *dtb;
123
124    Decoder decoder;
125
126    // constructor: initialize SimpleThread from given process structure
127    // FS
128    SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
129                 TheISA::TLB *_itb, TheISA::TLB *_dtb,
130                 bool use_kernel_stats = true);
131    // SE
132    SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
133                 TheISA::TLB *_itb, TheISA::TLB *_dtb);
134
135    SimpleThread();
136
137    virtual ~SimpleThread();
138
139    virtual void takeOverFrom(ThreadContext *oldContext);
140
141    void regStats(const std::string &name);
142
143    void copyTC(ThreadContext *context);
144
145    void copyState(ThreadContext *oldContext);
146
147    void serialize(std::ostream &os);
148    void unserialize(Checkpoint *cp, const std::string &section);
149
150    /***************************************************************
151     *  SimpleThread functions to provide CPU with access to various
152     *  state.
153     **************************************************************/
154
155    /** Returns the pointer to this SimpleThread's ThreadContext. Used
156     *  when a ThreadContext must be passed to objects outside of the
157     *  CPU.
158     */
159    ThreadContext *getTC() { return tc; }
160
161    void demapPage(Addr vaddr, uint64_t asn)
162    {
163        itb->demapPage(vaddr, asn);
164        dtb->demapPage(vaddr, asn);
165    }
166
167    void demapInstPage(Addr vaddr, uint64_t asn)
168    {
169        itb->demapPage(vaddr, asn);
170    }
171
172    void demapDataPage(Addr vaddr, uint64_t asn)
173    {
174        dtb->demapPage(vaddr, asn);
175    }
176
177    void dumpFuncProfile();
178
179    Fault hwrei();
180
181    bool simPalCheck(int palFunc);
182
183    /*******************************************
184     * ThreadContext interface functions.
185     ******************************************/
186
187    BaseCPU *getCpuPtr() { return cpu; }
188
189    TheISA::TLB *getITBPtr() { return itb; }
190
191    TheISA::TLB *getDTBPtr() { return dtb; }
192
193    Decoder *getDecoderPtr() { return &decoder; }
194
195    System *getSystemPtr() { return system; }
196
197    PortProxy* getPhysProxy() { return physProxy; }
198
199    /** Return a virtual port. This port cannot be cached locally in an object.
200     * After a CPU switch it may point to the wrong memory object which could
201     * mean stale data.
202     */
203    FSTranslatingPortProxy* getVirtProxy() { return virtProxy; }
204
205    Status status() const { return _status; }
206
207    void setStatus(Status newStatus) { _status = newStatus; }
208
209    /// Set the status to Active.  Optional delay indicates number of
210    /// cycles to wait before beginning execution.
211    void activate(int delay = 1);
212
213    /// Set the status to Suspended.
214    void suspend();
215
216    /// Set the status to Halted.
217    void halt();
218
219    virtual bool misspeculating();
220
221    void copyArchRegs(ThreadContext *tc);
222
223    void clearArchRegs()
224    {
225        _pcState = 0;
226        memset(intRegs, 0, sizeof(intRegs));
227        memset(floatRegs.i, 0, sizeof(floatRegs.i));
228        isa.clear();
229    }
230
231    //
232    // New accessors for new decoder.
233    //
234    uint64_t readIntReg(int reg_idx)
235    {
236        int flatIndex = isa.flattenIntIndex(reg_idx);
237        assert(flatIndex < TheISA::NumIntRegs);
238        uint64_t regVal = intRegs[flatIndex];
239        DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
240                reg_idx, flatIndex, regVal);
241        return regVal;
242    }
243
244    FloatReg readFloatReg(int reg_idx)
245    {
246        int flatIndex = isa.flattenFloatIndex(reg_idx);
247        assert(flatIndex < TheISA::NumFloatRegs);
248        FloatReg regVal = floatRegs.f[flatIndex];
249        DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
250                reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
251        return regVal;
252    }
253
254    FloatRegBits readFloatRegBits(int reg_idx)
255    {
256        int flatIndex = isa.flattenFloatIndex(reg_idx);
257        assert(flatIndex < TheISA::NumFloatRegs);
258        FloatRegBits regVal = floatRegs.i[flatIndex];
259        DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
260                reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
261        return regVal;
262    }
263
264    void setIntReg(int reg_idx, uint64_t val)
265    {
266        int flatIndex = isa.flattenIntIndex(reg_idx);
267        assert(flatIndex < TheISA::NumIntRegs);
268        DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
269                reg_idx, flatIndex, val);
270        intRegs[flatIndex] = val;
271    }
272
273    void setFloatReg(int reg_idx, FloatReg val)
274    {
275        int flatIndex = isa.flattenFloatIndex(reg_idx);
276        assert(flatIndex < TheISA::NumFloatRegs);
277        floatRegs.f[flatIndex] = val;
278        DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
279                reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
280    }
281
282    void setFloatRegBits(int reg_idx, FloatRegBits val)
283    {
284        int flatIndex = isa.flattenFloatIndex(reg_idx);
285        assert(flatIndex < TheISA::NumFloatRegs);
286        floatRegs.i[flatIndex] = val;
287        DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
288                reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
289    }
290
291    TheISA::PCState
292    pcState()
293    {
294        return _pcState;
295    }
296
297    void
298    pcState(const TheISA::PCState &val)
299    {
300        _pcState = val;
301    }
302
303    Addr
304    instAddr()
305    {
306        return _pcState.instAddr();
307    }
308
309    Addr
310    nextInstAddr()
311    {
312        return _pcState.nextInstAddr();
313    }
314
315    MicroPC
316    microPC()
317    {
318        return _pcState.microPC();
319    }
320
321    bool readPredicate()
322    {
323        return predicate;
324    }
325
326    void setPredicate(bool val)
327    {
328        predicate = val;
329    }
330
331    MiscReg
332    readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
333    {
334        return isa.readMiscRegNoEffect(misc_reg);
335    }
336
337    MiscReg
338    readMiscReg(int misc_reg, ThreadID tid = 0)
339    {
340        return isa.readMiscReg(misc_reg, tc);
341    }
342
343    void
344    setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
345    {
346        return isa.setMiscRegNoEffect(misc_reg, val);
347    }
348
349    void
350    setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
351    {
352        return isa.setMiscReg(misc_reg, val, tc);
353    }
354
355    int
356    flattenIntIndex(int reg)
357    {
358        return isa.flattenIntIndex(reg);
359    }
360
361    int
362    flattenFloatIndex(int reg)
363    {
364        return isa.flattenFloatIndex(reg);
365    }
366
367    unsigned readStCondFailures() { return storeCondFailures; }
368
369    void setStCondFailures(unsigned sc_failures)
370    { storeCondFailures = sc_failures; }
371
372    void syscall(int64_t callnum)
373    {
374        process->syscall(callnum, tc);
375    }
376};
377
378
379// for non-speculative execution context, spec_mode is always false
380inline bool
381SimpleThread::misspeculating()
382{
383    return false;
384}
385
386#endif // __CPU_CPU_EXEC_CONTEXT_HH__
387