simple_thread.hh revision 8793
1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_SIMPLE_THREAD_HH__ 33#define __CPU_SIMPLE_THREAD_HH__ 34 35#include "arch/isa.hh" 36#include "arch/isa_traits.hh" 37#include "arch/registers.hh" 38#include "arch/tlb.hh" 39#include "arch/types.hh" 40#include "base/types.hh" 41#include "config/full_system.hh" 42#include "config/the_isa.hh" 43#include "cpu/decode.hh" 44#include "cpu/thread_context.hh" 45#include "cpu/thread_state.hh" 46#include "debug/FloatRegs.hh" 47#include "debug/IntRegs.hh" 48#include "mem/page_table.hh" 49#include "mem/request.hh" 50#include "sim/byteswap.hh" 51#include "sim/eventq.hh" 52#include "sim/process.hh" 53#include "sim/serialize.hh" 54#include "sim/system.hh" 55 56class BaseCPU; 57 58 59class FunctionProfile; 60class ProfileNode; 61class FunctionalPort; 62class PhysicalPort; 63class TranslatingPort; 64 65namespace TheISA { 66 namespace Kernel { 67 class Statistics; 68 }; 69}; 70 71/** 72 * The SimpleThread object provides a combination of the ThreadState 73 * object and the ThreadContext interface. It implements the 74 * ThreadContext interface so that a ProxyThreadContext class can be 75 * made using SimpleThread as the template parameter (see 76 * thread_context.hh). It adds to the ThreadState object by adding all 77 * the objects needed for simple functional execution, including a 78 * simple architectural register file, and pointers to the ITB and DTB 79 * in full system mode. For CPU models that do not need more advanced 80 * ways to hold state (i.e. a separate physical register file, or 81 * separate fetch and commit PC's), this SimpleThread class provides 82 * all the necessary state for full architecture-level functional 83 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 84 * examples. 85 */ 86 87class SimpleThread : public ThreadState 88{ 89 protected: 90 typedef TheISA::MachInst MachInst; 91 typedef TheISA::MiscReg MiscReg; 92 typedef TheISA::FloatReg FloatReg; 93 typedef TheISA::FloatRegBits FloatRegBits; 94 public: 95 typedef ThreadContext::Status Status; 96 97 protected: 98 union { 99 FloatReg f[TheISA::NumFloatRegs]; 100 FloatRegBits i[TheISA::NumFloatRegs]; 101 } floatRegs; 102 TheISA::IntReg intRegs[TheISA::NumIntRegs]; 103 TheISA::ISA isa; // one "instance" of the current ISA. 104 105 TheISA::PCState _pcState; 106 107 /** Did this instruction execute or is it predicated false */ 108 bool predicate; 109 110 public: 111 std::string name() const 112 { 113 return csprintf("%s.[tid:%i]", cpu->name(), tc->threadId()); 114 } 115 116 // pointer to CPU associated with this SimpleThread 117 BaseCPU *cpu; 118 119 ProxyThreadContext<SimpleThread> *tc; 120 121 System *system; 122 123 TheISA::TLB *itb; 124 TheISA::TLB *dtb; 125 126 Decoder decoder; 127 128 // constructor: initialize SimpleThread from given process structure 129 // FS 130 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 131 TheISA::TLB *_itb, TheISA::TLB *_dtb, 132 bool use_kernel_stats = true); 133 // SE 134 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 135 TheISA::TLB *_itb, TheISA::TLB *_dtb); 136 137 SimpleThread(); 138 139 virtual ~SimpleThread(); 140 141 virtual void takeOverFrom(ThreadContext *oldContext); 142 143 void regStats(const std::string &name); 144 145 void copyTC(ThreadContext *context); 146 147 void copyState(ThreadContext *oldContext); 148 149 void serialize(std::ostream &os); 150 void unserialize(Checkpoint *cp, const std::string §ion); 151 152 /*************************************************************** 153 * SimpleThread functions to provide CPU with access to various 154 * state. 155 **************************************************************/ 156 157 /** Returns the pointer to this SimpleThread's ThreadContext. Used 158 * when a ThreadContext must be passed to objects outside of the 159 * CPU. 160 */ 161 ThreadContext *getTC() { return tc; } 162 163 void demapPage(Addr vaddr, uint64_t asn) 164 { 165 itb->demapPage(vaddr, asn); 166 dtb->demapPage(vaddr, asn); 167 } 168 169 void demapInstPage(Addr vaddr, uint64_t asn) 170 { 171 itb->demapPage(vaddr, asn); 172 } 173 174 void demapDataPage(Addr vaddr, uint64_t asn) 175 { 176 dtb->demapPage(vaddr, asn); 177 } 178 179 void dumpFuncProfile(); 180 181 Fault hwrei(); 182 183 bool simPalCheck(int palFunc); 184 185 /******************************************* 186 * ThreadContext interface functions. 187 ******************************************/ 188 189 BaseCPU *getCpuPtr() { return cpu; } 190 191 TheISA::TLB *getITBPtr() { return itb; } 192 193 TheISA::TLB *getDTBPtr() { return dtb; } 194 195 Decoder *getDecoderPtr() { return &decoder; } 196 197 System *getSystemPtr() { return system; } 198 199 FunctionalPort *getPhysPort() { return physPort; } 200 201 /** Return a virtual port. This port cannot be cached locally in an object. 202 * After a CPU switch it may point to the wrong memory object which could 203 * mean stale data. 204 */ 205 VirtualPort *getVirtPort() { return virtPort; } 206 207 Status status() const { return _status; } 208 209 void setStatus(Status newStatus) { _status = newStatus; } 210 211 /// Set the status to Active. Optional delay indicates number of 212 /// cycles to wait before beginning execution. 213 void activate(int delay = 1); 214 215 /// Set the status to Suspended. 216 void suspend(); 217 218 /// Set the status to Halted. 219 void halt(); 220 221 virtual bool misspeculating(); 222 223 void copyArchRegs(ThreadContext *tc); 224 225 void clearArchRegs() 226 { 227 _pcState = 0; 228 memset(intRegs, 0, sizeof(intRegs)); 229 memset(floatRegs.i, 0, sizeof(floatRegs.i)); 230 isa.clear(); 231 } 232 233 // 234 // New accessors for new decoder. 235 // 236 uint64_t readIntReg(int reg_idx) 237 { 238 int flatIndex = isa.flattenIntIndex(reg_idx); 239 assert(flatIndex < TheISA::NumIntRegs); 240 uint64_t regVal = intRegs[flatIndex]; 241 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 242 reg_idx, flatIndex, regVal); 243 return regVal; 244 } 245 246 FloatReg readFloatReg(int reg_idx) 247 { 248 int flatIndex = isa.flattenFloatIndex(reg_idx); 249 assert(flatIndex < TheISA::NumFloatRegs); 250 FloatReg regVal = floatRegs.f[flatIndex]; 251 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 252 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 253 return regVal; 254 } 255 256 FloatRegBits readFloatRegBits(int reg_idx) 257 { 258 int flatIndex = isa.flattenFloatIndex(reg_idx); 259 assert(flatIndex < TheISA::NumFloatRegs); 260 FloatRegBits regVal = floatRegs.i[flatIndex]; 261 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 262 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 263 return regVal; 264 } 265 266 void setIntReg(int reg_idx, uint64_t val) 267 { 268 int flatIndex = isa.flattenIntIndex(reg_idx); 269 assert(flatIndex < TheISA::NumIntRegs); 270 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 271 reg_idx, flatIndex, val); 272 intRegs[flatIndex] = val; 273 } 274 275 void setFloatReg(int reg_idx, FloatReg val) 276 { 277 int flatIndex = isa.flattenFloatIndex(reg_idx); 278 assert(flatIndex < TheISA::NumFloatRegs); 279 floatRegs.f[flatIndex] = val; 280 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 281 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 282 } 283 284 void setFloatRegBits(int reg_idx, FloatRegBits val) 285 { 286 int flatIndex = isa.flattenFloatIndex(reg_idx); 287 assert(flatIndex < TheISA::NumFloatRegs); 288 floatRegs.i[flatIndex] = val; 289 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 290 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 291 } 292 293 TheISA::PCState 294 pcState() 295 { 296 return _pcState; 297 } 298 299 void 300 pcState(const TheISA::PCState &val) 301 { 302 _pcState = val; 303 } 304 305 Addr 306 instAddr() 307 { 308 return _pcState.instAddr(); 309 } 310 311 Addr 312 nextInstAddr() 313 { 314 return _pcState.nextInstAddr(); 315 } 316 317 MicroPC 318 microPC() 319 { 320 return _pcState.microPC(); 321 } 322 323 bool readPredicate() 324 { 325 return predicate; 326 } 327 328 void setPredicate(bool val) 329 { 330 predicate = val; 331 } 332 333 MiscReg 334 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 335 { 336 return isa.readMiscRegNoEffect(misc_reg); 337 } 338 339 MiscReg 340 readMiscReg(int misc_reg, ThreadID tid = 0) 341 { 342 return isa.readMiscReg(misc_reg, tc); 343 } 344 345 void 346 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 347 { 348 return isa.setMiscRegNoEffect(misc_reg, val); 349 } 350 351 void 352 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 353 { 354 return isa.setMiscReg(misc_reg, val, tc); 355 } 356 357 int 358 flattenIntIndex(int reg) 359 { 360 return isa.flattenIntIndex(reg); 361 } 362 363 int 364 flattenFloatIndex(int reg) 365 { 366 return isa.flattenFloatIndex(reg); 367 } 368 369 unsigned readStCondFailures() { return storeCondFailures; } 370 371 void setStCondFailures(unsigned sc_failures) 372 { storeCondFailures = sc_failures; } 373 374 void syscall(int64_t callnum) 375 { 376 process->syscall(callnum, tc); 377 } 378}; 379 380 381// for non-speculative execution context, spec_mode is always false 382inline bool 383SimpleThread::misspeculating() 384{ 385 return false; 386} 387 388#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 389