simple_thread.hh revision 8777:dd43f1c9fa0a
1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_SIMPLE_THREAD_HH__ 33#define __CPU_SIMPLE_THREAD_HH__ 34 35#include "arch/isa.hh" 36#include "arch/isa_traits.hh" 37#include "arch/registers.hh" 38#include "arch/tlb.hh" 39#include "arch/types.hh" 40#include "base/types.hh" 41#include "config/full_system.hh" 42#include "config/the_isa.hh" 43#include "cpu/decode.hh" 44#include "cpu/thread_context.hh" 45#include "cpu/thread_state.hh" 46#include "debug/FloatRegs.hh" 47#include "debug/IntRegs.hh" 48#include "mem/page_table.hh" 49#include "mem/request.hh" 50#include "sim/byteswap.hh" 51#include "sim/eventq.hh" 52#include "sim/process.hh" 53#include "sim/serialize.hh" 54#include "sim/system.hh" 55 56class BaseCPU; 57 58 59class FunctionProfile; 60class ProfileNode; 61class FunctionalPort; 62class PhysicalPort; 63class TranslatingPort; 64 65namespace TheISA { 66 namespace Kernel { 67 class Statistics; 68 }; 69}; 70 71/** 72 * The SimpleThread object provides a combination of the ThreadState 73 * object and the ThreadContext interface. It implements the 74 * ThreadContext interface so that a ProxyThreadContext class can be 75 * made using SimpleThread as the template parameter (see 76 * thread_context.hh). It adds to the ThreadState object by adding all 77 * the objects needed for simple functional execution, including a 78 * simple architectural register file, and pointers to the ITB and DTB 79 * in full system mode. For CPU models that do not need more advanced 80 * ways to hold state (i.e. a separate physical register file, or 81 * separate fetch and commit PC's), this SimpleThread class provides 82 * all the necessary state for full architecture-level functional 83 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 84 * examples. 85 */ 86 87class SimpleThread : public ThreadState 88{ 89 protected: 90 typedef TheISA::MachInst MachInst; 91 typedef TheISA::MiscReg MiscReg; 92 typedef TheISA::FloatReg FloatReg; 93 typedef TheISA::FloatRegBits FloatRegBits; 94 public: 95 typedef ThreadContext::Status Status; 96 97 protected: 98 union { 99 FloatReg f[TheISA::NumFloatRegs]; 100 FloatRegBits i[TheISA::NumFloatRegs]; 101 } floatRegs; 102 TheISA::IntReg intRegs[TheISA::NumIntRegs]; 103 TheISA::ISA isa; // one "instance" of the current ISA. 104 105 TheISA::PCState _pcState; 106 107 /** Did this instruction execute or is it predicated false */ 108 bool predicate; 109 110 public: 111 std::string name() const 112 { 113 return csprintf("%s.[tid:%i]", cpu->name(), tc->threadId()); 114 } 115 116 // pointer to CPU associated with this SimpleThread 117 BaseCPU *cpu; 118 119 ProxyThreadContext<SimpleThread> *tc; 120 121 System *system; 122 123 TheISA::TLB *itb; 124 TheISA::TLB *dtb; 125 126 Decoder decoder; 127 128 // constructor: initialize SimpleThread from given process structure 129#if FULL_SYSTEM 130 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 131 TheISA::TLB *_itb, TheISA::TLB *_dtb, 132 bool use_kernel_stats = true); 133#else 134 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 135 TheISA::TLB *_itb, TheISA::TLB *_dtb); 136#endif 137 138 SimpleThread(); 139 140 virtual ~SimpleThread(); 141 142 virtual void takeOverFrom(ThreadContext *oldContext); 143 144 void regStats(const std::string &name); 145 146 void copyTC(ThreadContext *context); 147 148 void copyState(ThreadContext *oldContext); 149 150 void serialize(std::ostream &os); 151 void unserialize(Checkpoint *cp, const std::string §ion); 152 153 /*************************************************************** 154 * SimpleThread functions to provide CPU with access to various 155 * state. 156 **************************************************************/ 157 158 /** Returns the pointer to this SimpleThread's ThreadContext. Used 159 * when a ThreadContext must be passed to objects outside of the 160 * CPU. 161 */ 162 ThreadContext *getTC() { return tc; } 163 164 void demapPage(Addr vaddr, uint64_t asn) 165 { 166 itb->demapPage(vaddr, asn); 167 dtb->demapPage(vaddr, asn); 168 } 169 170 void demapInstPage(Addr vaddr, uint64_t asn) 171 { 172 itb->demapPage(vaddr, asn); 173 } 174 175 void demapDataPage(Addr vaddr, uint64_t asn) 176 { 177 dtb->demapPage(vaddr, asn); 178 } 179 180 void dumpFuncProfile(); 181 182 Fault hwrei(); 183 184 bool simPalCheck(int palFunc); 185 186 /******************************************* 187 * ThreadContext interface functions. 188 ******************************************/ 189 190 BaseCPU *getCpuPtr() { return cpu; } 191 192 TheISA::TLB *getITBPtr() { return itb; } 193 194 TheISA::TLB *getDTBPtr() { return dtb; } 195 196 Decoder *getDecoderPtr() { return &decoder; } 197 198 System *getSystemPtr() { return system; } 199 200 FunctionalPort *getPhysPort() { return physPort; } 201 202 /** Return a virtual port. This port cannot be cached locally in an object. 203 * After a CPU switch it may point to the wrong memory object which could 204 * mean stale data. 205 */ 206 VirtualPort *getVirtPort() { return virtPort; } 207 208 Status status() const { return _status; } 209 210 void setStatus(Status newStatus) { _status = newStatus; } 211 212 /// Set the status to Active. Optional delay indicates number of 213 /// cycles to wait before beginning execution. 214 void activate(int delay = 1); 215 216 /// Set the status to Suspended. 217 void suspend(); 218 219 /// Set the status to Halted. 220 void halt(); 221 222 virtual bool misspeculating(); 223 224 void copyArchRegs(ThreadContext *tc); 225 226 void clearArchRegs() 227 { 228 _pcState = 0; 229 memset(intRegs, 0, sizeof(intRegs)); 230 memset(floatRegs.i, 0, sizeof(floatRegs.i)); 231 isa.clear(); 232 } 233 234 // 235 // New accessors for new decoder. 236 // 237 uint64_t readIntReg(int reg_idx) 238 { 239 int flatIndex = isa.flattenIntIndex(reg_idx); 240 assert(flatIndex < TheISA::NumIntRegs); 241 uint64_t regVal = intRegs[flatIndex]; 242 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 243 reg_idx, flatIndex, regVal); 244 return regVal; 245 } 246 247 FloatReg readFloatReg(int reg_idx) 248 { 249 int flatIndex = isa.flattenFloatIndex(reg_idx); 250 assert(flatIndex < TheISA::NumFloatRegs); 251 FloatReg regVal = floatRegs.f[flatIndex]; 252 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 253 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 254 return regVal; 255 } 256 257 FloatRegBits readFloatRegBits(int reg_idx) 258 { 259 int flatIndex = isa.flattenFloatIndex(reg_idx); 260 assert(flatIndex < TheISA::NumFloatRegs); 261 FloatRegBits regVal = floatRegs.i[flatIndex]; 262 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 263 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 264 return regVal; 265 } 266 267 void setIntReg(int reg_idx, uint64_t val) 268 { 269 int flatIndex = isa.flattenIntIndex(reg_idx); 270 assert(flatIndex < TheISA::NumIntRegs); 271 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 272 reg_idx, flatIndex, val); 273 intRegs[flatIndex] = val; 274 } 275 276 void setFloatReg(int reg_idx, FloatReg val) 277 { 278 int flatIndex = isa.flattenFloatIndex(reg_idx); 279 assert(flatIndex < TheISA::NumFloatRegs); 280 floatRegs.f[flatIndex] = val; 281 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 282 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 283 } 284 285 void setFloatRegBits(int reg_idx, FloatRegBits val) 286 { 287 int flatIndex = isa.flattenFloatIndex(reg_idx); 288 assert(flatIndex < TheISA::NumFloatRegs); 289 floatRegs.i[flatIndex] = val; 290 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 291 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 292 } 293 294 TheISA::PCState 295 pcState() 296 { 297 return _pcState; 298 } 299 300 void 301 pcState(const TheISA::PCState &val) 302 { 303 _pcState = val; 304 } 305 306 Addr 307 instAddr() 308 { 309 return _pcState.instAddr(); 310 } 311 312 Addr 313 nextInstAddr() 314 { 315 return _pcState.nextInstAddr(); 316 } 317 318 MicroPC 319 microPC() 320 { 321 return _pcState.microPC(); 322 } 323 324 bool readPredicate() 325 { 326 return predicate; 327 } 328 329 void setPredicate(bool val) 330 { 331 predicate = val; 332 } 333 334 MiscReg 335 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 336 { 337 return isa.readMiscRegNoEffect(misc_reg); 338 } 339 340 MiscReg 341 readMiscReg(int misc_reg, ThreadID tid = 0) 342 { 343 return isa.readMiscReg(misc_reg, tc); 344 } 345 346 void 347 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 348 { 349 return isa.setMiscRegNoEffect(misc_reg, val); 350 } 351 352 void 353 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 354 { 355 return isa.setMiscReg(misc_reg, val, tc); 356 } 357 358 int 359 flattenIntIndex(int reg) 360 { 361 return isa.flattenIntIndex(reg); 362 } 363 364 int 365 flattenFloatIndex(int reg) 366 { 367 return isa.flattenFloatIndex(reg); 368 } 369 370 unsigned readStCondFailures() { return storeCondFailures; } 371 372 void setStCondFailures(unsigned sc_failures) 373 { storeCondFailures = sc_failures; } 374 375 void syscall(int64_t callnum) 376 { 377 process->syscall(callnum, tc); 378 } 379}; 380 381 382// for non-speculative execution context, spec_mode is always false 383inline bool 384SimpleThread::misspeculating() 385{ 386 return false; 387} 388 389#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 390