simple_thread.hh revision 8761
1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_SIMPLE_THREAD_HH__ 33#define __CPU_SIMPLE_THREAD_HH__ 34 35#include "arch/isa.hh" 36#include "arch/isa_traits.hh" 37#include "arch/registers.hh" 38#include "arch/tlb.hh" 39#include "arch/types.hh" 40#include "base/types.hh" 41#include "config/full_system.hh" 42#include "config/the_isa.hh" 43#include "cpu/decode.hh" 44#include "cpu/thread_context.hh" 45#include "cpu/thread_state.hh" 46#include "debug/FloatRegs.hh" 47#include "debug/IntRegs.hh" 48#include "mem/request.hh" 49#include "sim/byteswap.hh" 50#include "sim/eventq.hh" 51#include "sim/serialize.hh" 52 53class BaseCPU; 54 55#if FULL_SYSTEM 56 57#include "sim/system.hh" 58 59class FunctionProfile; 60class ProfileNode; 61class FunctionalPort; 62class PhysicalPort; 63 64namespace TheISA { 65 namespace Kernel { 66 class Statistics; 67 }; 68}; 69 70#else // !FULL_SYSTEM 71 72#include "mem/page_table.hh" 73#include "sim/process.hh" 74class TranslatingPort; 75 76#endif // FULL_SYSTEM 77 78/** 79 * The SimpleThread object provides a combination of the ThreadState 80 * object and the ThreadContext interface. It implements the 81 * ThreadContext interface so that a ProxyThreadContext class can be 82 * made using SimpleThread as the template parameter (see 83 * thread_context.hh). It adds to the ThreadState object by adding all 84 * the objects needed for simple functional execution, including a 85 * simple architectural register file, and pointers to the ITB and DTB 86 * in full system mode. For CPU models that do not need more advanced 87 * ways to hold state (i.e. a separate physical register file, or 88 * separate fetch and commit PC's), this SimpleThread class provides 89 * all the necessary state for full architecture-level functional 90 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 91 * examples. 92 */ 93 94class SimpleThread : public ThreadState 95{ 96 protected: 97 typedef TheISA::MachInst MachInst; 98 typedef TheISA::MiscReg MiscReg; 99 typedef TheISA::FloatReg FloatReg; 100 typedef TheISA::FloatRegBits FloatRegBits; 101 public: 102 typedef ThreadContext::Status Status; 103 104 protected: 105 union { 106 FloatReg f[TheISA::NumFloatRegs]; 107 FloatRegBits i[TheISA::NumFloatRegs]; 108 } floatRegs; 109 TheISA::IntReg intRegs[TheISA::NumIntRegs]; 110 TheISA::ISA isa; // one "instance" of the current ISA. 111 112 TheISA::PCState _pcState; 113 114 /** Did this instruction execute or is it predicated false */ 115 bool predicate; 116 117 public: 118 std::string name() const 119 { 120 return csprintf("%s.[tid:%i]", cpu->name(), tc->threadId()); 121 } 122 123 // pointer to CPU associated with this SimpleThread 124 BaseCPU *cpu; 125 126 ProxyThreadContext<SimpleThread> *tc; 127 128 System *system; 129 130 TheISA::TLB *itb; 131 TheISA::TLB *dtb; 132 133 Decoder decoder; 134 135 // constructor: initialize SimpleThread from given process structure 136#if FULL_SYSTEM 137 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 138 TheISA::TLB *_itb, TheISA::TLB *_dtb, 139 bool use_kernel_stats = true); 140#else 141 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 142 TheISA::TLB *_itb, TheISA::TLB *_dtb); 143#endif 144 145 SimpleThread(); 146 147 virtual ~SimpleThread(); 148 149 virtual void takeOverFrom(ThreadContext *oldContext); 150 151 void regStats(const std::string &name); 152 153 void copyTC(ThreadContext *context); 154 155 void copyState(ThreadContext *oldContext); 156 157 void serialize(std::ostream &os); 158 void unserialize(Checkpoint *cp, const std::string §ion); 159 160 /*************************************************************** 161 * SimpleThread functions to provide CPU with access to various 162 * state. 163 **************************************************************/ 164 165 /** Returns the pointer to this SimpleThread's ThreadContext. Used 166 * when a ThreadContext must be passed to objects outside of the 167 * CPU. 168 */ 169 ThreadContext *getTC() { return tc; } 170 171 void demapPage(Addr vaddr, uint64_t asn) 172 { 173 itb->demapPage(vaddr, asn); 174 dtb->demapPage(vaddr, asn); 175 } 176 177 void demapInstPage(Addr vaddr, uint64_t asn) 178 { 179 itb->demapPage(vaddr, asn); 180 } 181 182 void demapDataPage(Addr vaddr, uint64_t asn) 183 { 184 dtb->demapPage(vaddr, asn); 185 } 186 187#if FULL_SYSTEM 188 void dumpFuncProfile(); 189 190 Fault hwrei(); 191 192 bool simPalCheck(int palFunc); 193 194#endif 195 196 /******************************************* 197 * ThreadContext interface functions. 198 ******************************************/ 199 200 BaseCPU *getCpuPtr() { return cpu; } 201 202 TheISA::TLB *getITBPtr() { return itb; } 203 204 TheISA::TLB *getDTBPtr() { return dtb; } 205 206 Decoder *getDecoderPtr() { return &decoder; } 207 208 System *getSystemPtr() { return system; } 209 210 FunctionalPort *getPhysPort() { return physPort; } 211 212 /** Return a virtual port. This port cannot be cached locally in an object. 213 * After a CPU switch it may point to the wrong memory object which could 214 * mean stale data. 215 */ 216 VirtualPort *getVirtPort() { return virtPort; } 217 218 Status status() const { return _status; } 219 220 void setStatus(Status newStatus) { _status = newStatus; } 221 222 /// Set the status to Active. Optional delay indicates number of 223 /// cycles to wait before beginning execution. 224 void activate(int delay = 1); 225 226 /// Set the status to Suspended. 227 void suspend(); 228 229 /// Set the status to Halted. 230 void halt(); 231 232 virtual bool misspeculating(); 233 234 void copyArchRegs(ThreadContext *tc); 235 236 void clearArchRegs() 237 { 238 _pcState = 0; 239 memset(intRegs, 0, sizeof(intRegs)); 240 memset(floatRegs.i, 0, sizeof(floatRegs.i)); 241 isa.clear(); 242 } 243 244 // 245 // New accessors for new decoder. 246 // 247 uint64_t readIntReg(int reg_idx) 248 { 249 int flatIndex = isa.flattenIntIndex(reg_idx); 250 assert(flatIndex < TheISA::NumIntRegs); 251 uint64_t regVal = intRegs[flatIndex]; 252 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 253 reg_idx, flatIndex, regVal); 254 return regVal; 255 } 256 257 FloatReg readFloatReg(int reg_idx) 258 { 259 int flatIndex = isa.flattenFloatIndex(reg_idx); 260 assert(flatIndex < TheISA::NumFloatRegs); 261 FloatReg regVal = floatRegs.f[flatIndex]; 262 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 263 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 264 return regVal; 265 } 266 267 FloatRegBits readFloatRegBits(int reg_idx) 268 { 269 int flatIndex = isa.flattenFloatIndex(reg_idx); 270 assert(flatIndex < TheISA::NumFloatRegs); 271 FloatRegBits regVal = floatRegs.i[flatIndex]; 272 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 273 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 274 return regVal; 275 } 276 277 void setIntReg(int reg_idx, uint64_t val) 278 { 279 int flatIndex = isa.flattenIntIndex(reg_idx); 280 assert(flatIndex < TheISA::NumIntRegs); 281 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 282 reg_idx, flatIndex, val); 283 intRegs[flatIndex] = val; 284 } 285 286 void setFloatReg(int reg_idx, FloatReg val) 287 { 288 int flatIndex = isa.flattenFloatIndex(reg_idx); 289 assert(flatIndex < TheISA::NumFloatRegs); 290 floatRegs.f[flatIndex] = val; 291 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 292 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 293 } 294 295 void setFloatRegBits(int reg_idx, FloatRegBits val) 296 { 297 int flatIndex = isa.flattenFloatIndex(reg_idx); 298 assert(flatIndex < TheISA::NumFloatRegs); 299 floatRegs.i[flatIndex] = val; 300 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 301 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 302 } 303 304 TheISA::PCState 305 pcState() 306 { 307 return _pcState; 308 } 309 310 void 311 pcState(const TheISA::PCState &val) 312 { 313 _pcState = val; 314 } 315 316 Addr 317 instAddr() 318 { 319 return _pcState.instAddr(); 320 } 321 322 Addr 323 nextInstAddr() 324 { 325 return _pcState.nextInstAddr(); 326 } 327 328 MicroPC 329 microPC() 330 { 331 return _pcState.microPC(); 332 } 333 334 bool readPredicate() 335 { 336 return predicate; 337 } 338 339 void setPredicate(bool val) 340 { 341 predicate = val; 342 } 343 344 MiscReg 345 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 346 { 347 return isa.readMiscRegNoEffect(misc_reg); 348 } 349 350 MiscReg 351 readMiscReg(int misc_reg, ThreadID tid = 0) 352 { 353 return isa.readMiscReg(misc_reg, tc); 354 } 355 356 void 357 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 358 { 359 return isa.setMiscRegNoEffect(misc_reg, val); 360 } 361 362 void 363 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 364 { 365 return isa.setMiscReg(misc_reg, val, tc); 366 } 367 368 int 369 flattenIntIndex(int reg) 370 { 371 return isa.flattenIntIndex(reg); 372 } 373 374 int 375 flattenFloatIndex(int reg) 376 { 377 return isa.flattenFloatIndex(reg); 378 } 379 380 unsigned readStCondFailures() { return storeCondFailures; } 381 382 void setStCondFailures(unsigned sc_failures) 383 { storeCondFailures = sc_failures; } 384 385#if !FULL_SYSTEM 386 void syscall(int64_t callnum) 387 { 388 process->syscall(callnum, tc); 389 } 390#endif 391}; 392 393 394// for non-speculative execution context, spec_mode is always false 395inline bool 396SimpleThread::misspeculating() 397{ 398 return false; 399} 400 401#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 402