simple_thread.hh revision 8733
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 * Nathan Binkert 42 */ 43 44#ifndef __CPU_SIMPLE_THREAD_HH__ 45#define __CPU_SIMPLE_THREAD_HH__ 46 47#include "arch/isa.hh" 48#include "arch/isa_traits.hh" 49#include "arch/registers.hh" 50#include "arch/tlb.hh" 51#include "arch/types.hh" 52#include "base/types.hh" 53#include "config/full_system.hh" 54#include "config/the_isa.hh" 55#include "config/use_checker.hh" 56#include "cpu/decode.hh" 57#include "cpu/thread_context.hh" 58#include "cpu/thread_state.hh" 59#include "debug/FloatRegs.hh" 60#include "debug/IntRegs.hh" 61#include "mem/request.hh" 62#include "sim/byteswap.hh" 63#include "sim/eventq.hh" 64#include "sim/serialize.hh" 65 66class BaseCPU; 67 68#if FULL_SYSTEM 69 70#include "sim/system.hh" 71 72class FunctionProfile; 73class ProfileNode; 74 75namespace TheISA { 76 namespace Kernel { 77 class Statistics; 78 }; 79}; 80 81#else // !FULL_SYSTEM 82 83#include "mem/page_table.hh" 84#include "sim/process.hh" 85 86#endif // FULL_SYSTEM 87 88/** 89 * The SimpleThread object provides a combination of the ThreadState 90 * object and the ThreadContext interface. It implements the 91 * ThreadContext interface so that a ProxyThreadContext class can be 92 * made using SimpleThread as the template parameter (see 93 * thread_context.hh). It adds to the ThreadState object by adding all 94 * the objects needed for simple functional execution, including a 95 * simple architectural register file, and pointers to the ITB and DTB 96 * in full system mode. For CPU models that do not need more advanced 97 * ways to hold state (i.e. a separate physical register file, or 98 * separate fetch and commit PC's), this SimpleThread class provides 99 * all the necessary state for full architecture-level functional 100 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 101 * examples. 102 */ 103 104class SimpleThread : public ThreadState 105{ 106 protected: 107 typedef TheISA::MachInst MachInst; 108 typedef TheISA::MiscReg MiscReg; 109 typedef TheISA::FloatReg FloatReg; 110 typedef TheISA::FloatRegBits FloatRegBits; 111 public: 112 typedef ThreadContext::Status Status; 113 114 protected: 115 union { 116 FloatReg f[TheISA::NumFloatRegs]; 117 FloatRegBits i[TheISA::NumFloatRegs]; 118 } floatRegs; 119 TheISA::IntReg intRegs[TheISA::NumIntRegs]; 120 TheISA::ISA isa; // one "instance" of the current ISA. 121 122 TheISA::PCState _pcState; 123 124 /** Did this instruction execute or is it predicated false */ 125 bool predicate; 126 127 public: 128 std::string name() const 129 { 130 return csprintf("%s.[tid:%i]", cpu->name(), tc->threadId()); 131 } 132 133 // pointer to CPU associated with this SimpleThread 134 BaseCPU *cpu; 135 136 ProxyThreadContext<SimpleThread> *tc; 137 138 System *system; 139 140 TheISA::TLB *itb; 141 TheISA::TLB *dtb; 142 143 Decoder decoder; 144 145 // constructor: initialize SimpleThread from given process structure 146#if FULL_SYSTEM 147 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 148 TheISA::TLB *_itb, TheISA::TLB *_dtb, 149 bool use_kernel_stats = true); 150#else 151 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 152 TheISA::TLB *_itb, TheISA::TLB *_dtb); 153#endif 154 155 SimpleThread(); 156 157 virtual ~SimpleThread(); 158 159 virtual void takeOverFrom(ThreadContext *oldContext); 160 161 void regStats(const std::string &name); 162 163 void copyTC(ThreadContext *context); 164 165 void copyState(ThreadContext *oldContext); 166 167 void serialize(std::ostream &os); 168 void unserialize(Checkpoint *cp, const std::string §ion); 169 170 /*************************************************************** 171 * SimpleThread functions to provide CPU with access to various 172 * state. 173 **************************************************************/ 174 175 /** Returns the pointer to this SimpleThread's ThreadContext. Used 176 * when a ThreadContext must be passed to objects outside of the 177 * CPU. 178 */ 179 ThreadContext *getTC() { return tc; } 180 181 void demapPage(Addr vaddr, uint64_t asn) 182 { 183 itb->demapPage(vaddr, asn); 184 dtb->demapPage(vaddr, asn); 185 } 186 187 void demapInstPage(Addr vaddr, uint64_t asn) 188 { 189 itb->demapPage(vaddr, asn); 190 } 191 192 void demapDataPage(Addr vaddr, uint64_t asn) 193 { 194 dtb->demapPage(vaddr, asn); 195 } 196 197#if FULL_SYSTEM 198 void dumpFuncProfile(); 199 200 Fault hwrei(); 201 202 bool simPalCheck(int palFunc); 203 204#endif 205 206 /******************************************* 207 * ThreadContext interface functions. 208 ******************************************/ 209 210 BaseCPU *getCpuPtr() { return cpu; } 211 212 TheISA::TLB *getITBPtr() { return itb; } 213 214 TheISA::TLB *getDTBPtr() { return dtb; } 215 216#if USE_CHECKER 217 BaseCPU *getCheckerCpuPtr() { return NULL; } 218#endif 219 220 Decoder *getDecoderPtr() { return &decoder; } 221 222 System *getSystemPtr() { return system; } 223 224#if FULL_SYSTEM 225 PortProxy* getPhysProxy() { return physProxy; } 226 227 /** Return a virtual port. This port cannot be cached locally in an object. 228 * After a CPU switch it may point to the wrong memory object which could 229 * mean stale data. 230 */ 231 FSTranslatingPortProxy* getVirtProxy() { return virtProxy; } 232#endif 233 234 Status status() const { return _status; } 235 236 void setStatus(Status newStatus) { _status = newStatus; } 237 238 /// Set the status to Active. Optional delay indicates number of 239 /// cycles to wait before beginning execution. 240 void activate(int delay = 1); 241 242 /// Set the status to Suspended. 243 void suspend(); 244 245 /// Set the status to Halted. 246 void halt(); 247 248 virtual bool misspeculating(); 249 250 void copyArchRegs(ThreadContext *tc); 251 252 void clearArchRegs() 253 { 254 _pcState = 0; 255 memset(intRegs, 0, sizeof(intRegs)); 256 memset(floatRegs.i, 0, sizeof(floatRegs.i)); 257 isa.clear(); 258 } 259 260 // 261 // New accessors for new decoder. 262 // 263 uint64_t readIntReg(int reg_idx) 264 { 265 int flatIndex = isa.flattenIntIndex(reg_idx); 266 assert(flatIndex < TheISA::NumIntRegs); 267 uint64_t regVal = intRegs[flatIndex]; 268 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 269 reg_idx, flatIndex, regVal); 270 return regVal; 271 } 272 273 FloatReg readFloatReg(int reg_idx) 274 { 275 int flatIndex = isa.flattenFloatIndex(reg_idx); 276 assert(flatIndex < TheISA::NumFloatRegs); 277 FloatReg regVal = floatRegs.f[flatIndex]; 278 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 279 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 280 return regVal; 281 } 282 283 FloatRegBits readFloatRegBits(int reg_idx) 284 { 285 int flatIndex = isa.flattenFloatIndex(reg_idx); 286 assert(flatIndex < TheISA::NumFloatRegs); 287 FloatRegBits regVal = floatRegs.i[flatIndex]; 288 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 289 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 290 return regVal; 291 } 292 293 void setIntReg(int reg_idx, uint64_t val) 294 { 295 int flatIndex = isa.flattenIntIndex(reg_idx); 296 assert(flatIndex < TheISA::NumIntRegs); 297 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 298 reg_idx, flatIndex, val); 299 intRegs[flatIndex] = val; 300 } 301 302 void setFloatReg(int reg_idx, FloatReg val) 303 { 304 int flatIndex = isa.flattenFloatIndex(reg_idx); 305 assert(flatIndex < TheISA::NumFloatRegs); 306 floatRegs.f[flatIndex] = val; 307 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 308 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 309 } 310 311 void setFloatRegBits(int reg_idx, FloatRegBits val) 312 { 313 int flatIndex = isa.flattenFloatIndex(reg_idx); 314 assert(flatIndex < TheISA::NumFloatRegs); 315 // XXX: Fix array out of bounds compiler error for gem5.fast 316 // when checkercpu enabled 317 if (flatIndex < TheISA::NumFloatRegs) 318 floatRegs.i[flatIndex] = val; 319 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 320 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 321 } 322 323 TheISA::PCState 324 pcState() 325 { 326 return _pcState; 327 } 328 329 void 330 pcState(const TheISA::PCState &val) 331 { 332 _pcState = val; 333 } 334 335#if USE_CHECKER 336 void 337 pcStateNoRecord(const TheISA::PCState &val) 338 { 339 _pcState = val; 340 } 341#endif 342 343 Addr 344 instAddr() 345 { 346 return _pcState.instAddr(); 347 } 348 349 Addr 350 nextInstAddr() 351 { 352 return _pcState.nextInstAddr(); 353 } 354 355 MicroPC 356 microPC() 357 { 358 return _pcState.microPC(); 359 } 360 361 bool readPredicate() 362 { 363 return predicate; 364 } 365 366 void setPredicate(bool val) 367 { 368 predicate = val; 369 } 370 371 MiscReg 372 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 373 { 374 return isa.readMiscRegNoEffect(misc_reg); 375 } 376 377 MiscReg 378 readMiscReg(int misc_reg, ThreadID tid = 0) 379 { 380 return isa.readMiscReg(misc_reg, tc); 381 } 382 383 void 384 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 385 { 386 return isa.setMiscRegNoEffect(misc_reg, val); 387 } 388 389 void 390 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 391 { 392 return isa.setMiscReg(misc_reg, val, tc); 393 } 394 395 int 396 flattenIntIndex(int reg) 397 { 398 return isa.flattenIntIndex(reg); 399 } 400 401 int 402 flattenFloatIndex(int reg) 403 { 404 return isa.flattenFloatIndex(reg); 405 } 406 407 unsigned readStCondFailures() { return storeCondFailures; } 408 409 void setStCondFailures(unsigned sc_failures) 410 { storeCondFailures = sc_failures; } 411 412#if !FULL_SYSTEM 413 void syscall(int64_t callnum) 414 { 415 process->syscall(callnum, tc); 416 } 417#endif 418}; 419 420 421// for non-speculative execution context, spec_mode is always false 422inline bool 423SimpleThread::misspeculating() 424{ 425 return false; 426} 427 428#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 429