simple_thread.hh revision 8232:b28d06a175be
1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_SIMPLE_THREAD_HH__ 33#define __CPU_SIMPLE_THREAD_HH__ 34 35#include "arch/isa.hh" 36#include "arch/isa_traits.hh" 37#include "arch/registers.hh" 38#include "arch/tlb.hh" 39#include "arch/types.hh" 40#include "base/types.hh" 41#include "config/full_system.hh" 42#include "config/the_isa.hh" 43#include "cpu/thread_context.hh" 44#include "cpu/thread_state.hh" 45#include "debug/FloatRegs.hh" 46#include "debug/IntRegs.hh" 47#include "mem/request.hh" 48#include "sim/byteswap.hh" 49#include "sim/eventq.hh" 50#include "sim/serialize.hh" 51 52class BaseCPU; 53 54#if FULL_SYSTEM 55 56#include "sim/system.hh" 57 58class FunctionProfile; 59class ProfileNode; 60class FunctionalPort; 61class PhysicalPort; 62 63namespace TheISA { 64 namespace Kernel { 65 class Statistics; 66 }; 67}; 68 69#else // !FULL_SYSTEM 70 71#include "mem/page_table.hh" 72#include "sim/process.hh" 73class TranslatingPort; 74 75#endif // FULL_SYSTEM 76 77/** 78 * The SimpleThread object provides a combination of the ThreadState 79 * object and the ThreadContext interface. It implements the 80 * ThreadContext interface so that a ProxyThreadContext class can be 81 * made using SimpleThread as the template parameter (see 82 * thread_context.hh). It adds to the ThreadState object by adding all 83 * the objects needed for simple functional execution, including a 84 * simple architectural register file, and pointers to the ITB and DTB 85 * in full system mode. For CPU models that do not need more advanced 86 * ways to hold state (i.e. a separate physical register file, or 87 * separate fetch and commit PC's), this SimpleThread class provides 88 * all the necessary state for full architecture-level functional 89 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 90 * examples. 91 */ 92 93class SimpleThread : public ThreadState 94{ 95 protected: 96 typedef TheISA::MachInst MachInst; 97 typedef TheISA::MiscReg MiscReg; 98 typedef TheISA::FloatReg FloatReg; 99 typedef TheISA::FloatRegBits FloatRegBits; 100 public: 101 typedef ThreadContext::Status Status; 102 103 protected: 104 union { 105 FloatReg f[TheISA::NumFloatRegs]; 106 FloatRegBits i[TheISA::NumFloatRegs]; 107 } floatRegs; 108 TheISA::IntReg intRegs[TheISA::NumIntRegs]; 109 TheISA::ISA isa; // one "instance" of the current ISA. 110 111 TheISA::PCState _pcState; 112 113 /** Did this instruction execute or is it predicated false */ 114 bool predicate; 115 116 public: 117 // pointer to CPU associated with this SimpleThread 118 BaseCPU *cpu; 119 120 ProxyThreadContext<SimpleThread> *tc; 121 122 System *system; 123 124 TheISA::TLB *itb; 125 TheISA::TLB *dtb; 126 127 // constructor: initialize SimpleThread from given process structure 128#if FULL_SYSTEM 129 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 130 TheISA::TLB *_itb, TheISA::TLB *_dtb, 131 bool use_kernel_stats = true); 132#else 133 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 134 TheISA::TLB *_itb, TheISA::TLB *_dtb); 135#endif 136 137 SimpleThread(); 138 139 virtual ~SimpleThread(); 140 141 virtual void takeOverFrom(ThreadContext *oldContext); 142 143 void regStats(const std::string &name); 144 145 void copyTC(ThreadContext *context); 146 147 void copyState(ThreadContext *oldContext); 148 149 void serialize(std::ostream &os); 150 void unserialize(Checkpoint *cp, const std::string §ion); 151 152 /*************************************************************** 153 * SimpleThread functions to provide CPU with access to various 154 * state. 155 **************************************************************/ 156 157 /** Returns the pointer to this SimpleThread's ThreadContext. Used 158 * when a ThreadContext must be passed to objects outside of the 159 * CPU. 160 */ 161 ThreadContext *getTC() { return tc; } 162 163 void demapPage(Addr vaddr, uint64_t asn) 164 { 165 itb->demapPage(vaddr, asn); 166 dtb->demapPage(vaddr, asn); 167 } 168 169 void demapInstPage(Addr vaddr, uint64_t asn) 170 { 171 itb->demapPage(vaddr, asn); 172 } 173 174 void demapDataPage(Addr vaddr, uint64_t asn) 175 { 176 dtb->demapPage(vaddr, asn); 177 } 178 179#if FULL_SYSTEM 180 void dumpFuncProfile(); 181 182 Fault hwrei(); 183 184 bool simPalCheck(int palFunc); 185 186#endif 187 188 /******************************************* 189 * ThreadContext interface functions. 190 ******************************************/ 191 192 BaseCPU *getCpuPtr() { return cpu; } 193 194 TheISA::TLB *getITBPtr() { return itb; } 195 196 TheISA::TLB *getDTBPtr() { return dtb; } 197 198 System *getSystemPtr() { return system; } 199 200#if FULL_SYSTEM 201 FunctionalPort *getPhysPort() { return physPort; } 202 203 /** Return a virtual port. This port cannot be cached locally in an object. 204 * After a CPU switch it may point to the wrong memory object which could 205 * mean stale data. 206 */ 207 VirtualPort *getVirtPort() { return virtPort; } 208#endif 209 210 Status status() const { return _status; } 211 212 void setStatus(Status newStatus) { _status = newStatus; } 213 214 /// Set the status to Active. Optional delay indicates number of 215 /// cycles to wait before beginning execution. 216 void activate(int delay = 1); 217 218 /// Set the status to Suspended. 219 void suspend(); 220 221 /// Set the status to Halted. 222 void halt(); 223 224 virtual bool misspeculating(); 225 226 void copyArchRegs(ThreadContext *tc); 227 228 void clearArchRegs() 229 { 230 _pcState = 0; 231 memset(intRegs, 0, sizeof(intRegs)); 232 memset(floatRegs.i, 0, sizeof(floatRegs.i)); 233 isa.clear(); 234 } 235 236 // 237 // New accessors for new decoder. 238 // 239 uint64_t readIntReg(int reg_idx) 240 { 241 int flatIndex = isa.flattenIntIndex(reg_idx); 242 assert(flatIndex < TheISA::NumIntRegs); 243 uint64_t regVal = intRegs[flatIndex]; 244 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 245 reg_idx, flatIndex, regVal); 246 return regVal; 247 } 248 249 FloatReg readFloatReg(int reg_idx) 250 { 251 int flatIndex = isa.flattenFloatIndex(reg_idx); 252 assert(flatIndex < TheISA::NumFloatRegs); 253 FloatReg regVal = floatRegs.f[flatIndex]; 254 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 255 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 256 return regVal; 257 } 258 259 FloatRegBits readFloatRegBits(int reg_idx) 260 { 261 int flatIndex = isa.flattenFloatIndex(reg_idx); 262 assert(flatIndex < TheISA::NumFloatRegs); 263 FloatRegBits regVal = floatRegs.i[flatIndex]; 264 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 265 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 266 return regVal; 267 } 268 269 void setIntReg(int reg_idx, uint64_t val) 270 { 271 int flatIndex = isa.flattenIntIndex(reg_idx); 272 assert(flatIndex < TheISA::NumIntRegs); 273 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 274 reg_idx, flatIndex, val); 275 intRegs[flatIndex] = val; 276 } 277 278 void setFloatReg(int reg_idx, FloatReg val) 279 { 280 int flatIndex = isa.flattenFloatIndex(reg_idx); 281 assert(flatIndex < TheISA::NumFloatRegs); 282 floatRegs.f[flatIndex] = val; 283 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 284 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 285 } 286 287 void setFloatRegBits(int reg_idx, FloatRegBits val) 288 { 289 int flatIndex = isa.flattenFloatIndex(reg_idx); 290 assert(flatIndex < TheISA::NumFloatRegs); 291 floatRegs.i[flatIndex] = val; 292 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 293 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 294 } 295 296 TheISA::PCState 297 pcState() 298 { 299 return _pcState; 300 } 301 302 void 303 pcState(const TheISA::PCState &val) 304 { 305 _pcState = val; 306 } 307 308 Addr 309 instAddr() 310 { 311 return _pcState.instAddr(); 312 } 313 314 Addr 315 nextInstAddr() 316 { 317 return _pcState.nextInstAddr(); 318 } 319 320 MicroPC 321 microPC() 322 { 323 return _pcState.microPC(); 324 } 325 326 bool readPredicate() 327 { 328 return predicate; 329 } 330 331 void setPredicate(bool val) 332 { 333 predicate = val; 334 } 335 336 MiscReg 337 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 338 { 339 return isa.readMiscRegNoEffect(misc_reg); 340 } 341 342 MiscReg 343 readMiscReg(int misc_reg, ThreadID tid = 0) 344 { 345 return isa.readMiscReg(misc_reg, tc); 346 } 347 348 void 349 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 350 { 351 return isa.setMiscRegNoEffect(misc_reg, val); 352 } 353 354 void 355 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 356 { 357 return isa.setMiscReg(misc_reg, val, tc); 358 } 359 360 int 361 flattenIntIndex(int reg) 362 { 363 return isa.flattenIntIndex(reg); 364 } 365 366 int 367 flattenFloatIndex(int reg) 368 { 369 return isa.flattenFloatIndex(reg); 370 } 371 372 unsigned readStCondFailures() { return storeCondFailures; } 373 374 void setStCondFailures(unsigned sc_failures) 375 { storeCondFailures = sc_failures; } 376 377#if !FULL_SYSTEM 378 void syscall(int64_t callnum) 379 { 380 process->syscall(callnum, tc); 381 } 382#endif 383}; 384 385 386// for non-speculative execution context, spec_mode is always false 387inline bool 388SimpleThread::misspeculating() 389{ 390 return false; 391} 392 393#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 394