simple_thread.hh revision 7678:f19b6a3a8cec
112855Sgabeblack@google.com/* 212855Sgabeblack@google.com * Copyright (c) 2001-2006 The Regents of The University of Michigan 312855Sgabeblack@google.com * All rights reserved. 412855Sgabeblack@google.com * 512855Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 612855Sgabeblack@google.com * modification, are permitted provided that the following conditions are 712855Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 812855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 912855Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 1012855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 1112855Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 1212855Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 1312855Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 1412855Sgabeblack@google.com * this software without specific prior written permission. 1512855Sgabeblack@google.com * 1612855Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712855Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812855Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912855Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012855Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112855Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212855Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312855Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412855Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512855Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612855Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712855Sgabeblack@google.com * 2812855Sgabeblack@google.com * Authors: Steve Reinhardt 2912855Sgabeblack@google.com * Nathan Binkert 3012855Sgabeblack@google.com */ 3112855Sgabeblack@google.com 3212855Sgabeblack@google.com#ifndef __CPU_SIMPLE_THREAD_HH__ 3312855Sgabeblack@google.com#define __CPU_SIMPLE_THREAD_HH__ 3412855Sgabeblack@google.com 3512855Sgabeblack@google.com#include "arch/isa.hh" 3612855Sgabeblack@google.com#include "arch/isa_traits.hh" 3712855Sgabeblack@google.com#include "arch/registers.hh" 3812855Sgabeblack@google.com#include "arch/tlb.hh" 3912855Sgabeblack@google.com#include "arch/types.hh" 4012855Sgabeblack@google.com#include "base/types.hh" 4112855Sgabeblack@google.com#include "config/full_system.hh" 4212855Sgabeblack@google.com#include "config/the_isa.hh" 4312855Sgabeblack@google.com#include "cpu/thread_context.hh" 4412855Sgabeblack@google.com#include "cpu/thread_state.hh" 4512855Sgabeblack@google.com#include "mem/request.hh" 4612855Sgabeblack@google.com#include "sim/byteswap.hh" 4712855Sgabeblack@google.com#include "sim/eventq.hh" 4812855Sgabeblack@google.com#include "sim/serialize.hh" 4912855Sgabeblack@google.com 5012855Sgabeblack@google.comclass BaseCPU; 5112855Sgabeblack@google.com 5212855Sgabeblack@google.com#if FULL_SYSTEM 5312855Sgabeblack@google.com 5412855Sgabeblack@google.com#include "sim/system.hh" 5512855Sgabeblack@google.com 5612855Sgabeblack@google.comclass FunctionProfile; 5712855Sgabeblack@google.comclass ProfileNode; 5812855Sgabeblack@google.comclass FunctionalPort; 5912855Sgabeblack@google.comclass PhysicalPort; 6012855Sgabeblack@google.com 6112855Sgabeblack@google.comnamespace TheISA { 6212855Sgabeblack@google.com namespace Kernel { 6312855Sgabeblack@google.com class Statistics; 6412855Sgabeblack@google.com }; 6512855Sgabeblack@google.com}; 6612855Sgabeblack@google.com 6712855Sgabeblack@google.com#else // !FULL_SYSTEM 6812855Sgabeblack@google.com 6912855Sgabeblack@google.com#include "sim/process.hh" 7012855Sgabeblack@google.com#include "mem/page_table.hh" 7112855Sgabeblack@google.comclass TranslatingPort; 7212855Sgabeblack@google.com 7312855Sgabeblack@google.com#endif // FULL_SYSTEM 7412855Sgabeblack@google.com 7512855Sgabeblack@google.com/** 7612855Sgabeblack@google.com * The SimpleThread object provides a combination of the ThreadState 7712855Sgabeblack@google.com * object and the ThreadContext interface. It implements the 7812855Sgabeblack@google.com * ThreadContext interface so that a ProxyThreadContext class can be 7912855Sgabeblack@google.com * made using SimpleThread as the template parameter (see 8012855Sgabeblack@google.com * thread_context.hh). It adds to the ThreadState object by adding all 81 * the objects needed for simple functional execution, including a 82 * simple architectural register file, and pointers to the ITB and DTB 83 * in full system mode. For CPU models that do not need more advanced 84 * ways to hold state (i.e. a separate physical register file, or 85 * separate fetch and commit PC's), this SimpleThread class provides 86 * all the necessary state for full architecture-level functional 87 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 88 * examples. 89 */ 90 91class SimpleThread : public ThreadState 92{ 93 protected: 94 typedef TheISA::MachInst MachInst; 95 typedef TheISA::MiscReg MiscReg; 96 typedef TheISA::FloatReg FloatReg; 97 typedef TheISA::FloatRegBits FloatRegBits; 98 public: 99 typedef ThreadContext::Status Status; 100 101 protected: 102 union { 103 FloatReg f[TheISA::NumFloatRegs]; 104 FloatRegBits i[TheISA::NumFloatRegs]; 105 } floatRegs; 106 TheISA::IntReg intRegs[TheISA::NumIntRegs]; 107 TheISA::ISA isa; // one "instance" of the current ISA. 108 109 /** The current microcode pc for the currently executing macro 110 * operation. 111 */ 112 MicroPC microPC; 113 114 /** The next microcode pc for the currently executing macro 115 * operation. 116 */ 117 MicroPC nextMicroPC; 118 119 /** The current pc. 120 */ 121 Addr PC; 122 123 /** The next pc. 124 */ 125 Addr nextPC; 126 127 /** The next next pc. 128 */ 129 Addr nextNPC; 130 131 /** Did this instruction execute or is it predicated false */ 132 bool predicate; 133 134 public: 135 // pointer to CPU associated with this SimpleThread 136 BaseCPU *cpu; 137 138 ProxyThreadContext<SimpleThread> *tc; 139 140 System *system; 141 142 TheISA::TLB *itb; 143 TheISA::TLB *dtb; 144 145 // constructor: initialize SimpleThread from given process structure 146#if FULL_SYSTEM 147 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 148 TheISA::TLB *_itb, TheISA::TLB *_dtb, 149 bool use_kernel_stats = true); 150#else 151 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 152 TheISA::TLB *_itb, TheISA::TLB *_dtb); 153#endif 154 155 SimpleThread(); 156 157 virtual ~SimpleThread(); 158 159 virtual void takeOverFrom(ThreadContext *oldContext); 160 161 void regStats(const std::string &name); 162 163 void copyTC(ThreadContext *context); 164 165 void copyState(ThreadContext *oldContext); 166 167 void serialize(std::ostream &os); 168 void unserialize(Checkpoint *cp, const std::string §ion); 169 170 /*************************************************************** 171 * SimpleThread functions to provide CPU with access to various 172 * state. 173 **************************************************************/ 174 175 /** Returns the pointer to this SimpleThread's ThreadContext. Used 176 * when a ThreadContext must be passed to objects outside of the 177 * CPU. 178 */ 179 ThreadContext *getTC() { return tc; } 180 181 void demapPage(Addr vaddr, uint64_t asn) 182 { 183 itb->demapPage(vaddr, asn); 184 dtb->demapPage(vaddr, asn); 185 } 186 187 void demapInstPage(Addr vaddr, uint64_t asn) 188 { 189 itb->demapPage(vaddr, asn); 190 } 191 192 void demapDataPage(Addr vaddr, uint64_t asn) 193 { 194 dtb->demapPage(vaddr, asn); 195 } 196 197#if FULL_SYSTEM 198 void dumpFuncProfile(); 199 200 Fault hwrei(); 201 202 bool simPalCheck(int palFunc); 203 204#endif 205 206 /******************************************* 207 * ThreadContext interface functions. 208 ******************************************/ 209 210 BaseCPU *getCpuPtr() { return cpu; } 211 212 TheISA::TLB *getITBPtr() { return itb; } 213 214 TheISA::TLB *getDTBPtr() { return dtb; } 215 216 System *getSystemPtr() { return system; } 217 218#if FULL_SYSTEM 219 FunctionalPort *getPhysPort() { return physPort; } 220 221 /** Return a virtual port. This port cannot be cached locally in an object. 222 * After a CPU switch it may point to the wrong memory object which could 223 * mean stale data. 224 */ 225 VirtualPort *getVirtPort() { return virtPort; } 226#endif 227 228 Status status() const { return _status; } 229 230 void setStatus(Status newStatus) { _status = newStatus; } 231 232 /// Set the status to Active. Optional delay indicates number of 233 /// cycles to wait before beginning execution. 234 void activate(int delay = 1); 235 236 /// Set the status to Suspended. 237 void suspend(); 238 239 /// Set the status to Halted. 240 void halt(); 241 242 virtual bool misspeculating(); 243 244 void copyArchRegs(ThreadContext *tc); 245 246 void clearArchRegs() 247 { 248 microPC = 0; 249 nextMicroPC = 1; 250 PC = nextPC = nextNPC = 0; 251 memset(intRegs, 0, sizeof(intRegs)); 252 memset(floatRegs.i, 0, sizeof(floatRegs.i)); 253 isa.clear(); 254 } 255 256 // 257 // New accessors for new decoder. 258 // 259 uint64_t readIntReg(int reg_idx) 260 { 261 int flatIndex = isa.flattenIntIndex(reg_idx); 262 assert(flatIndex < TheISA::NumIntRegs); 263 uint64_t regVal = intRegs[flatIndex]; 264 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 265 reg_idx, flatIndex, regVal); 266 return regVal; 267 } 268 269 FloatReg readFloatReg(int reg_idx) 270 { 271 int flatIndex = isa.flattenFloatIndex(reg_idx); 272 assert(flatIndex < TheISA::NumFloatRegs); 273 FloatReg regVal = floatRegs.f[flatIndex]; 274 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 275 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 276 return regVal; 277 } 278 279 FloatRegBits readFloatRegBits(int reg_idx) 280 { 281 int flatIndex = isa.flattenFloatIndex(reg_idx); 282 assert(flatIndex < TheISA::NumFloatRegs); 283 FloatRegBits regVal = floatRegs.i[flatIndex]; 284 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 285 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 286 return regVal; 287 } 288 289 void setIntReg(int reg_idx, uint64_t val) 290 { 291 int flatIndex = isa.flattenIntIndex(reg_idx); 292 assert(flatIndex < TheISA::NumIntRegs); 293 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 294 reg_idx, flatIndex, val); 295 intRegs[flatIndex] = val; 296 } 297 298 void setFloatReg(int reg_idx, FloatReg val) 299 { 300 int flatIndex = isa.flattenFloatIndex(reg_idx); 301 assert(flatIndex < TheISA::NumFloatRegs); 302 floatRegs.f[flatIndex] = val; 303 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 304 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 305 } 306 307 void setFloatRegBits(int reg_idx, FloatRegBits val) 308 { 309 int flatIndex = isa.flattenFloatIndex(reg_idx); 310 assert(flatIndex < TheISA::NumFloatRegs); 311 floatRegs.i[flatIndex] = val; 312 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 313 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 314 } 315 316 uint64_t readPC() 317 { 318 return PC; 319 } 320 321 void setPC(uint64_t val) 322 { 323 PC = val; 324 } 325 326 uint64_t readMicroPC() 327 { 328 return microPC; 329 } 330 331 void setMicroPC(uint64_t val) 332 { 333 microPC = val; 334 } 335 336 uint64_t readNextPC() 337 { 338 return nextPC; 339 } 340 341 void setNextPC(uint64_t val) 342 { 343 nextPC = val; 344 } 345 346 uint64_t readNextMicroPC() 347 { 348 return nextMicroPC; 349 } 350 351 void setNextMicroPC(uint64_t val) 352 { 353 nextMicroPC = val; 354 } 355 356 uint64_t readNextNPC() 357 { 358#if ISA_HAS_DELAY_SLOT 359 return nextNPC; 360#else 361 return nextPC + sizeof(TheISA::MachInst); 362#endif 363 } 364 365 void setNextNPC(uint64_t val) 366 { 367#if ISA_HAS_DELAY_SLOT 368 nextNPC = val; 369#endif 370 } 371 372 bool readPredicate() 373 { 374 return predicate; 375 } 376 377 void setPredicate(bool val) 378 { 379 predicate = val; 380 } 381 382 MiscReg 383 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 384 { 385 return isa.readMiscRegNoEffect(misc_reg); 386 } 387 388 MiscReg 389 readMiscReg(int misc_reg, ThreadID tid = 0) 390 { 391 return isa.readMiscReg(misc_reg, tc); 392 } 393 394 void 395 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 396 { 397 return isa.setMiscRegNoEffect(misc_reg, val); 398 } 399 400 void 401 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 402 { 403 return isa.setMiscReg(misc_reg, val, tc); 404 } 405 406 int 407 flattenIntIndex(int reg) 408 { 409 return isa.flattenIntIndex(reg); 410 } 411 412 int 413 flattenFloatIndex(int reg) 414 { 415 return isa.flattenFloatIndex(reg); 416 } 417 418 unsigned readStCondFailures() { return storeCondFailures; } 419 420 void setStCondFailures(unsigned sc_failures) 421 { storeCondFailures = sc_failures; } 422 423#if !FULL_SYSTEM 424 void syscall(int64_t callnum) 425 { 426 process->syscall(callnum, tc); 427 } 428#endif 429}; 430 431 432// for non-speculative execution context, spec_mode is always false 433inline bool 434SimpleThread::misspeculating() 435{ 436 return false; 437} 438 439#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 440