simple_thread.hh revision 6324:a535b2232c08 
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa.hh"
36#include "arch/isa_traits.hh"
37#include "arch/regfile.hh"
38#include "arch/tlb.hh"
39#include "arch/types.hh"
40#include "base/types.hh"
41#include "config/full_system.hh"
42#include "cpu/thread_context.hh"
43#include "cpu/thread_state.hh"
44#include "mem/request.hh"
45#include "sim/byteswap.hh"
46#include "sim/eventq.hh"
47#include "sim/serialize.hh"
48
49class BaseCPU;
50
51#if FULL_SYSTEM
52
53#include "sim/system.hh"
54
55class FunctionProfile;
56class ProfileNode;
57class FunctionalPort;
58class PhysicalPort;
59
60namespace TheISA {
61    namespace Kernel {
62        class Statistics;
63    };
64};
65
66#else // !FULL_SYSTEM
67
68#include "sim/process.hh"
69#include "mem/page_table.hh"
70class TranslatingPort;
71
72#endif // FULL_SYSTEM
73
74/**
75 * The SimpleThread object provides a combination of the ThreadState
76 * object and the ThreadContext interface. It implements the
77 * ThreadContext interface so that a ProxyThreadContext class can be
78 * made using SimpleThread as the template parameter (see
79 * thread_context.hh). It adds to the ThreadState object by adding all
80 * the objects needed for simple functional execution, including a
81 * simple architectural register file, and pointers to the ITB and DTB
82 * in full system mode. For CPU models that do not need more advanced
83 * ways to hold state (i.e. a separate physical register file, or
84 * separate fetch and commit PC's), this SimpleThread class provides
85 * all the necessary state for full architecture-level functional
86 * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
87 * examples.
88 */
89
90class SimpleThread : public ThreadState
91{
92  protected:
93    typedef TheISA::RegFile RegFile;
94    typedef TheISA::MachInst MachInst;
95    typedef TheISA::MiscReg MiscReg;
96    typedef TheISA::FloatReg FloatReg;
97    typedef TheISA::FloatRegBits FloatRegBits;
98  public:
99    typedef ThreadContext::Status Status;
100
101  protected:
102    RegFile regs;       // correct-path register context
103    union {
104        FloatReg f[TheISA::NumFloatRegs];
105        FloatRegBits i[TheISA::NumFloatRegs];
106    } floatRegs;
107    TheISA::IntReg intRegs[TheISA::NumIntRegs];
108    TheISA::ISA isa;    // one "instance" of the current ISA.
109
110    /** The current microcode pc for the currently executing macro
111     * operation.
112     */
113    MicroPC microPC;
114
115    /** The next microcode pc for the currently executing macro
116     * operation.
117     */
118    MicroPC nextMicroPC;
119
120    /** The current pc.
121     */
122    Addr PC;
123
124    /** The next pc.
125     */
126    Addr nextPC;
127
128    /** The next next pc.
129     */
130    Addr nextNPC;
131
132  public:
133    // pointer to CPU associated with this SimpleThread
134    BaseCPU *cpu;
135
136    ProxyThreadContext<SimpleThread> *tc;
137
138    System *system;
139
140    TheISA::TLB *itb;
141    TheISA::TLB *dtb;
142
143    // constructor: initialize SimpleThread from given process structure
144#if FULL_SYSTEM
145    SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
146                 TheISA::TLB *_itb, TheISA::TLB *_dtb,
147                 bool use_kernel_stats = true);
148#else
149    SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
150                 TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid);
151#endif
152
153    SimpleThread();
154
155    virtual ~SimpleThread();
156
157    virtual void takeOverFrom(ThreadContext *oldContext);
158
159    void regStats(const std::string &name);
160
161    void copyTC(ThreadContext *context);
162
163    void copyState(ThreadContext *oldContext);
164
165    void serialize(std::ostream &os);
166    void unserialize(Checkpoint *cp, const std::string &section);
167
168    /***************************************************************
169     *  SimpleThread functions to provide CPU with access to various
170     *  state.
171     **************************************************************/
172
173    /** Returns the pointer to this SimpleThread's ThreadContext. Used
174     *  when a ThreadContext must be passed to objects outside of the
175     *  CPU.
176     */
177    ThreadContext *getTC() { return tc; }
178
179    void demapPage(Addr vaddr, uint64_t asn)
180    {
181        itb->demapPage(vaddr, asn);
182        dtb->demapPage(vaddr, asn);
183    }
184
185    void demapInstPage(Addr vaddr, uint64_t asn)
186    {
187        itb->demapPage(vaddr, asn);
188    }
189
190    void demapDataPage(Addr vaddr, uint64_t asn)
191    {
192        dtb->demapPage(vaddr, asn);
193    }
194
195#if FULL_SYSTEM
196    int getInstAsid() { return isa.instAsid(); }
197    int getDataAsid() { return isa.dataAsid(); }
198
199    void dumpFuncProfile();
200
201    Fault hwrei();
202
203    bool simPalCheck(int palFunc);
204
205#endif
206
207    /*******************************************
208     * ThreadContext interface functions.
209     ******************************************/
210
211    BaseCPU *getCpuPtr() { return cpu; }
212
213    TheISA::TLB *getITBPtr() { return itb; }
214
215    TheISA::TLB *getDTBPtr() { return dtb; }
216
217    System *getSystemPtr() { return system; }
218
219#if FULL_SYSTEM
220    FunctionalPort *getPhysPort() { return physPort; }
221
222    /** Return a virtual port. This port cannot be cached locally in an object.
223     * After a CPU switch it may point to the wrong memory object which could
224     * mean stale data.
225     */
226    VirtualPort *getVirtPort() { return virtPort; }
227#endif
228
229    Status status() const { return _status; }
230
231    void setStatus(Status newStatus) { _status = newStatus; }
232
233    /// Set the status to Active.  Optional delay indicates number of
234    /// cycles to wait before beginning execution.
235    void activate(int delay = 1);
236
237    /// Set the status to Suspended.
238    void suspend();
239
240    /// Set the status to Halted.
241    void halt();
242
243    virtual bool misspeculating();
244
245    Fault instRead(RequestPtr &req)
246    {
247        panic("instRead not implemented");
248        // return funcPhysMem->read(req, inst);
249        return NoFault;
250    }
251
252    void copyArchRegs(ThreadContext *tc);
253
254    void clearArchRegs()
255    {
256        regs.clear();
257        microPC = 0;
258        nextMicroPC = 1;
259        PC = nextPC = nextNPC = 0;
260        memset(intRegs, 0, sizeof(intRegs));
261        memset(floatRegs.i, 0, sizeof(floatRegs.i));
262    }
263
264    //
265    // New accessors for new decoder.
266    //
267    uint64_t readIntReg(int reg_idx)
268    {
269        int flatIndex = isa.flattenIntIndex(reg_idx);
270        assert(flatIndex < TheISA::NumIntRegs);
271        return intRegs[flatIndex];
272    }
273
274    FloatReg readFloatReg(int reg_idx)
275    {
276        int flatIndex = isa.flattenFloatIndex(reg_idx);
277        assert(flatIndex < TheISA::NumFloatRegs);
278        return floatRegs.f[flatIndex];
279    }
280
281    FloatRegBits readFloatRegBits(int reg_idx)
282    {
283        int flatIndex = isa.flattenFloatIndex(reg_idx);
284        assert(flatIndex < TheISA::NumFloatRegs);
285        return floatRegs.i[flatIndex];
286    }
287
288    void setIntReg(int reg_idx, uint64_t val)
289    {
290        int flatIndex = isa.flattenIntIndex(reg_idx);
291        assert(flatIndex < TheISA::NumIntRegs);
292        intRegs[flatIndex] = val;
293    }
294
295    void setFloatReg(int reg_idx, FloatReg val)
296    {
297        int flatIndex = isa.flattenFloatIndex(reg_idx);
298        assert(flatIndex < TheISA::NumFloatRegs);
299        floatRegs.f[flatIndex] = val;
300    }
301
302    void setFloatRegBits(int reg_idx, FloatRegBits val)
303    {
304        int flatIndex = isa.flattenFloatIndex(reg_idx);
305        assert(flatIndex < TheISA::NumFloatRegs);
306        floatRegs.i[flatIndex] = val;
307    }
308
309    uint64_t readPC()
310    {
311        return PC;
312    }
313
314    void setPC(uint64_t val)
315    {
316        PC = val;
317    }
318
319    uint64_t readMicroPC()
320    {
321        return microPC;
322    }
323
324    void setMicroPC(uint64_t val)
325    {
326        microPC = val;
327    }
328
329    uint64_t readNextPC()
330    {
331        return nextPC;
332    }
333
334    void setNextPC(uint64_t val)
335    {
336        nextPC = val;
337    }
338
339    uint64_t readNextMicroPC()
340    {
341        return nextMicroPC;
342    }
343
344    void setNextMicroPC(uint64_t val)
345    {
346        nextMicroPC = val;
347    }
348
349    uint64_t readNextNPC()
350    {
351#if ISA_HAS_DELAY_SLOT
352        return nextNPC;
353#else
354        return nextPC + sizeof(TheISA::MachInst);
355#endif
356    }
357
358    void setNextNPC(uint64_t val)
359    {
360#if ISA_HAS_DELAY_SLOT
361        nextNPC = val;
362#endif
363    }
364
365    MiscReg
366    readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
367    {
368        return isa.readMiscRegNoEffect(misc_reg);
369    }
370
371    MiscReg
372    readMiscReg(int misc_reg, ThreadID tid = 0)
373    {
374        return isa.readMiscReg(misc_reg, tc);
375    }
376
377    void
378    setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
379    {
380        return isa.setMiscRegNoEffect(misc_reg, val);
381    }
382
383    void
384    setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
385    {
386        return isa.setMiscReg(misc_reg, val, tc);
387    }
388
389    int
390    flattenIntIndex(int reg)
391    {
392        return isa.flattenIntIndex(reg);
393    }
394
395    int
396    flattenFloatIndex(int reg)
397    {
398        return isa.flattenFloatIndex(reg);
399    }
400
401    unsigned readStCondFailures() { return storeCondFailures; }
402
403    void setStCondFailures(unsigned sc_failures)
404    { storeCondFailures = sc_failures; }
405
406#if !FULL_SYSTEM
407    void syscall(int64_t callnum)
408    {
409        process->syscall(callnum, tc);
410    }
411#endif
412};
413
414
415// for non-speculative execution context, spec_mode is always false
416inline bool
417SimpleThread::misspeculating()
418{
419    return false;
420}
421
422#endif // __CPU_CPU_EXEC_CONTEXT_HH__
423