simple_thread.hh revision 6029:007c36616f47
1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_SIMPLE_THREAD_HH__ 33#define __CPU_SIMPLE_THREAD_HH__ 34 35#include "arch/isa_traits.hh" 36#include "arch/regfile.hh" 37#include "arch/tlb.hh" 38#include "config/full_system.hh" 39#include "cpu/thread_context.hh" 40#include "cpu/thread_state.hh" 41#include "mem/request.hh" 42#include "sim/byteswap.hh" 43#include "sim/eventq.hh" 44#include "sim/host.hh" 45#include "sim/serialize.hh" 46 47class BaseCPU; 48 49#if FULL_SYSTEM 50 51#include "sim/system.hh" 52 53class FunctionProfile; 54class ProfileNode; 55class FunctionalPort; 56class PhysicalPort; 57 58namespace TheISA { 59 namespace Kernel { 60 class Statistics; 61 }; 62}; 63 64#else // !FULL_SYSTEM 65 66#include "sim/process.hh" 67#include "mem/page_table.hh" 68class TranslatingPort; 69 70#endif // FULL_SYSTEM 71 72/** 73 * The SimpleThread object provides a combination of the ThreadState 74 * object and the ThreadContext interface. It implements the 75 * ThreadContext interface so that a ProxyThreadContext class can be 76 * made using SimpleThread as the template parameter (see 77 * thread_context.hh). It adds to the ThreadState object by adding all 78 * the objects needed for simple functional execution, including a 79 * simple architectural register file, and pointers to the ITB and DTB 80 * in full system mode. For CPU models that do not need more advanced 81 * ways to hold state (i.e. a separate physical register file, or 82 * separate fetch and commit PC's), this SimpleThread class provides 83 * all the necessary state for full architecture-level functional 84 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 85 * examples. 86 */ 87 88class SimpleThread : public ThreadState 89{ 90 protected: 91 typedef TheISA::RegFile RegFile; 92 typedef TheISA::MachInst MachInst; 93 typedef TheISA::MiscRegFile MiscRegFile; 94 typedef TheISA::MiscReg MiscReg; 95 typedef TheISA::FloatReg FloatReg; 96 typedef TheISA::FloatRegBits FloatRegBits; 97 public: 98 typedef ThreadContext::Status Status; 99 100 protected: 101 RegFile regs; // correct-path register context 102 103 public: 104 // pointer to CPU associated with this SimpleThread 105 BaseCPU *cpu; 106 107 ProxyThreadContext<SimpleThread> *tc; 108 109 System *system; 110 111 TheISA::TLB *itb; 112 TheISA::TLB *dtb; 113 114 // constructor: initialize SimpleThread from given process structure 115#if FULL_SYSTEM 116 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 117 TheISA::TLB *_itb, TheISA::TLB *_dtb, 118 bool use_kernel_stats = true); 119#else 120 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 121 TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid); 122#endif 123 124 SimpleThread(); 125 126 virtual ~SimpleThread(); 127 128 virtual void takeOverFrom(ThreadContext *oldContext); 129 130 void regStats(const std::string &name); 131 132 void copyTC(ThreadContext *context); 133 134 void copyState(ThreadContext *oldContext); 135 136 void serialize(std::ostream &os); 137 void unserialize(Checkpoint *cp, const std::string §ion); 138 139 /*************************************************************** 140 * SimpleThread functions to provide CPU with access to various 141 * state. 142 **************************************************************/ 143 144 /** Returns the pointer to this SimpleThread's ThreadContext. Used 145 * when a ThreadContext must be passed to objects outside of the 146 * CPU. 147 */ 148 ThreadContext *getTC() { return tc; } 149 150 void demapPage(Addr vaddr, uint64_t asn) 151 { 152 itb->demapPage(vaddr, asn); 153 dtb->demapPage(vaddr, asn); 154 } 155 156 void demapInstPage(Addr vaddr, uint64_t asn) 157 { 158 itb->demapPage(vaddr, asn); 159 } 160 161 void demapDataPage(Addr vaddr, uint64_t asn) 162 { 163 dtb->demapPage(vaddr, asn); 164 } 165 166#if FULL_SYSTEM 167 int getInstAsid() { return regs.instAsid(); } 168 int getDataAsid() { return regs.dataAsid(); } 169 170 void dumpFuncProfile(); 171 172 Fault hwrei(); 173 174 bool simPalCheck(int palFunc); 175 176#endif 177 178 /******************************************* 179 * ThreadContext interface functions. 180 ******************************************/ 181 182 BaseCPU *getCpuPtr() { return cpu; } 183 184 TheISA::TLB *getITBPtr() { return itb; } 185 186 TheISA::TLB *getDTBPtr() { return dtb; } 187 188 System *getSystemPtr() { return system; } 189 190#if FULL_SYSTEM 191 FunctionalPort *getPhysPort() { return physPort; } 192 193 /** Return a virtual port. This port cannot be cached locally in an object. 194 * After a CPU switch it may point to the wrong memory object which could 195 * mean stale data. 196 */ 197 VirtualPort *getVirtPort() { return virtPort; } 198#endif 199 200 Status status() const { return _status; } 201 202 void setStatus(Status newStatus) { _status = newStatus; } 203 204 /// Set the status to Active. Optional delay indicates number of 205 /// cycles to wait before beginning execution. 206 void activate(int delay = 1); 207 208 /// Set the status to Suspended. 209 void suspend(); 210 211 /// Set the status to Halted. 212 void halt(); 213 214 virtual bool misspeculating(); 215 216 Fault instRead(RequestPtr &req) 217 { 218 panic("instRead not implemented"); 219 // return funcPhysMem->read(req, inst); 220 return NoFault; 221 } 222 223 void copyArchRegs(ThreadContext *tc); 224 225 void clearArchRegs() { regs.clear(); } 226 227 // 228 // New accessors for new decoder. 229 // 230 uint64_t readIntReg(int reg_idx) 231 { 232 int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); 233 return regs.readIntReg(flatIndex); 234 } 235 236 FloatReg readFloatReg(int reg_idx, int width) 237 { 238 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 239 return regs.readFloatReg(flatIndex, width); 240 } 241 242 FloatReg readFloatReg(int reg_idx) 243 { 244 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 245 return regs.readFloatReg(flatIndex); 246 } 247 248 FloatRegBits readFloatRegBits(int reg_idx, int width) 249 { 250 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 251 return regs.readFloatRegBits(flatIndex, width); 252 } 253 254 FloatRegBits readFloatRegBits(int reg_idx) 255 { 256 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 257 return regs.readFloatRegBits(flatIndex); 258 } 259 260 void setIntReg(int reg_idx, uint64_t val) 261 { 262 int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); 263 regs.setIntReg(flatIndex, val); 264 } 265 266 void setFloatReg(int reg_idx, FloatReg val, int width) 267 { 268 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 269 regs.setFloatReg(flatIndex, val, width); 270 } 271 272 void setFloatReg(int reg_idx, FloatReg val) 273 { 274 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 275 regs.setFloatReg(flatIndex, val); 276 } 277 278 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 279 { 280 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 281 regs.setFloatRegBits(flatIndex, val, width); 282 } 283 284 void setFloatRegBits(int reg_idx, FloatRegBits val) 285 { 286 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 287 regs.setFloatRegBits(flatIndex, val); 288 } 289 290 uint64_t readPC() 291 { 292 return regs.readPC(); 293 } 294 295 void setPC(uint64_t val) 296 { 297 regs.setPC(val); 298 } 299 300 uint64_t readMicroPC() 301 { 302 return microPC; 303 } 304 305 void setMicroPC(uint64_t val) 306 { 307 microPC = val; 308 } 309 310 uint64_t readNextPC() 311 { 312 return regs.readNextPC(); 313 } 314 315 void setNextPC(uint64_t val) 316 { 317 regs.setNextPC(val); 318 } 319 320 uint64_t readNextMicroPC() 321 { 322 return nextMicroPC; 323 } 324 325 void setNextMicroPC(uint64_t val) 326 { 327 nextMicroPC = val; 328 } 329 330 uint64_t readNextNPC() 331 { 332 return regs.readNextNPC(); 333 } 334 335 void setNextNPC(uint64_t val) 336 { 337 regs.setNextNPC(val); 338 } 339 340 MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0) 341 { 342 return regs.readMiscRegNoEffect(misc_reg); 343 } 344 345 MiscReg readMiscReg(int misc_reg, unsigned tid = 0) 346 { 347 return regs.readMiscReg(misc_reg, tc); 348 } 349 350 void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0) 351 { 352 return regs.setMiscRegNoEffect(misc_reg, val); 353 } 354 355 void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0) 356 { 357 return regs.setMiscReg(misc_reg, val, tc); 358 } 359 360 unsigned readStCondFailures() { return storeCondFailures; } 361 362 void setStCondFailures(unsigned sc_failures) 363 { storeCondFailures = sc_failures; } 364 365#if !FULL_SYSTEM 366 void syscall(int64_t callnum) 367 { 368 process->syscall(callnum, tc); 369 } 370#endif 371}; 372 373 374// for non-speculative execution context, spec_mode is always false 375inline bool 376SimpleThread::misspeculating() 377{ 378 return false; 379} 380 381#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 382