simple_thread.hh revision 6022
1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_SIMPLE_THREAD_HH__ 33#define __CPU_SIMPLE_THREAD_HH__ 34 35#include "arch/isa_traits.hh" 36#include "arch/regfile.hh" 37#include "arch/tlb.hh" 38#include "config/full_system.hh" 39#include "cpu/thread_context.hh" 40#include "cpu/thread_state.hh" 41#include "mem/request.hh" 42#include "sim/byteswap.hh" 43#include "sim/eventq.hh" 44#include "sim/host.hh" 45#include "sim/serialize.hh" 46 47class BaseCPU; 48 49#if FULL_SYSTEM 50 51#include "sim/system.hh" 52 53class FunctionProfile; 54class ProfileNode; 55class FunctionalPort; 56class PhysicalPort; 57 58namespace TheISA { 59 namespace Kernel { 60 class Statistics; 61 }; 62}; 63 64#else // !FULL_SYSTEM 65 66#include "sim/process.hh" 67#include "mem/page_table.hh" 68class TranslatingPort; 69 70#endif // FULL_SYSTEM 71 72/** 73 * The SimpleThread object provides a combination of the ThreadState 74 * object and the ThreadContext interface. It implements the 75 * ThreadContext interface so that a ProxyThreadContext class can be 76 * made using SimpleThread as the template parameter (see 77 * thread_context.hh). It adds to the ThreadState object by adding all 78 * the objects needed for simple functional execution, including a 79 * simple architectural register file, and pointers to the ITB and DTB 80 * in full system mode. For CPU models that do not need more advanced 81 * ways to hold state (i.e. a separate physical register file, or 82 * separate fetch and commit PC's), this SimpleThread class provides 83 * all the necessary state for full architecture-level functional 84 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 85 * examples. 86 */ 87 88class SimpleThread : public ThreadState 89{ 90 protected: 91 typedef TheISA::RegFile RegFile; 92 typedef TheISA::MachInst MachInst; 93 typedef TheISA::MiscRegFile MiscRegFile; 94 typedef TheISA::MiscReg MiscReg; 95 typedef TheISA::FloatReg FloatReg; 96 typedef TheISA::FloatRegBits FloatRegBits; 97 public: 98 typedef ThreadContext::Status Status; 99 100 protected: 101 RegFile regs; // correct-path register context 102 103 public: 104 // pointer to CPU associated with this SimpleThread 105 BaseCPU *cpu; 106 107 ProxyThreadContext<SimpleThread> *tc; 108 109 System *system; 110 111 TheISA::TLB *itb; 112 TheISA::TLB *dtb; 113 114 // constructor: initialize SimpleThread from given process structure 115#if FULL_SYSTEM 116 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 117 TheISA::TLB *_itb, TheISA::TLB *_dtb, 118 bool use_kernel_stats = true); 119#else 120 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 121 TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid); 122#endif 123 124 SimpleThread(); 125 126 virtual ~SimpleThread(); 127 128 virtual void takeOverFrom(ThreadContext *oldContext); 129 130 void regStats(const std::string &name); 131 132 void copyTC(ThreadContext *context); 133 134 void copyState(ThreadContext *oldContext); 135 136 void serialize(std::ostream &os); 137 void unserialize(Checkpoint *cp, const std::string §ion); 138 139 /*************************************************************** 140 * SimpleThread functions to provide CPU with access to various 141 * state. 142 **************************************************************/ 143 144 /** Returns the pointer to this SimpleThread's ThreadContext. Used 145 * when a ThreadContext must be passed to objects outside of the 146 * CPU. 147 */ 148 ThreadContext *getTC() { return tc; } 149 150 void demapPage(Addr vaddr, uint64_t asn) 151 { 152 itb->demapPage(vaddr, asn); 153 dtb->demapPage(vaddr, asn); 154 } 155 156 void demapInstPage(Addr vaddr, uint64_t asn) 157 { 158 itb->demapPage(vaddr, asn); 159 } 160 161 void demapDataPage(Addr vaddr, uint64_t asn) 162 { 163 dtb->demapPage(vaddr, asn); 164 } 165 166#if FULL_SYSTEM 167 int getInstAsid() { return regs.instAsid(); } 168 int getDataAsid() { return regs.dataAsid(); } 169 170 void dumpFuncProfile(); 171 172 Fault hwrei(); 173 174 bool simPalCheck(int palFunc); 175 176#endif 177 178 /******************************************* 179 * ThreadContext interface functions. 180 ******************************************/ 181 182 BaseCPU *getCpuPtr() { return cpu; } 183 184 TheISA::TLB *getITBPtr() { return itb; } 185 186 TheISA::TLB *getDTBPtr() { return dtb; } 187 188 System *getSystemPtr() { return system; } 189 190#if FULL_SYSTEM 191 FunctionalPort *getPhysPort() { return physPort; } 192 193 /** Return a virtual port. This port cannot be cached locally in an object. 194 * After a CPU switch it may point to the wrong memory object which could 195 * mean stale data. 196 */ 197 VirtualPort *getVirtPort() { return virtPort; } 198#endif 199 200 Status status() const { return _status; } 201 202 void setStatus(Status newStatus) { _status = newStatus; } 203 204 /// Set the status to Active. Optional delay indicates number of 205 /// cycles to wait before beginning execution. 206 void activate(int delay = 1); 207 208 /// Set the status to Suspended. 209 void suspend(); 210 211 /// Set the status to Unallocated. 212 void deallocate(); 213 214 /// Set the status to Halted. 215 void halt(); 216 217 virtual bool misspeculating(); 218 219 Fault instRead(RequestPtr &req) 220 { 221 panic("instRead not implemented"); 222 // return funcPhysMem->read(req, inst); 223 return NoFault; 224 } 225 226 void copyArchRegs(ThreadContext *tc); 227 228 void clearArchRegs() { regs.clear(); } 229 230 // 231 // New accessors for new decoder. 232 // 233 uint64_t readIntReg(int reg_idx) 234 { 235 int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); 236 return regs.readIntReg(flatIndex); 237 } 238 239 FloatReg readFloatReg(int reg_idx, int width) 240 { 241 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 242 return regs.readFloatReg(flatIndex, width); 243 } 244 245 FloatReg readFloatReg(int reg_idx) 246 { 247 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 248 return regs.readFloatReg(flatIndex); 249 } 250 251 FloatRegBits readFloatRegBits(int reg_idx, int width) 252 { 253 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 254 return regs.readFloatRegBits(flatIndex, width); 255 } 256 257 FloatRegBits readFloatRegBits(int reg_idx) 258 { 259 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 260 return regs.readFloatRegBits(flatIndex); 261 } 262 263 void setIntReg(int reg_idx, uint64_t val) 264 { 265 int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); 266 regs.setIntReg(flatIndex, val); 267 } 268 269 void setFloatReg(int reg_idx, FloatReg val, int width) 270 { 271 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 272 regs.setFloatReg(flatIndex, val, width); 273 } 274 275 void setFloatReg(int reg_idx, FloatReg val) 276 { 277 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 278 regs.setFloatReg(flatIndex, val); 279 } 280 281 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 282 { 283 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 284 regs.setFloatRegBits(flatIndex, val, width); 285 } 286 287 void setFloatRegBits(int reg_idx, FloatRegBits val) 288 { 289 int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 290 regs.setFloatRegBits(flatIndex, val); 291 } 292 293 uint64_t readPC() 294 { 295 return regs.readPC(); 296 } 297 298 void setPC(uint64_t val) 299 { 300 regs.setPC(val); 301 } 302 303 uint64_t readMicroPC() 304 { 305 return microPC; 306 } 307 308 void setMicroPC(uint64_t val) 309 { 310 microPC = val; 311 } 312 313 uint64_t readNextPC() 314 { 315 return regs.readNextPC(); 316 } 317 318 void setNextPC(uint64_t val) 319 { 320 regs.setNextPC(val); 321 } 322 323 uint64_t readNextMicroPC() 324 { 325 return nextMicroPC; 326 } 327 328 void setNextMicroPC(uint64_t val) 329 { 330 nextMicroPC = val; 331 } 332 333 uint64_t readNextNPC() 334 { 335 return regs.readNextNPC(); 336 } 337 338 void setNextNPC(uint64_t val) 339 { 340 regs.setNextNPC(val); 341 } 342 343 MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0) 344 { 345 return regs.readMiscRegNoEffect(misc_reg); 346 } 347 348 MiscReg readMiscReg(int misc_reg, unsigned tid = 0) 349 { 350 return regs.readMiscReg(misc_reg, tc); 351 } 352 353 void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0) 354 { 355 return regs.setMiscRegNoEffect(misc_reg, val); 356 } 357 358 void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0) 359 { 360 return regs.setMiscReg(misc_reg, val, tc); 361 } 362 363 unsigned readStCondFailures() { return storeCondFailures; } 364 365 void setStCondFailures(unsigned sc_failures) 366 { storeCondFailures = sc_failures; } 367 368#if !FULL_SYSTEM 369 void syscall(int64_t callnum) 370 { 371 process->syscall(callnum, tc); 372 } 373#endif 374}; 375 376 377// for non-speculative execution context, spec_mode is always false 378inline bool 379SimpleThread::misspeculating() 380{ 381 return false; 382} 383 384#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 385