simple_thread.hh revision 5088:2d5e28510f27
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2001-2006 The Regents of The University of Michigan 310259SAndrew.Bardsley@arm.com * All rights reserved. 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 610259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 710259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 810259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 910259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 1110259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 1210259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 1310259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 1410259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 1510259SAndrew.Bardsley@arm.com * 1610259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710259SAndrew.Bardsley@arm.com * 2810259SAndrew.Bardsley@arm.com * Authors: Steve Reinhardt 2910259SAndrew.Bardsley@arm.com * Nathan Binkert 3010259SAndrew.Bardsley@arm.com */ 3110259SAndrew.Bardsley@arm.com 3210259SAndrew.Bardsley@arm.com#ifndef __CPU_SIMPLE_THREAD_HH__ 3310259SAndrew.Bardsley@arm.com#define __CPU_SIMPLE_THREAD_HH__ 3410259SAndrew.Bardsley@arm.com 3510259SAndrew.Bardsley@arm.com#include "arch/isa_traits.hh" 3610259SAndrew.Bardsley@arm.com#include "arch/regfile.hh" 3710259SAndrew.Bardsley@arm.com#include "arch/syscallreturn.hh" 3810259SAndrew.Bardsley@arm.com#include "arch/tlb.hh" 3910259SAndrew.Bardsley@arm.com#include "config/full_system.hh" 4010259SAndrew.Bardsley@arm.com#include "cpu/thread_context.hh" 4110259SAndrew.Bardsley@arm.com#include "cpu/thread_state.hh" 4210259SAndrew.Bardsley@arm.com#include "mem/request.hh" 4310259SAndrew.Bardsley@arm.com#include "sim/byteswap.hh" 4410259SAndrew.Bardsley@arm.com#include "sim/eventq.hh" 4510259SAndrew.Bardsley@arm.com#include "sim/host.hh" 4610259SAndrew.Bardsley@arm.com#include "sim/serialize.hh" 4710259SAndrew.Bardsley@arm.com 4810259SAndrew.Bardsley@arm.comclass BaseCPU; 4910259SAndrew.Bardsley@arm.com 5010259SAndrew.Bardsley@arm.com#if FULL_SYSTEM 5110259SAndrew.Bardsley@arm.com 5210259SAndrew.Bardsley@arm.com#include "sim/system.hh" 5310259SAndrew.Bardsley@arm.com 5410259SAndrew.Bardsley@arm.comclass FunctionProfile; 5510259SAndrew.Bardsley@arm.comclass ProfileNode; 5610259SAndrew.Bardsley@arm.comclass FunctionalPort; 5710259SAndrew.Bardsley@arm.comclass PhysicalPort; 5810259SAndrew.Bardsley@arm.com 5910259SAndrew.Bardsley@arm.comnamespace TheISA { 6010259SAndrew.Bardsley@arm.com namespace Kernel { 6110259SAndrew.Bardsley@arm.com class Statistics; 6210259SAndrew.Bardsley@arm.com }; 6310259SAndrew.Bardsley@arm.com}; 6410259SAndrew.Bardsley@arm.com 6510259SAndrew.Bardsley@arm.com#else // !FULL_SYSTEM 6610259SAndrew.Bardsley@arm.com 6710259SAndrew.Bardsley@arm.com#include "sim/process.hh" 6810259SAndrew.Bardsley@arm.com#include "mem/page_table.hh" 6910259SAndrew.Bardsley@arm.comclass TranslatingPort; 7010259SAndrew.Bardsley@arm.com 7110259SAndrew.Bardsley@arm.com#endif // FULL_SYSTEM 7210259SAndrew.Bardsley@arm.com 7310259SAndrew.Bardsley@arm.com/** 7410259SAndrew.Bardsley@arm.com * The SimpleThread object provides a combination of the ThreadState 7510259SAndrew.Bardsley@arm.com * object and the ThreadContext interface. It implements the 7610259SAndrew.Bardsley@arm.com * ThreadContext interface so that a ProxyThreadContext class can be 7710259SAndrew.Bardsley@arm.com * made using SimpleThread as the template parameter (see 7810259SAndrew.Bardsley@arm.com * thread_context.hh). It adds to the ThreadState object by adding all 7910259SAndrew.Bardsley@arm.com * the objects needed for simple functional execution, including a 8010259SAndrew.Bardsley@arm.com * simple architectural register file, and pointers to the ITB and DTB 8110259SAndrew.Bardsley@arm.com * in full system mode. For CPU models that do not need more advanced 8210259SAndrew.Bardsley@arm.com * ways to hold state (i.e. a separate physical register file, or 8310259SAndrew.Bardsley@arm.com * separate fetch and commit PC's), this SimpleThread class provides 8410259SAndrew.Bardsley@arm.com * all the necessary state for full architecture-level functional 8510259SAndrew.Bardsley@arm.com * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 8610259SAndrew.Bardsley@arm.com * examples. 8710259SAndrew.Bardsley@arm.com */ 8810259SAndrew.Bardsley@arm.com 8910259SAndrew.Bardsley@arm.comclass SimpleThread : public ThreadState 9010259SAndrew.Bardsley@arm.com{ 9110259SAndrew.Bardsley@arm.com protected: 9210259SAndrew.Bardsley@arm.com typedef TheISA::RegFile RegFile; 9310259SAndrew.Bardsley@arm.com typedef TheISA::MachInst MachInst; 9410259SAndrew.Bardsley@arm.com typedef TheISA::MiscRegFile MiscRegFile; 9510259SAndrew.Bardsley@arm.com typedef TheISA::MiscReg MiscReg; 9610259SAndrew.Bardsley@arm.com typedef TheISA::FloatReg FloatReg; 9710259SAndrew.Bardsley@arm.com typedef TheISA::FloatRegBits FloatRegBits; 9810259SAndrew.Bardsley@arm.com public: 9910259SAndrew.Bardsley@arm.com typedef ThreadContext::Status Status; 10010259SAndrew.Bardsley@arm.com 10110259SAndrew.Bardsley@arm.com protected: 10210259SAndrew.Bardsley@arm.com RegFile regs; // correct-path register context 10310259SAndrew.Bardsley@arm.com 10410259SAndrew.Bardsley@arm.com public: 10510259SAndrew.Bardsley@arm.com // pointer to CPU associated with this SimpleThread 10610259SAndrew.Bardsley@arm.com BaseCPU *cpu; 10710259SAndrew.Bardsley@arm.com 10810259SAndrew.Bardsley@arm.com ProxyThreadContext<SimpleThread> *tc; 10910259SAndrew.Bardsley@arm.com 11010259SAndrew.Bardsley@arm.com System *system; 11110259SAndrew.Bardsley@arm.com 11210259SAndrew.Bardsley@arm.com TheISA::ITB *itb; 11310259SAndrew.Bardsley@arm.com TheISA::DTB *dtb; 11410259SAndrew.Bardsley@arm.com 11510259SAndrew.Bardsley@arm.com // constructor: initialize SimpleThread from given process structure 11610259SAndrew.Bardsley@arm.com#if FULL_SYSTEM 11710259SAndrew.Bardsley@arm.com SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 11810259SAndrew.Bardsley@arm.com TheISA::ITB *_itb, TheISA::DTB *_dtb, 11910259SAndrew.Bardsley@arm.com bool use_kernel_stats = true); 12010259SAndrew.Bardsley@arm.com#else 12110259SAndrew.Bardsley@arm.com SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 12210259SAndrew.Bardsley@arm.com TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid); 12310259SAndrew.Bardsley@arm.com#endif 12410259SAndrew.Bardsley@arm.com 12510259SAndrew.Bardsley@arm.com SimpleThread(); 12610259SAndrew.Bardsley@arm.com 12710259SAndrew.Bardsley@arm.com virtual ~SimpleThread(); 12810259SAndrew.Bardsley@arm.com 12910259SAndrew.Bardsley@arm.com virtual void takeOverFrom(ThreadContext *oldContext); 13010259SAndrew.Bardsley@arm.com 13110259SAndrew.Bardsley@arm.com void regStats(const std::string &name); 13210259SAndrew.Bardsley@arm.com 13310259SAndrew.Bardsley@arm.com void copyTC(ThreadContext *context); 13410259SAndrew.Bardsley@arm.com 13510259SAndrew.Bardsley@arm.com void copyState(ThreadContext *oldContext); 13610259SAndrew.Bardsley@arm.com 13710259SAndrew.Bardsley@arm.com void serialize(std::ostream &os); 13810259SAndrew.Bardsley@arm.com void unserialize(Checkpoint *cp, const std::string §ion); 13910259SAndrew.Bardsley@arm.com 14010259SAndrew.Bardsley@arm.com /*************************************************************** 14110259SAndrew.Bardsley@arm.com * SimpleThread functions to provide CPU with access to various 14210259SAndrew.Bardsley@arm.com * state, and to provide address translation methods. 14310259SAndrew.Bardsley@arm.com **************************************************************/ 14410259SAndrew.Bardsley@arm.com 14510259SAndrew.Bardsley@arm.com /** Returns the pointer to this SimpleThread's ThreadContext. Used 14610259SAndrew.Bardsley@arm.com * when a ThreadContext must be passed to objects outside of the 14710259SAndrew.Bardsley@arm.com * CPU. 14810259SAndrew.Bardsley@arm.com */ 14910259SAndrew.Bardsley@arm.com ThreadContext *getTC() { return tc; } 15010259SAndrew.Bardsley@arm.com 15110259SAndrew.Bardsley@arm.com Fault translateInstReq(RequestPtr &req) 15210259SAndrew.Bardsley@arm.com { 15310259SAndrew.Bardsley@arm.com return itb->translate(req, tc); 15410259SAndrew.Bardsley@arm.com } 15510259SAndrew.Bardsley@arm.com 15610259SAndrew.Bardsley@arm.com Fault translateDataReadReq(RequestPtr &req) 15710259SAndrew.Bardsley@arm.com { 15810259SAndrew.Bardsley@arm.com return dtb->translate(req, tc, false); 15910259SAndrew.Bardsley@arm.com } 16010259SAndrew.Bardsley@arm.com 16110259SAndrew.Bardsley@arm.com Fault translateDataWriteReq(RequestPtr &req) 16210259SAndrew.Bardsley@arm.com { 16310259SAndrew.Bardsley@arm.com return dtb->translate(req, tc, true); 16410259SAndrew.Bardsley@arm.com } 16510259SAndrew.Bardsley@arm.com 16610259SAndrew.Bardsley@arm.com#if FULL_SYSTEM 16710259SAndrew.Bardsley@arm.com int getInstAsid() { return regs.instAsid(); } 16810259SAndrew.Bardsley@arm.com int getDataAsid() { return regs.dataAsid(); } 16910259SAndrew.Bardsley@arm.com 17010259SAndrew.Bardsley@arm.com void dumpFuncProfile(); 17110259SAndrew.Bardsley@arm.com 17210259SAndrew.Bardsley@arm.com Fault hwrei(); 17310259SAndrew.Bardsley@arm.com 17410259SAndrew.Bardsley@arm.com bool simPalCheck(int palFunc); 17510259SAndrew.Bardsley@arm.com 17610259SAndrew.Bardsley@arm.com#endif 17710259SAndrew.Bardsley@arm.com 17810259SAndrew.Bardsley@arm.com /******************************************* 17910259SAndrew.Bardsley@arm.com * ThreadContext interface functions. 18010259SAndrew.Bardsley@arm.com ******************************************/ 18110259SAndrew.Bardsley@arm.com 18210259SAndrew.Bardsley@arm.com BaseCPU *getCpuPtr() { return cpu; } 18310259SAndrew.Bardsley@arm.com 18410259SAndrew.Bardsley@arm.com int getThreadNum() { return tid; } 18510259SAndrew.Bardsley@arm.com 18610259SAndrew.Bardsley@arm.com TheISA::ITB *getITBPtr() { return itb; } 18710259SAndrew.Bardsley@arm.com 18810259SAndrew.Bardsley@arm.com TheISA::DTB *getDTBPtr() { return dtb; } 18910259SAndrew.Bardsley@arm.com 19010259SAndrew.Bardsley@arm.com#if FULL_SYSTEM 19110259SAndrew.Bardsley@arm.com System *getSystemPtr() { return system; } 19210259SAndrew.Bardsley@arm.com 19310259SAndrew.Bardsley@arm.com FunctionalPort *getPhysPort() { return physPort; } 19410259SAndrew.Bardsley@arm.com 19510259SAndrew.Bardsley@arm.com /** Return a virtual port. If no thread context is specified then a static 19610259SAndrew.Bardsley@arm.com * port is returned. Otherwise a port is created and returned. It must be 19710259SAndrew.Bardsley@arm.com * deleted by deleteVirtPort(). */ 19810259SAndrew.Bardsley@arm.com VirtualPort *getVirtPort(ThreadContext *tc); 19910259SAndrew.Bardsley@arm.com 20010259SAndrew.Bardsley@arm.com void delVirtPort(VirtualPort *vp); 20110259SAndrew.Bardsley@arm.com#endif 20210259SAndrew.Bardsley@arm.com 20310259SAndrew.Bardsley@arm.com Status status() const { return _status; } 20410259SAndrew.Bardsley@arm.com 20510259SAndrew.Bardsley@arm.com void setStatus(Status newStatus) { _status = newStatus; } 20610259SAndrew.Bardsley@arm.com 20710259SAndrew.Bardsley@arm.com /// Set the status to Active. Optional delay indicates number of 20810259SAndrew.Bardsley@arm.com /// cycles to wait before beginning execution. 20910259SAndrew.Bardsley@arm.com void activate(int delay = 1); 21010259SAndrew.Bardsley@arm.com 21110259SAndrew.Bardsley@arm.com /// Set the status to Suspended. 21210259SAndrew.Bardsley@arm.com void suspend(); 21310259SAndrew.Bardsley@arm.com 21410259SAndrew.Bardsley@arm.com /// Set the status to Unallocated. 21510259SAndrew.Bardsley@arm.com void deallocate(); 21610259SAndrew.Bardsley@arm.com 21710259SAndrew.Bardsley@arm.com /// Set the status to Halted. 21810259SAndrew.Bardsley@arm.com void halt(); 21910259SAndrew.Bardsley@arm.com 22010259SAndrew.Bardsley@arm.com virtual bool misspeculating(); 22110259SAndrew.Bardsley@arm.com 22210259SAndrew.Bardsley@arm.com Fault instRead(RequestPtr &req) 22310259SAndrew.Bardsley@arm.com { 22410259SAndrew.Bardsley@arm.com panic("instRead not implemented"); 22510259SAndrew.Bardsley@arm.com // return funcPhysMem->read(req, inst); 22610259SAndrew.Bardsley@arm.com return NoFault; 22710259SAndrew.Bardsley@arm.com } 22810259SAndrew.Bardsley@arm.com 22910379Sandreas.hansson@arm.com void copyArchRegs(ThreadContext *tc); 23010379Sandreas.hansson@arm.com 23110259SAndrew.Bardsley@arm.com void clearArchRegs() { regs.clear(); } 23210259SAndrew.Bardsley@arm.com 23310259SAndrew.Bardsley@arm.com // 23410259SAndrew.Bardsley@arm.com // New accessors for new decoder. 23510259SAndrew.Bardsley@arm.com // 23610259SAndrew.Bardsley@arm.com uint64_t readIntReg(int reg_idx) 23710259SAndrew.Bardsley@arm.com { 23810259SAndrew.Bardsley@arm.com int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); 23910259SAndrew.Bardsley@arm.com return regs.readIntReg(flatIndex); 24010259SAndrew.Bardsley@arm.com } 24110259SAndrew.Bardsley@arm.com 24210259SAndrew.Bardsley@arm.com FloatReg readFloatReg(int reg_idx, int width) 24310259SAndrew.Bardsley@arm.com { 24410259SAndrew.Bardsley@arm.com int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 24510259SAndrew.Bardsley@arm.com return regs.readFloatReg(flatIndex, width); 24610259SAndrew.Bardsley@arm.com } 24710259SAndrew.Bardsley@arm.com 24810259SAndrew.Bardsley@arm.com FloatReg readFloatReg(int reg_idx) 24910259SAndrew.Bardsley@arm.com { 25010259SAndrew.Bardsley@arm.com int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 25110259SAndrew.Bardsley@arm.com return regs.readFloatReg(flatIndex); 25210259SAndrew.Bardsley@arm.com } 25310259SAndrew.Bardsley@arm.com 25410259SAndrew.Bardsley@arm.com FloatRegBits readFloatRegBits(int reg_idx, int width) 25510259SAndrew.Bardsley@arm.com { 25610259SAndrew.Bardsley@arm.com int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 25710259SAndrew.Bardsley@arm.com return regs.readFloatRegBits(flatIndex, width); 25810259SAndrew.Bardsley@arm.com } 25910259SAndrew.Bardsley@arm.com 26010259SAndrew.Bardsley@arm.com FloatRegBits readFloatRegBits(int reg_idx) 26110259SAndrew.Bardsley@arm.com { 26210259SAndrew.Bardsley@arm.com int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 26310259SAndrew.Bardsley@arm.com return regs.readFloatRegBits(flatIndex); 26410259SAndrew.Bardsley@arm.com } 26510259SAndrew.Bardsley@arm.com 26610259SAndrew.Bardsley@arm.com void setIntReg(int reg_idx, uint64_t val) 26710259SAndrew.Bardsley@arm.com { 26810259SAndrew.Bardsley@arm.com int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); 26910259SAndrew.Bardsley@arm.com regs.setIntReg(flatIndex, val); 27010259SAndrew.Bardsley@arm.com } 27110259SAndrew.Bardsley@arm.com 27210259SAndrew.Bardsley@arm.com void setFloatReg(int reg_idx, FloatReg val, int width) 27310259SAndrew.Bardsley@arm.com { 27410259SAndrew.Bardsley@arm.com int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 27510259SAndrew.Bardsley@arm.com regs.setFloatReg(flatIndex, val, width); 27610379Sandreas.hansson@arm.com } 27710379Sandreas.hansson@arm.com 27810259SAndrew.Bardsley@arm.com void setFloatReg(int reg_idx, FloatReg val) 27910259SAndrew.Bardsley@arm.com { 28010259SAndrew.Bardsley@arm.com int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 28110259SAndrew.Bardsley@arm.com regs.setFloatReg(flatIndex, val); 28210259SAndrew.Bardsley@arm.com } 28310259SAndrew.Bardsley@arm.com 28410259SAndrew.Bardsley@arm.com void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 28510259SAndrew.Bardsley@arm.com { 28610259SAndrew.Bardsley@arm.com int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 28710259SAndrew.Bardsley@arm.com regs.setFloatRegBits(flatIndex, val, width); 28810259SAndrew.Bardsley@arm.com } 28910259SAndrew.Bardsley@arm.com 29010259SAndrew.Bardsley@arm.com void setFloatRegBits(int reg_idx, FloatRegBits val) 29110259SAndrew.Bardsley@arm.com { 29210259SAndrew.Bardsley@arm.com int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 29310259SAndrew.Bardsley@arm.com regs.setFloatRegBits(flatIndex, val); 29410259SAndrew.Bardsley@arm.com } 29510259SAndrew.Bardsley@arm.com 29610259SAndrew.Bardsley@arm.com uint64_t readPC() 29710259SAndrew.Bardsley@arm.com { 29810259SAndrew.Bardsley@arm.com return regs.readPC(); 29910259SAndrew.Bardsley@arm.com } 30010259SAndrew.Bardsley@arm.com 30110259SAndrew.Bardsley@arm.com void setPC(uint64_t val) 30210259SAndrew.Bardsley@arm.com { 30310259SAndrew.Bardsley@arm.com regs.setPC(val); 30410259SAndrew.Bardsley@arm.com } 30510259SAndrew.Bardsley@arm.com 30610259SAndrew.Bardsley@arm.com uint64_t readMicroPC() 30710259SAndrew.Bardsley@arm.com { 30810259SAndrew.Bardsley@arm.com return microPC; 30910259SAndrew.Bardsley@arm.com } 31010259SAndrew.Bardsley@arm.com 31110259SAndrew.Bardsley@arm.com void setMicroPC(uint64_t val) 31210259SAndrew.Bardsley@arm.com { 31310259SAndrew.Bardsley@arm.com microPC = val; 31410259SAndrew.Bardsley@arm.com } 31510259SAndrew.Bardsley@arm.com 31610259SAndrew.Bardsley@arm.com uint64_t readNextPC() 31710259SAndrew.Bardsley@arm.com { 31810259SAndrew.Bardsley@arm.com return regs.readNextPC(); 31910259SAndrew.Bardsley@arm.com } 32010259SAndrew.Bardsley@arm.com 32110259SAndrew.Bardsley@arm.com void setNextPC(uint64_t val) 32210259SAndrew.Bardsley@arm.com { 32310259SAndrew.Bardsley@arm.com regs.setNextPC(val); 32410259SAndrew.Bardsley@arm.com } 32510259SAndrew.Bardsley@arm.com 32610259SAndrew.Bardsley@arm.com uint64_t readNextMicroPC() 32710259SAndrew.Bardsley@arm.com { 32810259SAndrew.Bardsley@arm.com return nextMicroPC; 32910259SAndrew.Bardsley@arm.com } 33010259SAndrew.Bardsley@arm.com 33110259SAndrew.Bardsley@arm.com void setNextMicroPC(uint64_t val) 33210259SAndrew.Bardsley@arm.com { 33310259SAndrew.Bardsley@arm.com nextMicroPC = val; 33410259SAndrew.Bardsley@arm.com } 33510259SAndrew.Bardsley@arm.com 33610259SAndrew.Bardsley@arm.com uint64_t readNextNPC() 33710259SAndrew.Bardsley@arm.com { 33810259SAndrew.Bardsley@arm.com return regs.readNextNPC(); 33910259SAndrew.Bardsley@arm.com } 34010259SAndrew.Bardsley@arm.com 34110259SAndrew.Bardsley@arm.com void setNextNPC(uint64_t val) 34210259SAndrew.Bardsley@arm.com { 34310259SAndrew.Bardsley@arm.com regs.setNextNPC(val); 34410259SAndrew.Bardsley@arm.com } 34510259SAndrew.Bardsley@arm.com 34610259SAndrew.Bardsley@arm.com MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0) 34710259SAndrew.Bardsley@arm.com { 34810259SAndrew.Bardsley@arm.com return regs.readMiscRegNoEffect(misc_reg); 34910259SAndrew.Bardsley@arm.com } 35010259SAndrew.Bardsley@arm.com 35110259SAndrew.Bardsley@arm.com MiscReg readMiscReg(int misc_reg, unsigned tid = 0) 35210259SAndrew.Bardsley@arm.com { 35310259SAndrew.Bardsley@arm.com return regs.readMiscReg(misc_reg, tc); 35410259SAndrew.Bardsley@arm.com } 35510259SAndrew.Bardsley@arm.com 35610259SAndrew.Bardsley@arm.com void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0) 35710259SAndrew.Bardsley@arm.com { 35810259SAndrew.Bardsley@arm.com return regs.setMiscRegNoEffect(misc_reg, val); 35910259SAndrew.Bardsley@arm.com } 36010259SAndrew.Bardsley@arm.com 36110259SAndrew.Bardsley@arm.com void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0) 36210259SAndrew.Bardsley@arm.com { 36310259SAndrew.Bardsley@arm.com return regs.setMiscReg(misc_reg, val, tc); 36410259SAndrew.Bardsley@arm.com } 36510259SAndrew.Bardsley@arm.com 36610259SAndrew.Bardsley@arm.com unsigned readStCondFailures() { return storeCondFailures; } 36710259SAndrew.Bardsley@arm.com 36810259SAndrew.Bardsley@arm.com void setStCondFailures(unsigned sc_failures) 36910259SAndrew.Bardsley@arm.com { storeCondFailures = sc_failures; } 37010259SAndrew.Bardsley@arm.com 37110259SAndrew.Bardsley@arm.com#if !FULL_SYSTEM 37210259SAndrew.Bardsley@arm.com TheISA::IntReg getSyscallArg(int i) 37310259SAndrew.Bardsley@arm.com { 37410259SAndrew.Bardsley@arm.com assert(i < TheISA::NumArgumentRegs); 37510259SAndrew.Bardsley@arm.com return regs.readIntReg(TheISA::flattenIntIndex(getTC(), 37610259SAndrew.Bardsley@arm.com TheISA::ArgumentReg[i])); 37710259SAndrew.Bardsley@arm.com } 37810259SAndrew.Bardsley@arm.com 37910259SAndrew.Bardsley@arm.com // used to shift args for indirect syscall 38010259SAndrew.Bardsley@arm.com void setSyscallArg(int i, TheISA::IntReg val) 38110259SAndrew.Bardsley@arm.com { 38210259SAndrew.Bardsley@arm.com assert(i < TheISA::NumArgumentRegs); 38310259SAndrew.Bardsley@arm.com regs.setIntReg(TheISA::flattenIntIndex(getTC(), 38410259SAndrew.Bardsley@arm.com TheISA::ArgumentReg[i]), val); 38510259SAndrew.Bardsley@arm.com } 38610259SAndrew.Bardsley@arm.com 38710259SAndrew.Bardsley@arm.com void setSyscallReturn(SyscallReturn return_value) 38810259SAndrew.Bardsley@arm.com { 38910259SAndrew.Bardsley@arm.com TheISA::setSyscallReturn(return_value, getTC()); 39010259SAndrew.Bardsley@arm.com } 39110259SAndrew.Bardsley@arm.com 39210259SAndrew.Bardsley@arm.com void syscall(int64_t callnum) 39310259SAndrew.Bardsley@arm.com { 39410259SAndrew.Bardsley@arm.com process->syscall(callnum, tc); 39510259SAndrew.Bardsley@arm.com } 39610259SAndrew.Bardsley@arm.com#endif 39710259SAndrew.Bardsley@arm.com 39810259SAndrew.Bardsley@arm.com void changeRegFileContext(TheISA::RegContextParam param, 39910259SAndrew.Bardsley@arm.com TheISA::RegContextVal val) 40010259SAndrew.Bardsley@arm.com { 40110259SAndrew.Bardsley@arm.com regs.changeContext(param, val); 40210259SAndrew.Bardsley@arm.com } 40310259SAndrew.Bardsley@arm.com}; 40410259SAndrew.Bardsley@arm.com 40510259SAndrew.Bardsley@arm.com 40610259SAndrew.Bardsley@arm.com// for non-speculative execution context, spec_mode is always false 40710259SAndrew.Bardsley@arm.cominline bool 40810259SAndrew.Bardsley@arm.comSimpleThread::misspeculating() 40910259SAndrew.Bardsley@arm.com{ 41010259SAndrew.Bardsley@arm.com return false; 41110259SAndrew.Bardsley@arm.com} 41210259SAndrew.Bardsley@arm.com 41310259SAndrew.Bardsley@arm.com#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 41410259SAndrew.Bardsley@arm.com