simple_thread.hh revision 360
1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __EXEC_CONTEXT_HH__ 30#define __EXEC_CONTEXT_HH__ 31 32#include "sim/host.hh" 33#include "mem/mem_req.hh" 34#include "sim/serialize.hh" 35 36// forward declaration: see functional_memory.hh 37class FunctionalMemory; 38class PhysicalMemory; 39class BaseCPU; 40 41#ifdef FULL_SYSTEM 42 43#include "targetarch/alpha_memory.hh" 44class MemoryController; 45 46#include "kern/tru64/kernel_stats.hh" 47#include "sim/system.hh" 48 49#ifdef FS_MEASURE 50#include "sim/sw_context.hh" 51#endif 52 53#else // !FULL_SYSTEM 54 55#include "sim/process.hh" 56 57#endif // FULL_SYSTEM 58 59// 60// The ExecContext object represents a functional context for 61// instruction execution. It incorporates everything required for 62// architecture-level functional simulation of a single thread. 63// 64 65class ExecContext 66{ 67 public: 68 enum Status 69 { 70 /// Initialized but not running yet. All CPUs start in 71 /// this state, but most transition to Active on cycle 1. 72 /// In MP or SMT systems, non-primary contexts will stay 73 /// in this state until a thread is assigned to them. 74 Unallocated, 75 76 /// Running. Instructions should be executed only when 77 /// the context is in this state. 78 Active, 79 80 /// Temporarily inactive. Entered while waiting for 81 /// synchronization, etc. 82 Suspended, 83 84 /// Permanently shut down. Entered when target executes 85 /// m5exit pseudo-instruction. When all contexts enter 86 /// this state, the simulation will terminate. 87 Halted 88 }; 89 90 private: 91 Status _status; 92 93 public: 94 Status status() const { return _status; } 95 96 void setStatus(Status new_status); 97 98#ifdef FULL_SYSTEM 99 public: 100 KernelStats kernelStats; 101#endif 102 103 public: 104 RegFile regs; // correct-path register context 105 106 // pointer to CPU associated with this context 107 BaseCPU *cpu; 108 109 // Index of hardware thread context on the CPU that this represents. 110 int thread_num; 111 112 // ID of this context w.r.t. the System or Process object to which 113 // it belongs. For full-system mode, this is the system CPU ID. 114 int cpu_id; 115 116#ifdef FULL_SYSTEM 117 118 FunctionalMemory *mem; 119 AlphaItb *itb; 120 AlphaDtb *dtb; 121 System *system; 122 123 // the following two fields are redundant, since we can always 124 // look them up through the system pointer, but we'll leave them 125 // here for now for convenience 126 MemoryController *memCtrl; 127 PhysicalMemory *physmem; 128 129#ifdef FS_MEASURE 130 SWContext *swCtx; 131#endif 132 133#else 134 Process *process; 135 136 FunctionalMemory *mem; // functional storage for process address space 137 138 // Address space ID. Note that this is used for TIMING cache 139 // simulation only; all functional memory accesses should use 140 // one of the FunctionalMemory pointers above. 141 short asid; 142 143#endif 144 145 146 /* 147 * number of executed instructions, for matching with syscall trace 148 * points in EIO files. 149 */ 150 Counter func_exe_insn; 151 152 // 153 // Count failed store conditionals so we can warn of apparent 154 // application deadlock situations. 155 unsigned storeCondFailures; 156 157 // constructor: initialize context from given process structure 158#ifdef FULL_SYSTEM 159 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 160 AlphaItb *_itb, AlphaDtb *_dtb, FunctionalMemory *_dem); 161#else 162 ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); 163 ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem, 164 int _asid); 165#endif 166 virtual ~ExecContext() {} 167 168 virtual void takeOverFrom(ExecContext *oldContext); 169 170 void regStats(const std::string &name); 171 172 void serialize(std::ostream &os); 173 void unserialize(Checkpoint *cp, const std::string §ion); 174 175#ifdef FULL_SYSTEM 176 bool validInstAddr(Addr addr) { return true; } 177 bool validDataAddr(Addr addr) { return true; } 178 int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); } 179 int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); } 180 181 Fault translateInstReq(MemReqPtr req) 182 { 183 return itb->translate(req); 184 } 185 186 Fault translateDataReadReq(MemReqPtr req) 187 { 188 return dtb->translate(req, false); 189 } 190 191 Fault translateDataWriteReq(MemReqPtr req) 192 { 193 return dtb->translate(req, true); 194 } 195 196#else 197 bool validInstAddr(Addr addr) 198 { return process->validInstAddr(addr); } 199 200 bool validDataAddr(Addr addr) 201 { return process->validDataAddr(addr); } 202 203 int getInstAsid() { return asid; } 204 int getDataAsid() { return asid; } 205 206 Fault dummyTranslation(MemReqPtr req) 207 { 208#if 0 209 assert((req->vaddr >> 48 & 0xffff) == 0); 210#endif 211 212 // put the asid in the upper 16 bits of the paddr 213 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); 214 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; 215 return No_Fault; 216 } 217 Fault translateInstReq(MemReqPtr req) 218 { 219 return dummyTranslation(req); 220 } 221 Fault translateDataReadReq(MemReqPtr req) 222 { 223 return dummyTranslation(req); 224 } 225 Fault translateDataWriteReq(MemReqPtr req) 226 { 227 return dummyTranslation(req); 228 } 229 230#endif 231 232 template <class T> 233 Fault read(MemReqPtr req, T& data) 234 { 235#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) 236 if (req->flags & LOCKED) { 237 MiscRegFile *cregs = &req->xc->regs.miscRegs; 238 cregs->lock_addr = req->paddr; 239 cregs->lock_flag = true; 240 } 241#endif 242 return mem->read(req, data); 243 } 244 245 template <class T> 246 Fault write(MemReqPtr req, T& data) 247 { 248#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) 249 250 MiscRegFile *cregs; 251 252 // If this is a store conditional, act appropriately 253 if (req->flags & LOCKED) { 254 cregs = &req->xc->regs.miscRegs; 255 256 if (req->flags & UNCACHEABLE) { 257 // Don't update result register (see stq_c in isa_desc) 258 req->result = 2; 259 req->xc->storeCondFailures = 0;//Needed? [RGD] 260 } else { 261 req->result = cregs->lock_flag; 262 if (!cregs->lock_flag || 263 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { 264 cregs->lock_flag = false; 265 if (((++req->xc->storeCondFailures) % 100000) == 0) { 266 std::cerr << "Warning: " 267 << req->xc->storeCondFailures 268 << " consecutive store conditional failures " 269 << "on cpu " << req->xc->cpu_id 270 << std::endl; 271 } 272 return No_Fault; 273 } 274 else req->xc->storeCondFailures = 0; 275 } 276 } 277 278 // Need to clear any locked flags on other proccessors for 279 // this address. Only do this for succsful Store Conditionals 280 // and all other stores (WH64?). Unsuccessful Store 281 // Conditionals would have returned above, and wouldn't fall 282 // through. 283 for (int i = 0; i < system->execContexts.size(); i++){ 284 cregs = &system->execContexts[i]->regs.miscRegs; 285 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { 286 cregs->lock_flag = false; 287 } 288 } 289 290#endif 291 return mem->write(req, data); 292 } 293 294 virtual bool misspeculating(); 295 296 297 // 298 // New accessors for new decoder. 299 // 300 uint64_t readIntReg(int reg_idx) 301 { 302 return regs.intRegFile[reg_idx]; 303 } 304 305 float readFloatRegSingle(int reg_idx) 306 { 307 return (float)regs.floatRegFile.d[reg_idx]; 308 } 309 310 double readFloatRegDouble(int reg_idx) 311 { 312 return regs.floatRegFile.d[reg_idx]; 313 } 314 315 uint64_t readFloatRegInt(int reg_idx) 316 { 317 return regs.floatRegFile.q[reg_idx]; 318 } 319 320 void setIntReg(int reg_idx, uint64_t val) 321 { 322 regs.intRegFile[reg_idx] = val; 323 } 324 325 void setFloatRegSingle(int reg_idx, float val) 326 { 327 regs.floatRegFile.d[reg_idx] = (double)val; 328 } 329 330 void setFloatRegDouble(int reg_idx, double val) 331 { 332 regs.floatRegFile.d[reg_idx] = val; 333 } 334 335 void setFloatRegInt(int reg_idx, uint64_t val) 336 { 337 regs.floatRegFile.q[reg_idx] = val; 338 } 339 340 uint64_t readPC() 341 { 342 return regs.pc; 343 } 344 345 void setNextPC(uint64_t val) 346 { 347 regs.npc = val; 348 } 349 350 uint64_t readUniq() 351 { 352 return regs.miscRegs.uniq; 353 } 354 355 void setUniq(uint64_t val) 356 { 357 regs.miscRegs.uniq = val; 358 } 359 360 uint64_t readFpcr() 361 { 362 return regs.miscRegs.fpcr; 363 } 364 365 void setFpcr(uint64_t val) 366 { 367 regs.miscRegs.fpcr = val; 368 } 369 370#ifdef FULL_SYSTEM 371 uint64_t readIpr(int idx, Fault &fault); 372 Fault setIpr(int idx, uint64_t val); 373 Fault hwrei(); 374 void ev5_trap(Fault fault); 375 bool simPalCheck(int palFunc); 376#endif 377 378#ifndef FULL_SYSTEM 379 IntReg getSyscallArg(int i) 380 { 381 return regs.intRegFile[ArgumentReg0 + i]; 382 } 383 384 // used to shift args for indirect syscall 385 void setSyscallArg(int i, IntReg val) 386 { 387 regs.intRegFile[ArgumentReg0 + i] = val; 388 } 389 390 void setSyscallReturn(int64_t return_value) 391 { 392 // check for error condition. Alpha syscall convention is to 393 // indicate success/failure in reg a3 (r19) and put the 394 // return value itself in the standard return value reg (v0). 395 const int RegA3 = 19; // only place this is used 396 if (return_value >= 0) { 397 // no error 398 regs.intRegFile[RegA3] = 0; 399 regs.intRegFile[ReturnValueReg] = return_value; 400 } else { 401 // got an error, return details 402 regs.intRegFile[RegA3] = (IntReg) -1; 403 regs.intRegFile[ReturnValueReg] = -return_value; 404 } 405 } 406 407 void syscall() 408 { 409 process->syscall(this); 410 } 411#endif 412}; 413 414 415// for non-speculative execution context, spec_mode is always false 416inline bool 417ExecContext::misspeculating() 418{ 419 return false; 420} 421 422#endif // __EXEC_CONTEXT_HH__ 423