simple_thread.hh revision 2972:f84c6c5309ce
110152Satgutier@umich.edu/* 210152Satgutier@umich.edu * Copyright (c) 2001-2006 The Regents of The University of Michigan 310152Satgutier@umich.edu * All rights reserved. 410152Satgutier@umich.edu * 510152Satgutier@umich.edu * Redistribution and use in source and binary forms, with or without 610152Satgutier@umich.edu * modification, are permitted provided that the following conditions are 710152Satgutier@umich.edu * met: redistributions of source code must retain the above copyright 810152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer; 910152Satgutier@umich.edu * redistributions in binary form must reproduce the above copyright 1010152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer in the 1110152Satgutier@umich.edu * documentation and/or other materials provided with the distribution; 1210152Satgutier@umich.edu * neither the name of the copyright holders nor the names of its 1310152Satgutier@umich.edu * contributors may be used to endorse or promote products derived from 1410152Satgutier@umich.edu * this software without specific prior written permission. 1510152Satgutier@umich.edu * 1610152Satgutier@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710152Satgutier@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810152Satgutier@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910152Satgutier@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010152Satgutier@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110152Satgutier@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210152Satgutier@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310152Satgutier@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410152Satgutier@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510152Satgutier@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610152Satgutier@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710152Satgutier@umich.edu * 2810152Satgutier@umich.edu * Authors: Steve Reinhardt 2910152Satgutier@umich.edu * Nathan Binkert 3010152Satgutier@umich.edu */ 3110152Satgutier@umich.edu 3210152Satgutier@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 3310152Satgutier@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 3410152Satgutier@umich.edu 3510152Satgutier@umich.edu#include "arch/isa_traits.hh" 3610152Satgutier@umich.edu#include "config/full_system.hh" 3710152Satgutier@umich.edu#include "cpu/thread_context.hh" 3810152Satgutier@umich.edu#include "cpu/thread_state.hh" 3910152Satgutier@umich.edu#include "mem/physical.hh" 4010152Satgutier@umich.edu#include "mem/request.hh" 4110152Satgutier@umich.edu#include "sim/byteswap.hh" 4210152Satgutier@umich.edu#include "sim/eventq.hh" 4310152Satgutier@umich.edu#include "sim/host.hh" 4410152Satgutier@umich.edu#include "sim/serialize.hh" 4510152Satgutier@umich.edu 4610152Satgutier@umich.educlass BaseCPU; 4710152Satgutier@umich.edu 4810152Satgutier@umich.edu#if FULL_SYSTEM 4910152Satgutier@umich.edu 5010152Satgutier@umich.edu#include "sim/system.hh" 5110152Satgutier@umich.edu#include "arch/tlb.hh" 5210152Satgutier@umich.edu 5310152Satgutier@umich.educlass FunctionProfile; 5410152Satgutier@umich.educlass ProfileNode; 5510152Satgutier@umich.educlass FunctionalPort; 5610152Satgutier@umich.educlass PhysicalPort; 5710152Satgutier@umich.edu 5810152Satgutier@umich.edunamespace Kernel { 5910152Satgutier@umich.edu class Statistics; 6010152Satgutier@umich.edu}; 6110152Satgutier@umich.edu 6210152Satgutier@umich.edu#else // !FULL_SYSTEM 6310152Satgutier@umich.edu 6410152Satgutier@umich.edu#include "sim/process.hh" 6510152Satgutier@umich.edu#include "mem/page_table.hh" 6610152Satgutier@umich.educlass TranslatingPort; 6710152Satgutier@umich.edu 6810152Satgutier@umich.edu#endif // FULL_SYSTEM 6910152Satgutier@umich.edu 7010152Satgutier@umich.edu/** 7110152Satgutier@umich.edu * The SimpleThread object provides a combination of the ThreadState 7210152Satgutier@umich.edu * object and the ThreadContext interface. It implements the 7310152Satgutier@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 7410152Satgutier@umich.edu * made using SimpleThread as the template parameter (see 7510152Satgutier@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 7610152Satgutier@umich.edu * the objects needed for simple functional execution, including a 7710152Satgutier@umich.edu * simple architectural register file, and pointers to the ITB and DTB 7810152Satgutier@umich.edu * in full system mode. For CPU models that do not need more advanced 7910152Satgutier@umich.edu * ways to hold state (i.e. a separate physical register file, or 8010152Satgutier@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 8110152Satgutier@umich.edu * all the necessary state for full architecture-level functional 8210152Satgutier@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 8310152Satgutier@umich.edu * examples. 8410152Satgutier@umich.edu */ 8510152Satgutier@umich.edu 8610152Satgutier@umich.educlass SimpleThread : public ThreadState 8710152Satgutier@umich.edu{ 8810152Satgutier@umich.edu protected: 8910152Satgutier@umich.edu typedef TheISA::RegFile RegFile; 9010152Satgutier@umich.edu typedef TheISA::MachInst MachInst; 9110152Satgutier@umich.edu typedef TheISA::MiscRegFile MiscRegFile; 9210152Satgutier@umich.edu typedef TheISA::MiscReg MiscReg; 9310152Satgutier@umich.edu typedef TheISA::FloatReg FloatReg; 9410152Satgutier@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 9510152Satgutier@umich.edu public: 9610152Satgutier@umich.edu typedef ThreadContext::Status Status; 9710152Satgutier@umich.edu 9810152Satgutier@umich.edu protected: 9910152Satgutier@umich.edu RegFile regs; // correct-path register context 10010152Satgutier@umich.edu 10110152Satgutier@umich.edu public: 10210152Satgutier@umich.edu // pointer to CPU associated with this SimpleThread 10310152Satgutier@umich.edu BaseCPU *cpu; 10410152Satgutier@umich.edu 10510152Satgutier@umich.edu ProxyThreadContext<SimpleThread> *tc; 10610152Satgutier@umich.edu 10710152Satgutier@umich.edu System *system; 10810152Satgutier@umich.edu 10910152Satgutier@umich.edu#if FULL_SYSTEM 11010152Satgutier@umich.edu AlphaITB *itb; 11110152Satgutier@umich.edu AlphaDTB *dtb; 11210152Satgutier@umich.edu#endif 11310152Satgutier@umich.edu 11410152Satgutier@umich.edu // constructor: initialize SimpleThread from given process structure 11510152Satgutier@umich.edu#if FULL_SYSTEM 11610152Satgutier@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 11710152Satgutier@umich.edu AlphaITB *_itb, AlphaDTB *_dtb, 11810152Satgutier@umich.edu bool use_kernel_stats = true); 11910152Satgutier@umich.edu#else 12010152Satgutier@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid, 12110152Satgutier@umich.edu MemObject *memobj); 12210152Satgutier@umich.edu#endif 12310152Satgutier@umich.edu 12410152Satgutier@umich.edu SimpleThread(); 12510152Satgutier@umich.edu 12610152Satgutier@umich.edu virtual ~SimpleThread(); 12710152Satgutier@umich.edu 12810152Satgutier@umich.edu virtual void takeOverFrom(ThreadContext *oldContext); 12910152Satgutier@umich.edu 13010152Satgutier@umich.edu void regStats(const std::string &name); 13110152Satgutier@umich.edu 13210152Satgutier@umich.edu void copyTC(ThreadContext *context); 13310152Satgutier@umich.edu 13410152Satgutier@umich.edu void copyState(ThreadContext *oldContext); 13510152Satgutier@umich.edu 13610152Satgutier@umich.edu void serialize(std::ostream &os); 13710152Satgutier@umich.edu void unserialize(Checkpoint *cp, const std::string §ion); 13810152Satgutier@umich.edu 13910152Satgutier@umich.edu /*************************************************************** 14010152Satgutier@umich.edu * SimpleThread functions to provide CPU with access to various 14110152Satgutier@umich.edu * state, and to provide address translation methods. 14210152Satgutier@umich.edu **************************************************************/ 14310152Satgutier@umich.edu 14410152Satgutier@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 14510152Satgutier@umich.edu * when a ThreadContext must be passed to objects outside of the 14610152Satgutier@umich.edu * CPU. 14710152Satgutier@umich.edu */ 14810152Satgutier@umich.edu ThreadContext *getTC() { return tc; } 14910152Satgutier@umich.edu 15010152Satgutier@umich.edu#if FULL_SYSTEM 15110152Satgutier@umich.edu int getInstAsid() { return regs.instAsid(); } 15210152Satgutier@umich.edu int getDataAsid() { return regs.dataAsid(); } 15310152Satgutier@umich.edu 15410152Satgutier@umich.edu Fault translateInstReq(RequestPtr &req) 15510152Satgutier@umich.edu { 15610152Satgutier@umich.edu return itb->translate(req, tc); 15710152Satgutier@umich.edu } 15810152Satgutier@umich.edu 15910152Satgutier@umich.edu Fault translateDataReadReq(RequestPtr &req) 16010152Satgutier@umich.edu { 16110152Satgutier@umich.edu return dtb->translate(req, tc, false); 16210152Satgutier@umich.edu } 16310152Satgutier@umich.edu 16410152Satgutier@umich.edu Fault translateDataWriteReq(RequestPtr &req) 16510152Satgutier@umich.edu { 16610152Satgutier@umich.edu return dtb->translate(req, tc, true); 16710152Satgutier@umich.edu } 16810152Satgutier@umich.edu 16910152Satgutier@umich.edu void dumpFuncProfile(); 17010152Satgutier@umich.edu 17110152Satgutier@umich.edu int readIntrFlag() { return regs.intrflag; } 17210152Satgutier@umich.edu void setIntrFlag(int val) { regs.intrflag = val; } 17310152Satgutier@umich.edu Fault hwrei(); 17410152Satgutier@umich.edu 17510152Satgutier@umich.edu bool simPalCheck(int palFunc); 17610152Satgutier@umich.edu#else 17710152Satgutier@umich.edu Fault translateInstReq(RequestPtr &req) 17810152Satgutier@umich.edu { 17910152Satgutier@umich.edu return process->pTable->translate(req); 18010152Satgutier@umich.edu } 18110152Satgutier@umich.edu 18210152Satgutier@umich.edu Fault translateDataReadReq(RequestPtr &req) 18310152Satgutier@umich.edu { 18410152Satgutier@umich.edu return process->pTable->translate(req); 18510152Satgutier@umich.edu } 18610152Satgutier@umich.edu 18710152Satgutier@umich.edu Fault translateDataWriteReq(RequestPtr &req) 18810152Satgutier@umich.edu { 18910152Satgutier@umich.edu return process->pTable->translate(req); 19010152Satgutier@umich.edu } 19110152Satgutier@umich.edu#endif 19210152Satgutier@umich.edu 19310152Satgutier@umich.edu /******************************************* 19410152Satgutier@umich.edu * ThreadContext interface functions. 19510152Satgutier@umich.edu ******************************************/ 19610152Satgutier@umich.edu 19710152Satgutier@umich.edu BaseCPU *getCpuPtr() { return cpu; } 19810152Satgutier@umich.edu 19910152Satgutier@umich.edu int getThreadNum() { return tid; } 20010152Satgutier@umich.edu 20110152Satgutier@umich.edu#if FULL_SYSTEM 20210152Satgutier@umich.edu System *getSystemPtr() { return system; } 20310152Satgutier@umich.edu 20410152Satgutier@umich.edu AlphaITB *getITBPtr() { return itb; } 20510152Satgutier@umich.edu 20610152Satgutier@umich.edu AlphaDTB *getDTBPtr() { return dtb; } 20710152Satgutier@umich.edu 20810152Satgutier@umich.edu FunctionalPort *getPhysPort() { return physPort; } 20910152Satgutier@umich.edu 21010152Satgutier@umich.edu /** Return a virtual port. If no thread context is specified then a static 21110152Satgutier@umich.edu * port is returned. Otherwise a port is created and returned. It must be 21210152Satgutier@umich.edu * deleted by deleteVirtPort(). */ 21310152Satgutier@umich.edu VirtualPort *getVirtPort(ThreadContext *tc); 21410152Satgutier@umich.edu 21510152Satgutier@umich.edu void delVirtPort(VirtualPort *vp); 21610152Satgutier@umich.edu#endif 21710152Satgutier@umich.edu 21810152Satgutier@umich.edu Status status() const { return _status; } 21910152Satgutier@umich.edu 22010152Satgutier@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 22110152Satgutier@umich.edu 22210152Satgutier@umich.edu /// Set the status to Active. Optional delay indicates number of 22310152Satgutier@umich.edu /// cycles to wait before beginning execution. 22410152Satgutier@umich.edu void activate(int delay = 1); 22510152Satgutier@umich.edu 22610152Satgutier@umich.edu /// Set the status to Suspended. 22710152Satgutier@umich.edu void suspend(); 22810152Satgutier@umich.edu 22910152Satgutier@umich.edu /// Set the status to Unallocated. 23010152Satgutier@umich.edu void deallocate(); 23110152Satgutier@umich.edu 23210152Satgutier@umich.edu /// Set the status to Halted. 23310152Satgutier@umich.edu void halt(); 23410152Satgutier@umich.edu 23510152Satgutier@umich.edu/* 23610152Satgutier@umich.edu template <class T> 23710152Satgutier@umich.edu Fault read(RequestPtr &req, T &data) 23810152Satgutier@umich.edu { 23910152Satgutier@umich.edu#if FULL_SYSTEM && THE_ISA == ALPHA_ISA 24010152Satgutier@umich.edu if (req->flags & LOCKED) { 24110152Satgutier@umich.edu req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr); 24210152Satgutier@umich.edu req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true); 24310152Satgutier@umich.edu } 24410152Satgutier@umich.edu#endif 24510152Satgutier@umich.edu 24610152Satgutier@umich.edu Fault error; 24710152Satgutier@umich.edu error = mem->prot_read(req->paddr, data, req->size); 24810152Satgutier@umich.edu data = LittleEndianGuest::gtoh(data); 24910152Satgutier@umich.edu return error; 25010152Satgutier@umich.edu } 25110152Satgutier@umich.edu 25210152Satgutier@umich.edu template <class T> 25310152Satgutier@umich.edu Fault write(RequestPtr &req, T &data) 25410152Satgutier@umich.edu { 25510152Satgutier@umich.edu#if FULL_SYSTEM && THE_ISA == ALPHA_ISA 25610152Satgutier@umich.edu ExecContext *xc; 25710152Satgutier@umich.edu 25810152Satgutier@umich.edu // If this is a store conditional, act appropriately 25910152Satgutier@umich.edu if (req->flags & LOCKED) { 26010152Satgutier@umich.edu xc = req->xc; 26110152Satgutier@umich.edu 26210152Satgutier@umich.edu if (req->flags & UNCACHEABLE) { 26310152Satgutier@umich.edu // Don't update result register (see stq_c in isa_desc) 26410152Satgutier@umich.edu req->result = 2; 26510152Satgutier@umich.edu xc->setStCondFailures(0);//Needed? [RGD] 26610152Satgutier@umich.edu } else { 26710152Satgutier@umich.edu bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag); 26810152Satgutier@umich.edu Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag); 26910152Satgutier@umich.edu req->result = lock_flag; 27010152Satgutier@umich.edu if (!lock_flag || 27110152Satgutier@umich.edu ((lock_addr & ~0xf) != (req->paddr & ~0xf))) { 27210152Satgutier@umich.edu xc->setMiscReg(TheISA::Lock_Flag_DepTag, false); 27310152Satgutier@umich.edu xc->setStCondFailures(xc->readStCondFailures() + 1); 27410152Satgutier@umich.edu if (((xc->readStCondFailures()) % 100000) == 0) { 27510152Satgutier@umich.edu std::cerr << "Warning: " 27610152Satgutier@umich.edu << xc->readStCondFailures() 27710152Satgutier@umich.edu << " consecutive store conditional failures " 27810152Satgutier@umich.edu << "on cpu " << req->xc->readCpuId() 27910152Satgutier@umich.edu << std::endl; 28010152Satgutier@umich.edu } 28110152Satgutier@umich.edu return NoFault; 28210152Satgutier@umich.edu } 28310152Satgutier@umich.edu else xc->setStCondFailures(0); 28410152Satgutier@umich.edu } 28510152Satgutier@umich.edu } 28610152Satgutier@umich.edu 28710152Satgutier@umich.edu // Need to clear any locked flags on other proccessors for 28810152Satgutier@umich.edu // this address. Only do this for succsful Store Conditionals 28910152Satgutier@umich.edu // and all other stores (WH64?). Unsuccessful Store 29010152Satgutier@umich.edu // Conditionals would have returned above, and wouldn't fall 29110152Satgutier@umich.edu // through. 29210152Satgutier@umich.edu for (int i = 0; i < system->execContexts.size(); i++){ 29310152Satgutier@umich.edu xc = system->execContexts[i]; 29410152Satgutier@umich.edu if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) == 29510152Satgutier@umich.edu (req->paddr & ~0xf)) { 29610152Satgutier@umich.edu xc->setMiscReg(TheISA::Lock_Flag_DepTag, false); 29710152Satgutier@umich.edu } 29810152Satgutier@umich.edu } 29910152Satgutier@umich.edu 30010152Satgutier@umich.edu#endif 30110152Satgutier@umich.edu return mem->prot_write(req->paddr, (T)htog(data), req->size); 30210152Satgutier@umich.edu } 30310152Satgutier@umich.edu*/ 30410152Satgutier@umich.edu virtual bool misspeculating(); 30510152Satgutier@umich.edu 30610152Satgutier@umich.edu Fault instRead(RequestPtr &req) 30710152Satgutier@umich.edu { 30810152Satgutier@umich.edu panic("instRead not implemented"); 30910152Satgutier@umich.edu // return funcPhysMem->read(req, inst); 31010152Satgutier@umich.edu return NoFault; 31110152Satgutier@umich.edu } 31210152Satgutier@umich.edu 31310152Satgutier@umich.edu void copyArchRegs(ThreadContext *tc); 31410152Satgutier@umich.edu 31510152Satgutier@umich.edu void clearArchRegs() { regs.clear(); } 31610152Satgutier@umich.edu 31710152Satgutier@umich.edu // 31810152Satgutier@umich.edu // New accessors for new decoder. 31910152Satgutier@umich.edu // 32010152Satgutier@umich.edu uint64_t readIntReg(int reg_idx) 32110152Satgutier@umich.edu { 32210152Satgutier@umich.edu return regs.readIntReg(reg_idx); 32310152Satgutier@umich.edu } 32410152Satgutier@umich.edu 32510152Satgutier@umich.edu FloatReg readFloatReg(int reg_idx, int width) 32610152Satgutier@umich.edu { 32710152Satgutier@umich.edu return regs.readFloatReg(reg_idx, width); 32810152Satgutier@umich.edu } 32910152Satgutier@umich.edu 33010152Satgutier@umich.edu FloatReg readFloatReg(int reg_idx) 33110152Satgutier@umich.edu { 33210152Satgutier@umich.edu return regs.readFloatReg(reg_idx); 33310152Satgutier@umich.edu } 33410152Satgutier@umich.edu 33510152Satgutier@umich.edu FloatRegBits readFloatRegBits(int reg_idx, int width) 33610152Satgutier@umich.edu { 33710152Satgutier@umich.edu return regs.readFloatRegBits(reg_idx, width); 33810152Satgutier@umich.edu } 33910152Satgutier@umich.edu 34010152Satgutier@umich.edu FloatRegBits readFloatRegBits(int reg_idx) 34110152Satgutier@umich.edu { 34210152Satgutier@umich.edu return regs.readFloatRegBits(reg_idx); 34310152Satgutier@umich.edu } 34410152Satgutier@umich.edu 34510152Satgutier@umich.edu void setIntReg(int reg_idx, uint64_t val) 34610152Satgutier@umich.edu { 34710152Satgutier@umich.edu regs.setIntReg(reg_idx, val); 34810152Satgutier@umich.edu } 34910152Satgutier@umich.edu 35010152Satgutier@umich.edu void setFloatReg(int reg_idx, FloatReg val, int width) 35110152Satgutier@umich.edu { 35210152Satgutier@umich.edu regs.setFloatReg(reg_idx, val, width); 35310152Satgutier@umich.edu } 35410152Satgutier@umich.edu 35510152Satgutier@umich.edu void setFloatReg(int reg_idx, FloatReg val) 35610152Satgutier@umich.edu { 35710152Satgutier@umich.edu regs.setFloatReg(reg_idx, val); 35810152Satgutier@umich.edu } 35910152Satgutier@umich.edu 36010152Satgutier@umich.edu void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 36110152Satgutier@umich.edu { 36210152Satgutier@umich.edu regs.setFloatRegBits(reg_idx, val, width); 36310152Satgutier@umich.edu } 36410152Satgutier@umich.edu 36510152Satgutier@umich.edu void setFloatRegBits(int reg_idx, FloatRegBits val) 36610152Satgutier@umich.edu { 36710152Satgutier@umich.edu regs.setFloatRegBits(reg_idx, val); 36810152Satgutier@umich.edu } 36910152Satgutier@umich.edu 37010152Satgutier@umich.edu uint64_t readPC() 37110152Satgutier@umich.edu { 37210152Satgutier@umich.edu return regs.readPC(); 37310152Satgutier@umich.edu } 37410152Satgutier@umich.edu 37510152Satgutier@umich.edu void setPC(uint64_t val) 37610152Satgutier@umich.edu { 37710152Satgutier@umich.edu regs.setPC(val); 37810152Satgutier@umich.edu } 37910152Satgutier@umich.edu 38010152Satgutier@umich.edu uint64_t readNextPC() 38110152Satgutier@umich.edu { 38210152Satgutier@umich.edu return regs.readNextPC(); 38310152Satgutier@umich.edu } 38410152Satgutier@umich.edu 38510152Satgutier@umich.edu void setNextPC(uint64_t val) 38610152Satgutier@umich.edu { 38710152Satgutier@umich.edu regs.setNextPC(val); 38810152Satgutier@umich.edu } 38910152Satgutier@umich.edu 39010152Satgutier@umich.edu uint64_t readNextNPC() 39110152Satgutier@umich.edu { 39210152Satgutier@umich.edu return regs.readNextNPC(); 39310152Satgutier@umich.edu } 39410152Satgutier@umich.edu 39510152Satgutier@umich.edu void setNextNPC(uint64_t val) 39610152Satgutier@umich.edu { 39710152Satgutier@umich.edu regs.setNextNPC(val); 39810152Satgutier@umich.edu } 39910152Satgutier@umich.edu 40010152Satgutier@umich.edu MiscReg readMiscReg(int misc_reg) 40110152Satgutier@umich.edu { 40210152Satgutier@umich.edu return regs.readMiscReg(misc_reg); 40310152Satgutier@umich.edu } 40410152Satgutier@umich.edu 40510152Satgutier@umich.edu MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 40610152Satgutier@umich.edu { 40710152Satgutier@umich.edu return regs.readMiscRegWithEffect(misc_reg, fault, tc); 40810152Satgutier@umich.edu } 40910152Satgutier@umich.edu 41010152Satgutier@umich.edu Fault setMiscReg(int misc_reg, const MiscReg &val) 41110152Satgutier@umich.edu { 41210152Satgutier@umich.edu return regs.setMiscReg(misc_reg, val); 41310152Satgutier@umich.edu } 41410152Satgutier@umich.edu 41510152Satgutier@umich.edu Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 41610152Satgutier@umich.edu { 41710152Satgutier@umich.edu return regs.setMiscRegWithEffect(misc_reg, val, tc); 41810152Satgutier@umich.edu } 41910152Satgutier@umich.edu 42010152Satgutier@umich.edu unsigned readStCondFailures() { return storeCondFailures; } 42110152Satgutier@umich.edu 42210152Satgutier@umich.edu void setStCondFailures(unsigned sc_failures) 42310152Satgutier@umich.edu { storeCondFailures = sc_failures; } 42410152Satgutier@umich.edu 42510152Satgutier@umich.edu#if FULL_SYSTEM 42610152Satgutier@umich.edu bool inPalMode() { return AlphaISA::PcPAL(regs.readPC()); } 42710152Satgutier@umich.edu#endif 42810152Satgutier@umich.edu 42910152Satgutier@umich.edu#if !FULL_SYSTEM 43010152Satgutier@umich.edu TheISA::IntReg getSyscallArg(int i) 43110152Satgutier@umich.edu { 43210152Satgutier@umich.edu return regs.readIntReg(TheISA::ArgumentReg0 + i); 43310152Satgutier@umich.edu } 43410152Satgutier@umich.edu 43510152Satgutier@umich.edu // used to shift args for indirect syscall 43610152Satgutier@umich.edu void setSyscallArg(int i, TheISA::IntReg val) 43710152Satgutier@umich.edu { 43810152Satgutier@umich.edu regs.setIntReg(TheISA::ArgumentReg0 + i, val); 43910152Satgutier@umich.edu } 44010152Satgutier@umich.edu 44110152Satgutier@umich.edu void setSyscallReturn(SyscallReturn return_value) 44210152Satgutier@umich.edu { 44310152Satgutier@umich.edu TheISA::setSyscallReturn(return_value, ®s); 44410152Satgutier@umich.edu } 44510152Satgutier@umich.edu 44610152Satgutier@umich.edu void syscall(int64_t callnum) 44710152Satgutier@umich.edu { 44810152Satgutier@umich.edu process->syscall(callnum, tc); 44910152Satgutier@umich.edu } 45010152Satgutier@umich.edu#endif 45110152Satgutier@umich.edu 45210152Satgutier@umich.edu void changeRegFileContext(TheISA::RegContextParam param, 45310152Satgutier@umich.edu TheISA::RegContextVal val) 45410152Satgutier@umich.edu { 45510152Satgutier@umich.edu regs.changeContext(param, val); 456 } 457}; 458 459 460// for non-speculative execution context, spec_mode is always false 461inline bool 462SimpleThread::misspeculating() 463{ 464 return false; 465} 466 467#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 468