simple_thread.hh revision 2400
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_EXEC_CONTEXT_HH__ 30#define __CPU_EXEC_CONTEXT_HH__ 31 32#include "config/full_system.hh" 33#include "mem/physical.hh" 34#include "mem/request.hh" 35#include "sim/host.hh" 36#include "sim/serialize.hh" 37#include "targetarch/byte_swap.hh" 38#include "mem/translating_port.hh" 39 40class BaseCPU; 41 42#if FULL_SYSTEM 43 44#include "sim/system.hh" 45#include "targetarch/alpha_memory.hh" 46 47class FunctionProfile; 48class ProfileNode; 49class MemoryController; 50namespace Kernel { class Binning; class Statistics; } 51 52#else // !FULL_SYSTEM 53 54#include "sim/process.hh" 55 56#endif // FULL_SYSTEM 57 58// 59// The ExecContext object represents a functional context for 60// instruction execution. It incorporates everything required for 61// architecture-level functional simulation of a single thread. 62// 63 64class ExecContext 65{ 66 public: 67 enum Status 68 { 69 /// Initialized but not running yet. All CPUs start in 70 /// this state, but most transition to Active on cycle 1. 71 /// In MP or SMT systems, non-primary contexts will stay 72 /// in this state until a thread is assigned to them. 73 Unallocated, 74 75 /// Running. Instructions should be executed only when 76 /// the context is in this state. 77 Active, 78 79 /// Temporarily inactive. Entered while waiting for 80 /// synchronization, etc. 81 Suspended, 82 83 /// Permanently shut down. Entered when target executes 84 /// m5exit pseudo-instruction. When all contexts enter 85 /// this state, the simulation will terminate. 86 Halted 87 }; 88 89 private: 90 Status _status; 91 92 public: 93 Status status() const { return _status; } 94 95 /// Set the status to Active. Optional delay indicates number of 96 /// cycles to wait before beginning execution. 97 void activate(int delay = 1); 98 99 /// Set the status to Suspended. 100 void suspend(); 101 102 /// Set the status to Unallocated. 103 void deallocate(); 104 105 /// Set the status to Halted. 106 void halt(); 107 108 public: 109 RegFile regs; // correct-path register context 110 111 // pointer to CPU associated with this context 112 BaseCPU *cpu; 113 114 // Current instruction 115 MachInst inst; 116 117 // Index of hardware thread context on the CPU that this represents. 118 int thread_num; 119 120 // ID of this context w.r.t. the System or Process object to which 121 // it belongs. For full-system mode, this is the system CPU ID. 122 int cpu_id; 123 124 System *system; 125 126 /// Port that syscalls can use to access memory (provides translation step). 127 TranslatingPort *port; 128// Memory *mem; 129 130#if FULL_SYSTEM 131 AlphaITB *itb; 132 AlphaDTB *dtb; 133 134 // the following two fields are redundant, since we can always 135 // look them up through the system pointer, but we'll leave them 136 // here for now for convenience 137 MemoryController *memctrl; 138// PhysicalMemory *physmem; 139 140 Kernel::Binning *kernelBinning; 141 Kernel::Statistics *kernelStats; 142 bool bin; 143 bool fnbin; 144 145 FunctionProfile *profile; 146 ProfileNode *profileNode; 147 Addr profilePC; 148 void dumpFuncProfile(); 149 150#else 151 Process *process; 152 153 // Address space ID. Note that this is used for TIMING cache 154 // simulation only; all functional memory accesses should use 155 // one of the FunctionalMemory pointers above. 156 short asid; 157 158#endif 159 160 /** 161 * Temporary storage to pass the source address from copy_load to 162 * copy_store. 163 * @todo Remove this temporary when we have a better way to do it. 164 */ 165 Addr copySrcAddr; 166 /** 167 * Temp storage for the physical source address of a copy. 168 * @todo Remove this temporary when we have a better way to do it. 169 */ 170 Addr copySrcPhysAddr; 171 172 173 /* 174 * number of executed instructions, for matching with syscall trace 175 * points in EIO files. 176 */ 177 Counter func_exe_inst; 178 179 // 180 // Count failed store conditionals so we can warn of apparent 181 // application deadlock situations. 182 unsigned storeCondFailures; 183 184 // constructor: initialize context from given process structure 185#if FULL_SYSTEM 186 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 187 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); 188#else 189 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 190 Memory *_mem, Process *_process, int _asid); 191#endif 192 virtual ~ExecContext(); 193 194 virtual void takeOverFrom(ExecContext *oldContext); 195 196 void regStats(const std::string &name); 197 198 void serialize(std::ostream &os); 199 void unserialize(Checkpoint *cp, const std::string §ion); 200 201#if FULL_SYSTEM 202 bool validInstAddr(Addr addr) { return true; } 203 bool validDataAddr(Addr addr) { return true; } 204 int getInstAsid() { return regs.instAsid(); } 205 int getDataAsid() { return regs.dataAsid(); } 206 207 Fault translateInstReq(CpuRequestPtr &req) 208 { 209 return itb->translate(req); 210 } 211 212 Fault translateDataReadReq(CpuRequestPtr &req) 213 { 214 return dtb->translate(req, false); 215 } 216 217 Fault translateDataWriteReq(CpuRequestPtr &req) 218 { 219 return dtb->translate(req, true); 220 } 221 222#else 223 bool validInstAddr(Addr addr) 224 { return process->validInstAddr(addr); } 225 226 bool validDataAddr(Addr addr) 227 { return process->validDataAddr(addr); } 228 229 int getInstAsid() { return asid; } 230 int getDataAsid() { return asid; } 231 232 Fault translateInstReq(CpuRequestPtr &req) 233 { 234 return process->pTable->translate(req); 235 } 236 237 Fault translateDataReadReq(CpuRequestPtr &req) 238 { 239 return process->pTable->translate(req); 240 } 241 242 Fault translateDataWriteReq(CpuRequestPtr &req) 243 { 244 return process->pTable->translate(req); 245 } 246 247#endif 248 249/* 250 template <class T> 251 Fault read(CpuRequestPtr &req, T &data) 252 { 253#if FULL_SYSTEM && defined(TARGET_ALPHA) 254 if (req->flags & LOCKED) { 255 MiscRegFile *cregs = &req->xc->regs.miscRegs; 256 cregs->lock_addr = req->paddr; 257 cregs->lock_flag = true; 258 } 259#endif 260 261 Fault error; 262 error = mem->prot_read(req->paddr, data, req->size); 263 data = gtoh(data); 264 return error; 265 } 266 267 template <class T> 268 Fault write(CpuRequestPtr &req, T &data) 269 { 270#if FULL_SYSTEM && defined(TARGET_ALPHA) 271 272 MiscRegFile *cregs; 273 274 // If this is a store conditional, act appropriately 275 if (req->flags & LOCKED) { 276 cregs = &req->xc->regs.miscRegs; 277 278 if (req->flags & UNCACHEABLE) { 279 // Don't update result register (see stq_c in isa_desc) 280 req->result = 2; 281 req->xc->storeCondFailures = 0;//Needed? [RGD] 282 } else { 283 req->result = cregs->lock_flag; 284 if (!cregs->lock_flag || 285 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { 286 cregs->lock_flag = false; 287 if (((++req->xc->storeCondFailures) % 100000) == 0) { 288 std::cerr << "Warning: " 289 << req->xc->storeCondFailures 290 << " consecutive store conditional failures " 291 << "on cpu " << req->xc->cpu_id 292 << std::endl; 293 } 294 return No_Fault; 295 } 296 else req->xc->storeCondFailures = 0; 297 } 298 } 299 300 // Need to clear any locked flags on other proccessors for 301 // this address. Only do this for succsful Store Conditionals 302 // and all other stores (WH64?). Unsuccessful Store 303 // Conditionals would have returned above, and wouldn't fall 304 // through. 305 for (int i = 0; i < system->execContexts.size(); i++){ 306 cregs = &system->execContexts[i]->regs.miscRegs; 307 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { 308 cregs->lock_flag = false; 309 } 310 } 311 312#endif 313 return mem->prot_write(req->paddr, (T)htog(data), req->size); 314 } 315*/ 316 virtual bool misspeculating(); 317 318 319 MachInst getInst() { return inst; } 320 321 void setInst(MachInst new_inst) 322 { 323 inst = new_inst; 324 } 325 326 Fault instRead(CpuRequestPtr &req) 327 { 328 panic("instRead not implemented"); 329 // return funcPhysMem->read(req, inst); 330 return No_Fault; 331 } 332 333 // 334 // New accessors for new decoder. 335 // 336 uint64_t readIntReg(int reg_idx) 337 { 338 return regs.intRegFile[reg_idx]; 339 } 340 341 float readFloatRegSingle(int reg_idx) 342 { 343 return (float)regs.floatRegFile.d[reg_idx]; 344 } 345 346 double readFloatRegDouble(int reg_idx) 347 { 348 return regs.floatRegFile.d[reg_idx]; 349 } 350 351 uint64_t readFloatRegInt(int reg_idx) 352 { 353 return regs.floatRegFile.q[reg_idx]; 354 } 355 356 void setIntReg(int reg_idx, uint64_t val) 357 { 358 regs.intRegFile[reg_idx] = val; 359 } 360 361 void setFloatRegSingle(int reg_idx, float val) 362 { 363 regs.floatRegFile.d[reg_idx] = (double)val; 364 } 365 366 void setFloatRegDouble(int reg_idx, double val) 367 { 368 regs.floatRegFile.d[reg_idx] = val; 369 } 370 371 void setFloatRegInt(int reg_idx, uint64_t val) 372 { 373 regs.floatRegFile.q[reg_idx] = val; 374 } 375 376 uint64_t readPC() 377 { 378 return regs.pc; 379 } 380 381 void setNextPC(uint64_t val) 382 { 383 regs.npc = val; 384 } 385 386 uint64_t readUniq() 387 { 388 return regs.miscRegs.uniq; 389 } 390 391 void setUniq(uint64_t val) 392 { 393 regs.miscRegs.uniq = val; 394 } 395 396 uint64_t readFpcr() 397 { 398 return regs.miscRegs.fpcr; 399 } 400 401 void setFpcr(uint64_t val) 402 { 403 regs.miscRegs.fpcr = val; 404 } 405 406#if FULL_SYSTEM 407 uint64_t readIpr(int idx, Fault &fault); 408 Fault setIpr(int idx, uint64_t val); 409 int readIntrFlag() { return regs.intrflag; } 410 void setIntrFlag(int val) { regs.intrflag = val; } 411 Fault hwrei(); 412 bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } 413 void ev5_trap(Fault fault); 414 bool simPalCheck(int palFunc); 415#endif 416 417 /** Meant to be more generic trap function to be 418 * called when an instruction faults. 419 * @param fault The fault generated by executing the instruction. 420 * @todo How to do this properly so it's dependent upon ISA only? 421 */ 422 423 void trap(Fault fault); 424 425#if !FULL_SYSTEM 426 IntReg getSyscallArg(int i) 427 { 428 return regs.intRegFile[ArgumentReg0 + i]; 429 } 430 431 // used to shift args for indirect syscall 432 void setSyscallArg(int i, IntReg val) 433 { 434 regs.intRegFile[ArgumentReg0 + i] = val; 435 } 436 437 void setSyscallReturn(SyscallReturn return_value) 438 { 439 // check for error condition. Alpha syscall convention is to 440 // indicate success/failure in reg a3 (r19) and put the 441 // return value itself in the standard return value reg (v0). 442 const int RegA3 = 19; // only place this is used 443 if (return_value.successful()) { 444 // no error 445 regs.intRegFile[RegA3] = 0; 446 regs.intRegFile[ReturnValueReg] = return_value.value(); 447 } else { 448 // got an error, return details 449 regs.intRegFile[RegA3] = (IntReg) -1; 450 regs.intRegFile[ReturnValueReg] = -return_value.value(); 451 } 452 } 453 454 void syscall() 455 { 456 process->syscall(this); 457 } 458#endif 459}; 460 461 462// for non-speculative execution context, spec_mode is always false 463inline bool 464ExecContext::misspeculating() 465{ 466 return false; 467} 468 469#endif // __CPU_EXEC_CONTEXT_HH__ 470