simple_thread.hh revision 2132
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_EXEC_CONTEXT_HH__ 30#define __CPU_EXEC_CONTEXT_HH__ 31 32#include "config/full_system.hh" 33#include "mem/functional/functional.hh" 34#include "mem/mem_req.hh" 35#include "sim/host.hh" 36#include "sim/serialize.hh" 37#include "arch/isa_traits.hh" 38//#include "arch/isa_registers.hh" 39#include "sim/byteswap.hh" 40 41// forward declaration: see functional_memory.hh 42class FunctionalMemory; 43class PhysicalMemory; 44class BaseCPU; 45 46#if FULL_SYSTEM 47 48#include "sim/system.hh" 49#include "targetarch/alpha_memory.hh" 50 51class FunctionProfile; 52class ProfileNode; 53class MemoryController; 54namespace Kernel { class Binning; class Statistics; } 55 56#else // !FULL_SYSTEM 57 58#include "sim/process.hh" 59 60#endif // FULL_SYSTEM 61 62// 63// The ExecContext object represents a functional context for 64// instruction execution. It incorporates everything required for 65// architecture-level functional simulation of a single thread. 66// 67 68class ExecContext 69{ 70 protected: 71 typedef TheISA::RegFile RegFile; 72 typedef TheISA::MachInst MachInst; 73 typedef TheISA::MiscRegFile MiscRegFile; 74 public: 75 enum Status 76 { 77 /// Initialized but not running yet. All CPUs start in 78 /// this state, but most transition to Active on cycle 1. 79 /// In MP or SMT systems, non-primary contexts will stay 80 /// in this state until a thread is assigned to them. 81 Unallocated, 82 83 /// Running. Instructions should be executed only when 84 /// the context is in this state. 85 Active, 86 87 /// Temporarily inactive. Entered while waiting for 88 /// initialization,synchronization, etc. 89 Suspended, 90 91 /// Permanently shut down. Entered when target executes 92 /// m5exit pseudo-instruction. When all contexts enter 93 /// this state, the simulation will terminate. 94 Halted 95 }; 96 97 private: 98 Status _status; 99 100 public: 101 Status status() const { return _status; } 102 103 void setStatus(Status newStatus) { _status = newStatus; } 104 105 /// Set the status to Active. Optional delay indicates number of 106 /// cycles to wait before beginning execution. 107 void activate(int delay = 1); 108 109 /// Set the status to Suspended. 110 void suspend(); 111 112 /// Set the status to Unallocated. 113 void deallocate(); 114 115 /// Set the status to Halted. 116 void halt(); 117 118 public: 119 RegFile regs; // correct-path register context 120 121 // pointer to CPU associated with this context 122 BaseCPU *cpu; 123 124 // Current instruction 125 MachInst inst; 126 127 // Index of hardware thread context on the CPU that this represents. 128 int thread_num; 129 130 // ID of this context w.r.t. the System or Process object to which 131 // it belongs. For full-system mode, this is the system CPU ID. 132 int cpu_id; 133 134#if FULL_SYSTEM 135 FunctionalMemory *mem; 136 AlphaITB *itb; 137 AlphaDTB *dtb; 138 System *system; 139 140 // the following two fields are redundant, since we can always 141 // look them up through the system pointer, but we'll leave them 142 // here for now for convenience 143 MemoryController *memctrl; 144 PhysicalMemory *physmem; 145 146 Kernel::Binning *kernelBinning; 147 Kernel::Statistics *kernelStats; 148 bool bin; 149 bool fnbin; 150 151 FunctionProfile *profile; 152 ProfileNode *profileNode; 153 Addr profilePC; 154 void dumpFuncProfile(); 155 156#else 157 Process *process; 158 159 FunctionalMemory *mem; // functional storage for process address space 160 161 // Address space ID. Note that this is used for TIMING cache 162 // simulation only; all functional memory accesses should use 163 // one of the FunctionalMemory pointers above. 164 short asid; 165 166#endif 167 168 /** 169 * Temporary storage to pass the source address from copy_load to 170 * copy_store. 171 * @todo Remove this temporary when we have a better way to do it. 172 */ 173 Addr copySrcAddr; 174 /** 175 * Temp storage for the physical source address of a copy. 176 * @todo Remove this temporary when we have a better way to do it. 177 */ 178 Addr copySrcPhysAddr; 179 180 181 /* 182 * number of executed instructions, for matching with syscall trace 183 * points in EIO files. 184 */ 185 Counter func_exe_inst; 186 187 // 188 // Count failed store conditionals so we can warn of apparent 189 // application deadlock situations. 190 unsigned storeCondFailures; 191 192 // constructor: initialize context from given process structure 193#if FULL_SYSTEM 194 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 195 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); 196#else 197 ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); 198 ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem, 199 int _asid); 200#endif 201 virtual ~ExecContext(); 202 203 virtual void takeOverFrom(ExecContext *oldContext); 204 205 void regStats(const std::string &name); 206 207 void serialize(std::ostream &os); 208 void unserialize(Checkpoint *cp, const std::string §ion); 209 210#if FULL_SYSTEM 211 bool validInstAddr(Addr addr) { return true; } 212 bool validDataAddr(Addr addr) { return true; } 213 int getInstAsid() { return regs.instAsid(); } 214 int getDataAsid() { return regs.dataAsid(); } 215 216 Fault translateInstReq(MemReqPtr &req) 217 { 218 return itb->translate(req); 219 } 220 221 Fault translateDataReadReq(MemReqPtr &req) 222 { 223 return dtb->translate(req, false); 224 } 225 226 Fault translateDataWriteReq(MemReqPtr &req) 227 { 228 return dtb->translate(req, true); 229 } 230 231#else 232 bool validInstAddr(Addr addr) 233 { return process->validInstAddr(addr); } 234 235 bool validDataAddr(Addr addr) 236 { return process->validDataAddr(addr); } 237 238 int getInstAsid() { return asid; } 239 int getDataAsid() { return asid; } 240 241 Fault dummyTranslation(MemReqPtr &req) 242 { 243#if 0 244 assert((req->vaddr >> 48 & 0xffff) == 0); 245#endif 246 247 // put the asid in the upper 16 bits of the paddr 248 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); 249 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; 250 return NoFault; 251 } 252 Fault translateInstReq(MemReqPtr &req) 253 { 254 return dummyTranslation(req); 255 } 256 Fault translateDataReadReq(MemReqPtr &req) 257 { 258 return dummyTranslation(req); 259 } 260 Fault translateDataWriteReq(MemReqPtr &req) 261 { 262 return dummyTranslation(req); 263 } 264 265#endif 266 267 template <class T> 268 Fault read(MemReqPtr &req, T &data) 269 { 270#if FULL_SYSTEM && defined(TARGET_ALPHA) 271 if (req->flags & LOCKED) { 272 MiscRegFile *cregs = &req->xc->regs.miscRegs; 273 cregs->lock_addr = req->paddr; 274 cregs->lock_flag = true; 275 } 276#endif 277 278 Fault error; 279 error = mem->read(req, data); 280 data = LittleEndianGuest::gtoh(data); 281 return error; 282 } 283 284 template <class T> 285 Fault write(MemReqPtr &req, T &data) 286 { 287#if FULL_SYSTEM && defined(TARGET_ALPHA) 288 289 MiscRegFile *cregs; 290 291 // If this is a store conditional, act appropriately 292 if (req->flags & LOCKED) { 293 cregs = &req->xc->regs.miscRegs; 294 295 if (req->flags & UNCACHEABLE) { 296 // Don't update result register (see stq_c in isa_desc) 297 req->result = 2; 298 req->xc->storeCondFailures = 0;//Needed? [RGD] 299 } else { 300 req->result = cregs->lock_flag; 301 if (!cregs->lock_flag || 302 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { 303 cregs->lock_flag = false; 304 if (((++req->xc->storeCondFailures) % 100000) == 0) { 305 std::cerr << "Warning: " 306 << req->xc->storeCondFailures 307 << " consecutive store conditional failures " 308 << "on cpu " << req->xc->cpu_id 309 << std::endl; 310 } 311 return NoFault; 312 } 313 else req->xc->storeCondFailures = 0; 314 } 315 } 316 317 // Need to clear any locked flags on other proccessors for 318 // this address. Only do this for succsful Store Conditionals 319 // and all other stores (WH64?). Unsuccessful Store 320 // Conditionals would have returned above, and wouldn't fall 321 // through. 322 for (int i = 0; i < system->execContexts.size(); i++){ 323 cregs = &system->execContexts[i]->regs.miscRegs; 324 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { 325 cregs->lock_flag = false; 326 } 327 } 328 329#endif 330 return mem->write(req, (T)LittleEndianGuest::htog(data)); 331 } 332 333 virtual bool misspeculating(); 334 335 336 MachInst getInst() { return inst; } 337 338 void setInst(MachInst new_inst) 339 { 340 inst = new_inst; 341 } 342 343 Fault instRead(MemReqPtr &req) 344 { 345 return mem->read(req, inst); 346 } 347 348 // 349 // New accessors for new decoder. 350 // 351 uint64_t readIntReg(int reg_idx) 352 { 353 return regs.intRegFile[reg_idx]; 354 } 355 356 float readFloatRegSingle(int reg_idx) 357 { 358 return (float)regs.floatRegFile.d[reg_idx]; 359 } 360 361 double readFloatRegDouble(int reg_idx) 362 { 363 return regs.floatRegFile.d[reg_idx]; 364 } 365 366 uint64_t readFloatRegInt(int reg_idx) 367 { 368 return regs.floatRegFile.q[reg_idx]; 369 } 370 371 void setIntReg(int reg_idx, uint64_t val) 372 { 373 regs.intRegFile[reg_idx] = val; 374 } 375 376 void setFloatRegSingle(int reg_idx, float val) 377 { 378 regs.floatRegFile.d[reg_idx] = (double)val; 379 } 380 381 void setFloatRegDouble(int reg_idx, double val) 382 { 383 regs.floatRegFile.d[reg_idx] = val; 384 } 385 386 void setFloatRegInt(int reg_idx, uint64_t val) 387 { 388 regs.floatRegFile.q[reg_idx] = val; 389 } 390 391 uint64_t readPC() 392 { 393 return regs.pc; 394 } 395 396 void setNextPC(uint64_t val) 397 { 398 regs.npc = val; 399 } 400 401 uint64_t readUniq() 402 { 403 return regs.miscRegs.uniq; 404 } 405 406 void setUniq(uint64_t val) 407 { 408 regs.miscRegs.uniq = val; 409 } 410 411 uint64_t readFpcr() 412 { 413 return regs.miscRegs.fpcr; 414 } 415 416 void setFpcr(uint64_t val) 417 { 418 regs.miscRegs.fpcr = val; 419 } 420 421#if FULL_SYSTEM 422 uint64_t readIpr(int idx, Fault &fault); 423 Fault setIpr(int idx, uint64_t val); 424 int readIntrFlag() { return regs.intrflag; } 425 void setIntrFlag(int val) { regs.intrflag = val; } 426 Fault hwrei(); 427 bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } 428 void ev5_trap(Fault fault); 429 bool simPalCheck(int palFunc); 430#endif 431 432 /** Meant to be more generic trap function to be 433 * called when an instruction faults. 434 * @param fault The fault generated by executing the instruction. 435 * @todo How to do this properly so it's dependent upon ISA only? 436 */ 437 438 void trap(Fault fault); 439 440#if !FULL_SYSTEM 441 TheISA::IntReg getSyscallArg(int i) 442 { 443 return regs.intRegFile[TheISA::ArgumentReg0 + i]; 444 } 445 446 // used to shift args for indirect syscall 447 void setSyscallArg(int i, TheISA::IntReg val) 448 { 449 regs.intRegFile[TheISA::ArgumentReg0 + i] = val; 450 } 451 452 void setSyscallReturn(SyscallReturn return_value) 453 { 454 // check for error condition. Alpha syscall convention is to 455 // indicate success/failure in reg a3 (r19) and put the 456 // return value itself in the standard return value reg (v0). 457 const int RegA3 = 19; // only place this is used 458 if (return_value.successful()) { 459 // no error 460 regs.intRegFile[RegA3] = 0; 461 regs.intRegFile[TheISA::ReturnValueReg] = return_value.value(); 462 } else { 463 // got an error, return details 464 regs.intRegFile[RegA3] = (TheISA::IntReg) -1; 465 regs.intRegFile[TheISA::ReturnValueReg] = -return_value.value(); 466 } 467 } 468 469 void syscall() 470 { 471 process->syscall(this); 472 } 473#endif 474}; 475 476 477// for non-speculative execution context, spec_mode is always false 478inline bool 479ExecContext::misspeculating() 480{ 481 return false; 482} 483 484#endif // __CPU_EXEC_CONTEXT_HH__ 485