simple_thread.hh revision 13875
1/* 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2001-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 */ 44 45#ifndef __CPU_SIMPLE_THREAD_HH__ 46#define __CPU_SIMPLE_THREAD_HH__ 47 48#include "arch/decoder.hh" 49#include "arch/generic/tlb.hh" 50#include "arch/isa.hh" 51#include "arch/isa_traits.hh" 52#include "arch/registers.hh" 53#include "arch/types.hh" 54#include "base/types.hh" 55#include "config/the_isa.hh" 56#include "cpu/thread_context.hh" 57#include "cpu/thread_state.hh" 58#include "debug/CCRegs.hh" 59#include "debug/FloatRegs.hh" 60#include "debug/IntRegs.hh" 61#include "debug/VecPredRegs.hh" 62#include "debug/VecRegs.hh" 63#include "mem/page_table.hh" 64#include "mem/request.hh" 65#include "sim/byteswap.hh" 66#include "sim/eventq.hh" 67#include "sim/process.hh" 68#include "sim/serialize.hh" 69#include "sim/system.hh" 70 71class BaseCPU; 72class CheckerCPU; 73 74class FunctionProfile; 75class ProfileNode; 76 77namespace TheISA { 78 namespace Kernel { 79 class Statistics; 80 } 81} 82 83/** 84 * The SimpleThread object provides a combination of the ThreadState 85 * object and the ThreadContext interface. It implements the 86 * ThreadContext interface and adds to the ThreadState object by adding all 87 * the objects needed for simple functional execution, including a 88 * simple architectural register file, and pointers to the ITB and DTB 89 * in full system mode. For CPU models that do not need more advanced 90 * ways to hold state (i.e. a separate physical register file, or 91 * separate fetch and commit PC's), this SimpleThread class provides 92 * all the necessary state for full architecture-level functional 93 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 94 * examples. 95 */ 96 97class SimpleThread : public ThreadState, public ThreadContext 98{ 99 protected: 100 typedef TheISA::MachInst MachInst; 101 using VecRegContainer = TheISA::VecRegContainer; 102 using VecElem = TheISA::VecElem; 103 using VecPredRegContainer = TheISA::VecPredRegContainer; 104 public: 105 typedef ThreadContext::Status Status; 106 107 protected: 108 RegVal floatRegs[TheISA::NumFloatRegs]; 109 RegVal intRegs[TheISA::NumIntRegs]; 110 VecRegContainer vecRegs[TheISA::NumVecRegs]; 111 VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs]; 112#ifdef ISA_HAS_CC_REGS 113 RegVal ccRegs[TheISA::NumCCRegs]; 114#endif 115 TheISA::ISA *const isa; // one "instance" of the current ISA. 116 117 TheISA::PCState _pcState; 118 119 /** Did this instruction execute or is it predicated false */ 120 bool predicate; 121 122 public: 123 std::string name() const 124 { 125 return csprintf("%s.[tid:%i]", baseCpu->name(), threadId()); 126 } 127 128 System *system; 129 130 BaseTLB *itb; 131 BaseTLB *dtb; 132 133 TheISA::Decoder decoder; 134 135 // constructor: initialize SimpleThread from given process structure 136 // FS 137 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 138 BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa, 139 bool use_kernel_stats = true); 140 // SE 141 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 142 Process *_process, BaseTLB *_itb, BaseTLB *_dtb, 143 TheISA::ISA *_isa); 144 145 virtual ~SimpleThread() {} 146 147 void takeOverFrom(ThreadContext *oldContext) override; 148 149 void regStats(const std::string &name) override; 150 151 void copyState(ThreadContext *oldContext); 152 153 void serialize(CheckpointOut &cp) const override; 154 void unserialize(CheckpointIn &cp) override; 155 void startup(); 156 157 /*************************************************************** 158 * SimpleThread functions to provide CPU with access to various 159 * state. 160 **************************************************************/ 161 162 /** Returns the pointer to this SimpleThread's ThreadContext. Used 163 * when a ThreadContext must be passed to objects outside of the 164 * CPU. 165 */ 166 ThreadContext *getTC() { return this; } 167 168 void demapPage(Addr vaddr, uint64_t asn) 169 { 170 itb->demapPage(vaddr, asn); 171 dtb->demapPage(vaddr, asn); 172 } 173 174 void demapInstPage(Addr vaddr, uint64_t asn) 175 { 176 itb->demapPage(vaddr, asn); 177 } 178 179 void demapDataPage(Addr vaddr, uint64_t asn) 180 { 181 dtb->demapPage(vaddr, asn); 182 } 183 184 void dumpFuncProfile() override; 185 186 Fault hwrei(); 187 188 bool simPalCheck(int palFunc); 189 190 /******************************************* 191 * ThreadContext interface functions. 192 ******************************************/ 193 194 BaseCPU *getCpuPtr() override { return baseCpu; } 195 196 int cpuId() const override { return ThreadState::cpuId(); } 197 uint32_t socketId() const override { return ThreadState::socketId(); } 198 int threadId() const override { return ThreadState::threadId(); } 199 void setThreadId(int id) override { ThreadState::setThreadId(id); } 200 ContextID contextId() const override { return ThreadState::contextId(); } 201 void setContextId(ContextID id) override { ThreadState::setContextId(id); } 202 203 BaseTLB *getITBPtr() override { return itb; } 204 205 BaseTLB *getDTBPtr() override { return dtb; } 206 207 CheckerCPU *getCheckerCpuPtr() override { return NULL; } 208 209 TheISA::ISA *getIsaPtr() override { return isa; } 210 211 TheISA::Decoder *getDecoderPtr() override { return &decoder; } 212 213 System *getSystemPtr() override { return system; } 214 215 TheISA::Kernel::Statistics * 216 getKernelStats() override 217 { 218 return ThreadState::getKernelStats(); 219 } 220 221 PortProxy &getPhysProxy() override { return ThreadState::getPhysProxy(); } 222 FSTranslatingPortProxy & 223 getVirtProxy() override 224 { 225 return ThreadState::getVirtProxy(); 226 } 227 228 void initMemProxies(ThreadContext *tc) override 229 { 230 ThreadState::initMemProxies(tc); 231 } 232 233 SETranslatingPortProxy & 234 getMemProxy() override 235 { 236 return ThreadState::getMemProxy(); 237 } 238 239 Process *getProcessPtr() override { return ThreadState::getProcessPtr(); } 240 void setProcessPtr(Process *p) override { ThreadState::setProcessPtr(p); } 241 242 Status status() const override { return _status; } 243 244 void setStatus(Status newStatus) override { _status = newStatus; } 245 246 /// Set the status to Active. 247 void activate() override; 248 249 /// Set the status to Suspended. 250 void suspend() override; 251 252 /// Set the status to Halted. 253 void halt() override; 254 255 EndQuiesceEvent * 256 getQuiesceEvent() override 257 { 258 return ThreadState::getQuiesceEvent(); 259 } 260 261 Tick 262 readLastActivate() override 263 { 264 return ThreadState::readLastActivate(); 265 } 266 Tick 267 readLastSuspend() override 268 { 269 return ThreadState::readLastSuspend(); 270 } 271 272 void profileClear() override { ThreadState::profileClear(); } 273 void profileSample() override { ThreadState::profileSample(); } 274 275 void copyArchRegs(ThreadContext *tc) override; 276 277 void clearArchRegs() override 278 { 279 _pcState = 0; 280 memset(intRegs, 0, sizeof(intRegs)); 281 memset(floatRegs, 0, sizeof(floatRegs)); 282 for (int i = 0; i < TheISA::NumVecRegs; i++) { 283 vecRegs[i].zero(); 284 } 285 for (int i = 0; i < TheISA::NumVecPredRegs; i++) { 286 vecPredRegs[i].reset(); 287 } 288#ifdef ISA_HAS_CC_REGS 289 memset(ccRegs, 0, sizeof(ccRegs)); 290#endif 291 isa->clear(); 292 } 293 294 // 295 // New accessors for new decoder. 296 // 297 RegVal 298 readIntReg(RegIndex reg_idx) const override 299 { 300 int flatIndex = isa->flattenIntIndex(reg_idx); 301 assert(flatIndex < TheISA::NumIntRegs); 302 uint64_t regVal(readIntRegFlat(flatIndex)); 303 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 304 reg_idx, flatIndex, regVal); 305 return regVal; 306 } 307 308 RegVal 309 readFloatReg(RegIndex reg_idx) const override 310 { 311 int flatIndex = isa->flattenFloatIndex(reg_idx); 312 assert(flatIndex < TheISA::NumFloatRegs); 313 RegVal regVal(readFloatRegFlat(flatIndex)); 314 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", 315 reg_idx, flatIndex, regVal); 316 return regVal; 317 } 318 319 const VecRegContainer& 320 readVecReg(const RegId& reg) const override 321 { 322 int flatIndex = isa->flattenVecIndex(reg.index()); 323 assert(flatIndex < TheISA::NumVecRegs); 324 const VecRegContainer& regVal = readVecRegFlat(flatIndex); 325 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n", 326 reg.index(), flatIndex, regVal.print()); 327 return regVal; 328 } 329 330 VecRegContainer& 331 getWritableVecReg(const RegId& reg) override 332 { 333 int flatIndex = isa->flattenVecIndex(reg.index()); 334 assert(flatIndex < TheISA::NumVecRegs); 335 VecRegContainer& regVal = getWritableVecRegFlat(flatIndex); 336 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n", 337 reg.index(), flatIndex, regVal.print()); 338 return regVal; 339 } 340 341 /** Vector Register Lane Interfaces. */ 342 /** @{ */ 343 /** Reads source vector <T> operand. */ 344 template <typename T> 345 VecLaneT<T, true> 346 readVecLane(const RegId& reg) const 347 { 348 int flatIndex = isa->flattenVecIndex(reg.index()); 349 assert(flatIndex < TheISA::NumVecRegs); 350 auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex()); 351 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n", 352 reg.index(), flatIndex, reg.elemIndex(), regVal); 353 return regVal; 354 } 355 356 /** Reads source vector 8bit operand. */ 357 virtual ConstVecLane8 358 readVec8BitLaneReg(const RegId ®) const override 359 { 360 return readVecLane<uint8_t>(reg); 361 } 362 363 /** Reads source vector 16bit operand. */ 364 virtual ConstVecLane16 365 readVec16BitLaneReg(const RegId ®) const override 366 { 367 return readVecLane<uint16_t>(reg); 368 } 369 370 /** Reads source vector 32bit operand. */ 371 virtual ConstVecLane32 372 readVec32BitLaneReg(const RegId ®) const override 373 { 374 return readVecLane<uint32_t>(reg); 375 } 376 377 /** Reads source vector 64bit operand. */ 378 virtual ConstVecLane64 379 readVec64BitLaneReg(const RegId ®) const override 380 { 381 return readVecLane<uint64_t>(reg); 382 } 383 384 /** Write a lane of the destination vector register. */ 385 template <typename LD> 386 void 387 setVecLaneT(const RegId ®, const LD &val) 388 { 389 int flatIndex = isa->flattenVecIndex(reg.index()); 390 assert(flatIndex < TheISA::NumVecRegs); 391 setVecLaneFlat(flatIndex, reg.elemIndex(), val); 392 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n", 393 reg.index(), flatIndex, reg.elemIndex(), val); 394 } 395 virtual void 396 setVecLane(const RegId ®, const LaneData<LaneSize::Byte> &val) override 397 { 398 return setVecLaneT(reg, val); 399 } 400 virtual void 401 setVecLane(const RegId ®, 402 const LaneData<LaneSize::TwoByte> &val) override 403 { 404 return setVecLaneT(reg, val); 405 } 406 virtual void 407 setVecLane(const RegId ®, 408 const LaneData<LaneSize::FourByte> &val) override 409 { 410 return setVecLaneT(reg, val); 411 } 412 virtual void 413 setVecLane(const RegId ®, 414 const LaneData<LaneSize::EightByte> &val) override 415 { 416 return setVecLaneT(reg, val); 417 } 418 /** @} */ 419 420 const VecElem & 421 readVecElem(const RegId ®) const override 422 { 423 int flatIndex = isa->flattenVecElemIndex(reg.index()); 424 assert(flatIndex < TheISA::NumVecRegs); 425 const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex()); 426 DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as" 427 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal); 428 return regVal; 429 } 430 431 const VecPredRegContainer & 432 readVecPredReg(const RegId ®) const override 433 { 434 int flatIndex = isa->flattenVecPredIndex(reg.index()); 435 assert(flatIndex < TheISA::NumVecPredRegs); 436 const VecPredRegContainer& regVal = readVecPredRegFlat(flatIndex); 437 DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n", 438 reg.index(), flatIndex, regVal.print()); 439 return regVal; 440 } 441 442 VecPredRegContainer & 443 getWritableVecPredReg(const RegId ®) override 444 { 445 int flatIndex = isa->flattenVecPredIndex(reg.index()); 446 assert(flatIndex < TheISA::NumVecPredRegs); 447 VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex); 448 DPRINTF(VecPredRegs, 449 "Reading predicate reg %d (%d) as %s for modify.\n", 450 reg.index(), flatIndex, regVal.print()); 451 return regVal; 452 } 453 454 RegVal 455 readCCReg(RegIndex reg_idx) const override 456 { 457#ifdef ISA_HAS_CC_REGS 458 int flatIndex = isa->flattenCCIndex(reg_idx); 459 assert(0 <= flatIndex); 460 assert(flatIndex < TheISA::NumCCRegs); 461 uint64_t regVal(readCCRegFlat(flatIndex)); 462 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 463 reg_idx, flatIndex, regVal); 464 return regVal; 465#else 466 panic("Tried to read a CC register."); 467 return 0; 468#endif 469 } 470 471 void 472 setIntReg(RegIndex reg_idx, RegVal val) override 473 { 474 int flatIndex = isa->flattenIntIndex(reg_idx); 475 assert(flatIndex < TheISA::NumIntRegs); 476 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 477 reg_idx, flatIndex, val); 478 setIntRegFlat(flatIndex, val); 479 } 480 481 void 482 setFloatReg(RegIndex reg_idx, RegVal val) override 483 { 484 int flatIndex = isa->flattenFloatIndex(reg_idx); 485 assert(flatIndex < TheISA::NumFloatRegs); 486 // XXX: Fix array out of bounds compiler error for gem5.fast 487 // when checkercpu enabled 488 if (flatIndex < TheISA::NumFloatRegs) 489 setFloatRegFlat(flatIndex, val); 490 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", 491 reg_idx, flatIndex, val); 492 } 493 494 void 495 setVecReg(const RegId ®, const VecRegContainer &val) override 496 { 497 int flatIndex = isa->flattenVecIndex(reg.index()); 498 assert(flatIndex < TheISA::NumVecRegs); 499 setVecRegFlat(flatIndex, val); 500 DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n", 501 reg.index(), flatIndex, val.print()); 502 } 503 504 void 505 setVecElem(const RegId ®, const VecElem &val) override 506 { 507 int flatIndex = isa->flattenVecElemIndex(reg.index()); 508 assert(flatIndex < TheISA::NumVecRegs); 509 setVecElemFlat(flatIndex, reg.elemIndex(), val); 510 DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 511 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 512 } 513 514 void 515 setVecPredReg(const RegId ®, const VecPredRegContainer &val) override 516 { 517 int flatIndex = isa->flattenVecPredIndex(reg.index()); 518 assert(flatIndex < TheISA::NumVecPredRegs); 519 setVecPredRegFlat(flatIndex, val); 520 DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n", 521 reg.index(), flatIndex, val.print()); 522 } 523 524 void 525 setCCReg(RegIndex reg_idx, RegVal val) override 526 { 527#ifdef ISA_HAS_CC_REGS 528 int flatIndex = isa->flattenCCIndex(reg_idx); 529 assert(flatIndex < TheISA::NumCCRegs); 530 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 531 reg_idx, flatIndex, val); 532 setCCRegFlat(flatIndex, val); 533#else 534 panic("Tried to set a CC register."); 535#endif 536 } 537 538 TheISA::PCState pcState() const override { return _pcState; } 539 void pcState(const TheISA::PCState &val) override { _pcState = val; } 540 541 void 542 pcStateNoRecord(const TheISA::PCState &val) override 543 { 544 _pcState = val; 545 } 546 547 Addr instAddr() const override { return _pcState.instAddr(); } 548 Addr nextInstAddr() const override { return _pcState.nextInstAddr(); } 549 MicroPC microPC() const override { return _pcState.microPC(); } 550 bool readPredicate() const { return predicate; } 551 void setPredicate(bool val) { predicate = val; } 552 553 RegVal 554 readMiscRegNoEffect(RegIndex misc_reg) const override 555 { 556 return isa->readMiscRegNoEffect(misc_reg); 557 } 558 559 RegVal 560 readMiscReg(RegIndex misc_reg) override 561 { 562 return isa->readMiscReg(misc_reg, this); 563 } 564 565 void 566 setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override 567 { 568 return isa->setMiscRegNoEffect(misc_reg, val); 569 } 570 571 void 572 setMiscReg(RegIndex misc_reg, RegVal val) override 573 { 574 return isa->setMiscReg(misc_reg, val, this); 575 } 576 577 RegId 578 flattenRegId(const RegId& regId) const override 579 { 580 return isa->flattenRegId(regId); 581 } 582 583 unsigned readStCondFailures() const override { return storeCondFailures; } 584 585 void 586 setStCondFailures(unsigned sc_failures) override 587 { 588 storeCondFailures = sc_failures; 589 } 590 591 Counter 592 readFuncExeInst() const override 593 { 594 return ThreadState::readFuncExeInst(); 595 } 596 597 void 598 syscall(int64_t callnum, Fault *fault) override 599 { 600 process->syscall(callnum, this, fault); 601 } 602 603 RegVal readIntRegFlat(RegIndex idx) const override { return intRegs[idx]; } 604 void 605 setIntRegFlat(RegIndex idx, RegVal val) override 606 { 607 intRegs[idx] = val; 608 } 609 610 RegVal 611 readFloatRegFlat(RegIndex idx) const override 612 { 613 return floatRegs[idx]; 614 } 615 void 616 setFloatRegFlat(RegIndex idx, RegVal val) override 617 { 618 floatRegs[idx] = val; 619 } 620 621 const VecRegContainer & 622 readVecRegFlat(RegIndex reg) const override 623 { 624 return vecRegs[reg]; 625 } 626 627 VecRegContainer & 628 getWritableVecRegFlat(RegIndex reg) override 629 { 630 return vecRegs[reg]; 631 } 632 633 void 634 setVecRegFlat(RegIndex reg, const VecRegContainer &val) override 635 { 636 vecRegs[reg] = val; 637 } 638 639 template <typename T> 640 VecLaneT<T, true> 641 readVecLaneFlat(RegIndex reg, int lId) const 642 { 643 return vecRegs[reg].laneView<T>(lId); 644 } 645 646 template <typename LD> 647 void 648 setVecLaneFlat(RegIndex reg, int lId, const LD &val) 649 { 650 vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; 651 } 652 653 const VecElem & 654 readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override 655 { 656 return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; 657 } 658 659 void 660 setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex, 661 const VecElem &val) override 662 { 663 vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 664 } 665 666 const VecPredRegContainer & 667 readVecPredRegFlat(RegIndex reg) const override 668 { 669 return vecPredRegs[reg]; 670 } 671 672 VecPredRegContainer & 673 getWritableVecPredRegFlat(RegIndex reg) override 674 { 675 return vecPredRegs[reg]; 676 } 677 678 void 679 setVecPredRegFlat(RegIndex reg, const VecPredRegContainer &val) override 680 { 681 vecPredRegs[reg] = val; 682 } 683 684#ifdef ISA_HAS_CC_REGS 685 RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; } 686 void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] = val; } 687#else 688 RegVal 689 readCCRegFlat(RegIndex idx) const override 690 { 691 panic("readCCRegFlat w/no CC regs!\n"); 692 } 693 694 void 695 setCCRegFlat(RegIndex idx, RegVal val) override 696 { 697 panic("setCCRegFlat w/no CC regs!\n"); 698 } 699#endif 700}; 701 702 703#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 704