simple_thread.hh revision 13622:ba31c2a23eca
1/* 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2001-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 */ 44 45#ifndef __CPU_SIMPLE_THREAD_HH__ 46#define __CPU_SIMPLE_THREAD_HH__ 47 48#include "arch/decoder.hh" 49#include "arch/generic/tlb.hh" 50#include "arch/isa.hh" 51#include "arch/isa_traits.hh" 52#include "arch/registers.hh" 53#include "arch/types.hh" 54#include "base/types.hh" 55#include "config/the_isa.hh" 56#include "cpu/thread_context.hh" 57#include "cpu/thread_state.hh" 58#include "debug/CCRegs.hh" 59#include "debug/FloatRegs.hh" 60#include "debug/IntRegs.hh" 61#include "debug/VecPredRegs.hh" 62#include "debug/VecRegs.hh" 63#include "mem/page_table.hh" 64#include "mem/request.hh" 65#include "sim/byteswap.hh" 66#include "sim/eventq.hh" 67#include "sim/process.hh" 68#include "sim/serialize.hh" 69#include "sim/system.hh" 70 71class BaseCPU; 72class CheckerCPU; 73 74class FunctionProfile; 75class ProfileNode; 76 77namespace TheISA { 78 namespace Kernel { 79 class Statistics; 80 } 81} 82 83/** 84 * The SimpleThread object provides a combination of the ThreadState 85 * object and the ThreadContext interface. It implements the 86 * ThreadContext interface so that a ProxyThreadContext class can be 87 * made using SimpleThread as the template parameter (see 88 * thread_context.hh). It adds to the ThreadState object by adding all 89 * the objects needed for simple functional execution, including a 90 * simple architectural register file, and pointers to the ITB and DTB 91 * in full system mode. For CPU models that do not need more advanced 92 * ways to hold state (i.e. a separate physical register file, or 93 * separate fetch and commit PC's), this SimpleThread class provides 94 * all the necessary state for full architecture-level functional 95 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 96 * examples. 97 */ 98 99class SimpleThread : public ThreadState 100{ 101 protected: 102 typedef TheISA::MachInst MachInst; 103 using VecRegContainer = TheISA::VecRegContainer; 104 using VecElem = TheISA::VecElem; 105 using VecPredRegContainer = TheISA::VecPredRegContainer; 106 public: 107 typedef ThreadContext::Status Status; 108 109 protected: 110 RegVal floatRegs[TheISA::NumFloatRegs]; 111 RegVal intRegs[TheISA::NumIntRegs]; 112 VecRegContainer vecRegs[TheISA::NumVecRegs]; 113 VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs]; 114#ifdef ISA_HAS_CC_REGS 115 RegVal ccRegs[TheISA::NumCCRegs]; 116#endif 117 TheISA::ISA *const isa; // one "instance" of the current ISA. 118 119 TheISA::PCState _pcState; 120 121 /** Did this instruction execute or is it predicated false */ 122 bool predicate; 123 124 public: 125 std::string name() const 126 { 127 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 128 } 129 130 ProxyThreadContext<SimpleThread> *tc; 131 132 System *system; 133 134 BaseTLB *itb; 135 BaseTLB *dtb; 136 137 TheISA::Decoder decoder; 138 139 // constructor: initialize SimpleThread from given process structure 140 // FS 141 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 142 BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa, 143 bool use_kernel_stats = true); 144 // SE 145 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 146 Process *_process, BaseTLB *_itb, BaseTLB *_dtb, 147 TheISA::ISA *_isa); 148 149 virtual ~SimpleThread(); 150 151 virtual void takeOverFrom(ThreadContext *oldContext); 152 153 void regStats(const std::string &name); 154 155 void copyState(ThreadContext *oldContext); 156 157 void serialize(CheckpointOut &cp) const override; 158 void unserialize(CheckpointIn &cp) override; 159 void startup(); 160 161 /*************************************************************** 162 * SimpleThread functions to provide CPU with access to various 163 * state. 164 **************************************************************/ 165 166 /** Returns the pointer to this SimpleThread's ThreadContext. Used 167 * when a ThreadContext must be passed to objects outside of the 168 * CPU. 169 */ 170 ThreadContext *getTC() { return tc; } 171 172 void demapPage(Addr vaddr, uint64_t asn) 173 { 174 itb->demapPage(vaddr, asn); 175 dtb->demapPage(vaddr, asn); 176 } 177 178 void demapInstPage(Addr vaddr, uint64_t asn) 179 { 180 itb->demapPage(vaddr, asn); 181 } 182 183 void demapDataPage(Addr vaddr, uint64_t asn) 184 { 185 dtb->demapPage(vaddr, asn); 186 } 187 188 void dumpFuncProfile(); 189 190 Fault hwrei(); 191 192 bool simPalCheck(int palFunc); 193 194 /******************************************* 195 * ThreadContext interface functions. 196 ******************************************/ 197 198 BaseCPU *getCpuPtr() { return baseCpu; } 199 200 BaseTLB *getITBPtr() { return itb; } 201 202 BaseTLB *getDTBPtr() { return dtb; } 203 204 CheckerCPU *getCheckerCpuPtr() { return NULL; } 205 206 TheISA::Decoder *getDecoderPtr() { return &decoder; } 207 208 System *getSystemPtr() { return system; } 209 210 Status status() const { return _status; } 211 212 void setStatus(Status newStatus) { _status = newStatus; } 213 214 /// Set the status to Active. 215 void activate(); 216 217 /// Set the status to Suspended. 218 void suspend(); 219 220 /// Set the status to Halted. 221 void halt(); 222 223 void copyArchRegs(ThreadContext *tc); 224 225 void clearArchRegs() 226 { 227 _pcState = 0; 228 memset(intRegs, 0, sizeof(intRegs)); 229 memset(floatRegs, 0, sizeof(floatRegs)); 230 for (int i = 0; i < TheISA::NumVecRegs; i++) { 231 vecRegs[i].zero(); 232 } 233 for (int i = 0; i < TheISA::NumVecPredRegs; i++) { 234 vecPredRegs[i].reset(); 235 } 236#ifdef ISA_HAS_CC_REGS 237 memset(ccRegs, 0, sizeof(ccRegs)); 238#endif 239 isa->clear(); 240 } 241 242 // 243 // New accessors for new decoder. 244 // 245 RegVal 246 readIntReg(int reg_idx) 247 { 248 int flatIndex = isa->flattenIntIndex(reg_idx); 249 assert(flatIndex < TheISA::NumIntRegs); 250 uint64_t regVal(readIntRegFlat(flatIndex)); 251 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 252 reg_idx, flatIndex, regVal); 253 return regVal; 254 } 255 256 RegVal 257 readFloatReg(int reg_idx) 258 { 259 int flatIndex = isa->flattenFloatIndex(reg_idx); 260 assert(flatIndex < TheISA::NumFloatRegs); 261 RegVal regVal(readFloatRegFlat(flatIndex)); 262 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", 263 reg_idx, flatIndex, regVal); 264 return regVal; 265 } 266 267 const VecRegContainer& 268 readVecReg(const RegId& reg) const 269 { 270 int flatIndex = isa->flattenVecIndex(reg.index()); 271 assert(flatIndex < TheISA::NumVecRegs); 272 const VecRegContainer& regVal = readVecRegFlat(flatIndex); 273 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n", 274 reg.index(), flatIndex, regVal.print()); 275 return regVal; 276 } 277 278 VecRegContainer& 279 getWritableVecReg(const RegId& reg) 280 { 281 int flatIndex = isa->flattenVecIndex(reg.index()); 282 assert(flatIndex < TheISA::NumVecRegs); 283 VecRegContainer& regVal = getWritableVecRegFlat(flatIndex); 284 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n", 285 reg.index(), flatIndex, regVal.print()); 286 return regVal; 287 } 288 289 /** Vector Register Lane Interfaces. */ 290 /** @{ */ 291 /** Reads source vector <T> operand. */ 292 template <typename T> 293 VecLaneT<T, true> 294 readVecLane(const RegId& reg) const 295 { 296 int flatIndex = isa->flattenVecIndex(reg.index()); 297 assert(flatIndex < TheISA::NumVecRegs); 298 auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex()); 299 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n", 300 reg.index(), flatIndex, reg.elemIndex(), regVal); 301 return regVal; 302 } 303 304 /** Reads source vector 8bit operand. */ 305 virtual ConstVecLane8 306 readVec8BitLaneReg(const RegId& reg) const 307 { return readVecLane<uint8_t>(reg); } 308 309 /** Reads source vector 16bit operand. */ 310 virtual ConstVecLane16 311 readVec16BitLaneReg(const RegId& reg) const 312 { return readVecLane<uint16_t>(reg); } 313 314 /** Reads source vector 32bit operand. */ 315 virtual ConstVecLane32 316 readVec32BitLaneReg(const RegId& reg) const 317 { return readVecLane<uint32_t>(reg); } 318 319 /** Reads source vector 64bit operand. */ 320 virtual ConstVecLane64 321 readVec64BitLaneReg(const RegId& reg) const 322 { return readVecLane<uint64_t>(reg); } 323 324 /** Write a lane of the destination vector register. */ 325 template <typename LD> 326 void setVecLaneT(const RegId& reg, const LD& val) 327 { 328 int flatIndex = isa->flattenVecIndex(reg.index()); 329 assert(flatIndex < TheISA::NumVecRegs); 330 setVecLaneFlat(flatIndex, reg.elemIndex(), val); 331 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n", 332 reg.index(), flatIndex, reg.elemIndex(), val); 333 } 334 virtual void setVecLane(const RegId& reg, 335 const LaneData<LaneSize::Byte>& val) 336 { return setVecLaneT(reg, val); } 337 virtual void setVecLane(const RegId& reg, 338 const LaneData<LaneSize::TwoByte>& val) 339 { return setVecLaneT(reg, val); } 340 virtual void setVecLane(const RegId& reg, 341 const LaneData<LaneSize::FourByte>& val) 342 { return setVecLaneT(reg, val); } 343 virtual void setVecLane(const RegId& reg, 344 const LaneData<LaneSize::EightByte>& val) 345 { return setVecLaneT(reg, val); } 346 /** @} */ 347 348 const VecElem& readVecElem(const RegId& reg) const 349 { 350 int flatIndex = isa->flattenVecElemIndex(reg.index()); 351 assert(flatIndex < TheISA::NumVecRegs); 352 const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex()); 353 DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as" 354 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal); 355 return regVal; 356 } 357 358 const VecPredRegContainer& 359 readVecPredReg(const RegId& reg) const 360 { 361 int flatIndex = isa->flattenVecPredIndex(reg.index()); 362 assert(flatIndex < TheISA::NumVecPredRegs); 363 const VecPredRegContainer& regVal = readVecPredRegFlat(flatIndex); 364 DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n", 365 reg.index(), flatIndex, regVal.print()); 366 return regVal; 367 } 368 369 VecPredRegContainer& 370 getWritableVecPredReg(const RegId& reg) 371 { 372 int flatIndex = isa->flattenVecPredIndex(reg.index()); 373 assert(flatIndex < TheISA::NumVecPredRegs); 374 VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex); 375 DPRINTF(VecPredRegs, 376 "Reading predicate reg %d (%d) as %s for modify.\n", 377 reg.index(), flatIndex, regVal.print()); 378 return regVal; 379 } 380 381 RegVal 382 readCCReg(int reg_idx) 383 { 384#ifdef ISA_HAS_CC_REGS 385 int flatIndex = isa->flattenCCIndex(reg_idx); 386 assert(0 <= flatIndex); 387 assert(flatIndex < TheISA::NumCCRegs); 388 uint64_t regVal(readCCRegFlat(flatIndex)); 389 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 390 reg_idx, flatIndex, regVal); 391 return regVal; 392#else 393 panic("Tried to read a CC register."); 394 return 0; 395#endif 396 } 397 398 void 399 setIntReg(int reg_idx, RegVal val) 400 { 401 int flatIndex = isa->flattenIntIndex(reg_idx); 402 assert(flatIndex < TheISA::NumIntRegs); 403 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 404 reg_idx, flatIndex, val); 405 setIntRegFlat(flatIndex, val); 406 } 407 408 void 409 setFloatReg(int reg_idx, RegVal val) 410 { 411 int flatIndex = isa->flattenFloatIndex(reg_idx); 412 assert(flatIndex < TheISA::NumFloatRegs); 413 // XXX: Fix array out of bounds compiler error for gem5.fast 414 // when checkercpu enabled 415 if (flatIndex < TheISA::NumFloatRegs) 416 setFloatRegFlat(flatIndex, val); 417 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", 418 reg_idx, flatIndex, val); 419 } 420 421 void 422 setVecReg(const RegId& reg, const VecRegContainer& val) 423 { 424 int flatIndex = isa->flattenVecIndex(reg.index()); 425 assert(flatIndex < TheISA::NumVecRegs); 426 setVecRegFlat(flatIndex, val); 427 DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n", 428 reg.index(), flatIndex, val.print()); 429 } 430 431 void 432 setVecElem(const RegId& reg, const VecElem& val) 433 { 434 int flatIndex = isa->flattenVecElemIndex(reg.index()); 435 assert(flatIndex < TheISA::NumVecRegs); 436 setVecElemFlat(flatIndex, reg.elemIndex(), val); 437 DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 438 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 439 } 440 441 void 442 setVecPredReg(const RegId& reg, const VecPredRegContainer& val) 443 { 444 int flatIndex = isa->flattenVecPredIndex(reg.index()); 445 assert(flatIndex < TheISA::NumVecPredRegs); 446 setVecPredRegFlat(flatIndex, val); 447 DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n", 448 reg.index(), flatIndex, val.print()); 449 } 450 451 void 452 setCCReg(int reg_idx, RegVal val) 453 { 454#ifdef ISA_HAS_CC_REGS 455 int flatIndex = isa->flattenCCIndex(reg_idx); 456 assert(flatIndex < TheISA::NumCCRegs); 457 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 458 reg_idx, flatIndex, val); 459 setCCRegFlat(flatIndex, val); 460#else 461 panic("Tried to set a CC register."); 462#endif 463 } 464 465 TheISA::PCState 466 pcState() 467 { 468 return _pcState; 469 } 470 471 void 472 pcState(const TheISA::PCState &val) 473 { 474 _pcState = val; 475 } 476 477 void 478 pcStateNoRecord(const TheISA::PCState &val) 479 { 480 _pcState = val; 481 } 482 483 Addr 484 instAddr() 485 { 486 return _pcState.instAddr(); 487 } 488 489 Addr 490 nextInstAddr() 491 { 492 return _pcState.nextInstAddr(); 493 } 494 495 void 496 setNPC(Addr val) 497 { 498 _pcState.setNPC(val); 499 } 500 501 MicroPC 502 microPC() 503 { 504 return _pcState.microPC(); 505 } 506 507 bool readPredicate() 508 { 509 return predicate; 510 } 511 512 void setPredicate(bool val) 513 { 514 predicate = val; 515 } 516 517 RegVal 518 readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const 519 { 520 return isa->readMiscRegNoEffect(misc_reg); 521 } 522 523 RegVal 524 readMiscReg(int misc_reg, ThreadID tid=0) 525 { 526 return isa->readMiscReg(misc_reg, tc); 527 } 528 529 void 530 setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid = 0) 531 { 532 return isa->setMiscRegNoEffect(misc_reg, val); 533 } 534 535 void 536 setMiscReg(int misc_reg, RegVal val, ThreadID tid = 0) 537 { 538 return isa->setMiscReg(misc_reg, val, tc); 539 } 540 541 RegId 542 flattenRegId(const RegId& regId) const 543 { 544 return isa->flattenRegId(regId); 545 } 546 547 unsigned readStCondFailures() { return storeCondFailures; } 548 549 void setStCondFailures(unsigned sc_failures) 550 { storeCondFailures = sc_failures; } 551 552 void 553 syscall(int64_t callnum, Fault *fault) 554 { 555 process->syscall(callnum, tc, fault); 556 } 557 558 RegVal readIntRegFlat(int idx) { return intRegs[idx]; } 559 void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; } 560 561 RegVal readFloatRegFlat(int idx) { return floatRegs[idx]; } 562 void setFloatRegFlat(int idx, RegVal val) { floatRegs[idx] = val; } 563 564 const VecRegContainer & 565 readVecRegFlat(const RegIndex& reg) const 566 { 567 return vecRegs[reg]; 568 } 569 570 VecRegContainer & 571 getWritableVecRegFlat(const RegIndex& reg) 572 { 573 return vecRegs[reg]; 574 } 575 576 void 577 setVecRegFlat(const RegIndex& reg, const VecRegContainer& val) 578 { 579 vecRegs[reg] = val; 580 } 581 582 template <typename T> 583 VecLaneT<T, true> 584 readVecLaneFlat(const RegIndex& reg, int lId) const 585 { 586 return vecRegs[reg].laneView<T>(lId); 587 } 588 589 template <typename LD> 590 void 591 setVecLaneFlat(const RegIndex& reg, int lId, const LD& val) 592 { 593 vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; 594 } 595 596 const VecElem & 597 readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const 598 { 599 return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; 600 } 601 602 void 603 setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex, 604 const VecElem val) 605 { 606 vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 607 } 608 609 const VecPredRegContainer& readVecPredRegFlat(const RegIndex& reg) const 610 { 611 return vecPredRegs[reg]; 612 } 613 614 VecPredRegContainer& getWritableVecPredRegFlat(const RegIndex& reg) 615 { 616 return vecPredRegs[reg]; 617 } 618 619 void setVecPredRegFlat(const RegIndex& reg, const VecPredRegContainer& val) 620 { 621 vecPredRegs[reg] = val; 622 } 623 624#ifdef ISA_HAS_CC_REGS 625 RegVal readCCRegFlat(int idx) { return ccRegs[idx]; } 626 void setCCRegFlat(int idx, RegVal val) { ccRegs[idx] = val; } 627#else 628 RegVal readCCRegFlat(int idx) 629 { panic("readCCRegFlat w/no CC regs!\n"); } 630 631 void setCCRegFlat(int idx, RegVal val) 632 { panic("setCCRegFlat w/no CC regs!\n"); } 633#endif 634}; 635 636 637#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 638