simple_thread.hh revision 12406:86bde4a026b5
1/* 2 * Copyright (c) 2011-2012, 2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2001-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 */ 44 45#ifndef __CPU_SIMPLE_THREAD_HH__ 46#define __CPU_SIMPLE_THREAD_HH__ 47 48#include "arch/decoder.hh" 49#include "arch/generic/tlb.hh" 50#include "arch/isa.hh" 51#include "arch/isa_traits.hh" 52#include "arch/registers.hh" 53#include "arch/types.hh" 54#include "base/types.hh" 55#include "config/the_isa.hh" 56#include "cpu/thread_context.hh" 57#include "cpu/thread_state.hh" 58#include "debug/CCRegs.hh" 59#include "debug/FloatRegs.hh" 60#include "debug/IntRegs.hh" 61#include "debug/VecRegs.hh" 62#include "mem/page_table.hh" 63#include "mem/request.hh" 64#include "sim/byteswap.hh" 65#include "sim/eventq.hh" 66#include "sim/process.hh" 67#include "sim/serialize.hh" 68#include "sim/system.hh" 69 70class BaseCPU; 71class CheckerCPU; 72 73class FunctionProfile; 74class ProfileNode; 75 76namespace TheISA { 77 namespace Kernel { 78 class Statistics; 79 } 80} 81 82/** 83 * The SimpleThread object provides a combination of the ThreadState 84 * object and the ThreadContext interface. It implements the 85 * ThreadContext interface so that a ProxyThreadContext class can be 86 * made using SimpleThread as the template parameter (see 87 * thread_context.hh). It adds to the ThreadState object by adding all 88 * the objects needed for simple functional execution, including a 89 * simple architectural register file, and pointers to the ITB and DTB 90 * in full system mode. For CPU models that do not need more advanced 91 * ways to hold state (i.e. a separate physical register file, or 92 * separate fetch and commit PC's), this SimpleThread class provides 93 * all the necessary state for full architecture-level functional 94 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 95 * examples. 96 */ 97 98class SimpleThread : public ThreadState 99{ 100 protected: 101 typedef TheISA::MachInst MachInst; 102 typedef TheISA::MiscReg MiscReg; 103 typedef TheISA::FloatReg FloatReg; 104 typedef TheISA::FloatRegBits FloatRegBits; 105 typedef TheISA::CCReg CCReg; 106 using VecRegContainer = TheISA::VecRegContainer; 107 using VecElem = TheISA::VecElem; 108 public: 109 typedef ThreadContext::Status Status; 110 111 protected: 112 union { 113 FloatReg f[TheISA::NumFloatRegs]; 114 FloatRegBits i[TheISA::NumFloatRegs]; 115 } floatRegs; 116 TheISA::IntReg intRegs[TheISA::NumIntRegs]; 117 VecRegContainer vecRegs[TheISA::NumVecRegs]; 118#ifdef ISA_HAS_CC_REGS 119 TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 120#endif 121 TheISA::ISA *const isa; // one "instance" of the current ISA. 122 123 TheISA::PCState _pcState; 124 125 /** Did this instruction execute or is it predicated false */ 126 bool predicate; 127 128 public: 129 std::string name() const 130 { 131 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 132 } 133 134 ProxyThreadContext<SimpleThread> *tc; 135 136 System *system; 137 138 BaseTLB *itb; 139 BaseTLB *dtb; 140 141 TheISA::Decoder decoder; 142 143 // constructor: initialize SimpleThread from given process structure 144 // FS 145 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 146 BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa, 147 bool use_kernel_stats = true); 148 // SE 149 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 150 Process *_process, BaseTLB *_itb, BaseTLB *_dtb, 151 TheISA::ISA *_isa); 152 153 virtual ~SimpleThread(); 154 155 virtual void takeOverFrom(ThreadContext *oldContext); 156 157 void regStats(const std::string &name); 158 159 void copyState(ThreadContext *oldContext); 160 161 void serialize(CheckpointOut &cp) const override; 162 void unserialize(CheckpointIn &cp) override; 163 void startup(); 164 165 /*************************************************************** 166 * SimpleThread functions to provide CPU with access to various 167 * state. 168 **************************************************************/ 169 170 /** Returns the pointer to this SimpleThread's ThreadContext. Used 171 * when a ThreadContext must be passed to objects outside of the 172 * CPU. 173 */ 174 ThreadContext *getTC() { return tc; } 175 176 void demapPage(Addr vaddr, uint64_t asn) 177 { 178 itb->demapPage(vaddr, asn); 179 dtb->demapPage(vaddr, asn); 180 } 181 182 void demapInstPage(Addr vaddr, uint64_t asn) 183 { 184 itb->demapPage(vaddr, asn); 185 } 186 187 void demapDataPage(Addr vaddr, uint64_t asn) 188 { 189 dtb->demapPage(vaddr, asn); 190 } 191 192 void dumpFuncProfile(); 193 194 Fault hwrei(); 195 196 bool simPalCheck(int palFunc); 197 198 /******************************************* 199 * ThreadContext interface functions. 200 ******************************************/ 201 202 BaseCPU *getCpuPtr() { return baseCpu; } 203 204 BaseTLB *getITBPtr() { return itb; } 205 206 BaseTLB *getDTBPtr() { return dtb; } 207 208 CheckerCPU *getCheckerCpuPtr() { return NULL; } 209 210 TheISA::Decoder *getDecoderPtr() { return &decoder; } 211 212 System *getSystemPtr() { return system; } 213 214 Status status() const { return _status; } 215 216 void setStatus(Status newStatus) { _status = newStatus; } 217 218 /// Set the status to Active. 219 void activate(); 220 221 /// Set the status to Suspended. 222 void suspend(); 223 224 /// Set the status to Halted. 225 void halt(); 226 227 void copyArchRegs(ThreadContext *tc); 228 229 void clearArchRegs() 230 { 231 _pcState = 0; 232 memset(intRegs, 0, sizeof(intRegs)); 233 memset(floatRegs.i, 0, sizeof(floatRegs.i)); 234 for (int i = 0; i < TheISA::NumVecRegs; i++) { 235 vecRegs[i].zero(); 236 } 237#ifdef ISA_HAS_CC_REGS 238 memset(ccRegs, 0, sizeof(ccRegs)); 239#endif 240 isa->clear(); 241 } 242 243 // 244 // New accessors for new decoder. 245 // 246 uint64_t readIntReg(int reg_idx) 247 { 248 int flatIndex = isa->flattenIntIndex(reg_idx); 249 assert(flatIndex < TheISA::NumIntRegs); 250 uint64_t regVal(readIntRegFlat(flatIndex)); 251 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 252 reg_idx, flatIndex, regVal); 253 return regVal; 254 } 255 256 FloatReg readFloatReg(int reg_idx) 257 { 258 int flatIndex = isa->flattenFloatIndex(reg_idx); 259 assert(flatIndex < TheISA::NumFloatRegs); 260 FloatReg regVal(readFloatRegFlat(flatIndex)); 261 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 262 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 263 return regVal; 264 } 265 266 FloatRegBits readFloatRegBits(int reg_idx) 267 { 268 int flatIndex = isa->flattenFloatIndex(reg_idx); 269 assert(flatIndex < TheISA::NumFloatRegs); 270 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); 271 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 272 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 273 return regVal; 274 } 275 276 const VecRegContainer& 277 readVecReg(const RegId& reg) const 278 { 279 int flatIndex = isa->flattenVecIndex(reg.index()); 280 assert(flatIndex < TheISA::NumVecRegs); 281 const VecRegContainer& regVal = readVecRegFlat(flatIndex); 282 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n", 283 reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print()); 284 return regVal; 285 } 286 287 VecRegContainer& 288 getWritableVecReg(const RegId& reg) 289 { 290 int flatIndex = isa->flattenVecIndex(reg.index()); 291 assert(flatIndex < TheISA::NumVecRegs); 292 VecRegContainer& regVal = getWritableVecRegFlat(flatIndex); 293 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n", 294 reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print()); 295 return regVal; 296 } 297 298 /** Vector Register Lane Interfaces. */ 299 /** @{ */ 300 /** Reads source vector <T> operand. */ 301 template <typename T> 302 VecLaneT<T, true> 303 readVecLane(const RegId& reg) const 304 { 305 int flatIndex = isa->flattenVecIndex(reg.index()); 306 assert(flatIndex < TheISA::NumVecRegs); 307 auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex()); 308 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n", 309 reg.index(), flatIndex, reg.elemIndex(), regVal); 310 return regVal; 311 } 312 313 /** Reads source vector 8bit operand. */ 314 virtual ConstVecLane8 315 readVec8BitLaneReg(const RegId& reg) const 316 { return readVecLane<uint8_t>(reg); } 317 318 /** Reads source vector 16bit operand. */ 319 virtual ConstVecLane16 320 readVec16BitLaneReg(const RegId& reg) const 321 { return readVecLane<uint16_t>(reg); } 322 323 /** Reads source vector 32bit operand. */ 324 virtual ConstVecLane32 325 readVec32BitLaneReg(const RegId& reg) const 326 { return readVecLane<uint32_t>(reg); } 327 328 /** Reads source vector 64bit operand. */ 329 virtual ConstVecLane64 330 readVec64BitLaneReg(const RegId& reg) const 331 { return readVecLane<uint64_t>(reg); } 332 333 /** Write a lane of the destination vector register. */ 334 template <typename LD> 335 void setVecLaneT(const RegId& reg, const LD& val) 336 { 337 int flatIndex = isa->flattenVecIndex(reg.index()); 338 assert(flatIndex < TheISA::NumVecRegs); 339 setVecLaneFlat(flatIndex, reg.elemIndex(), val); 340 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n", 341 reg.index(), flatIndex, reg.elemIndex(), val); 342 } 343 virtual void setVecLane(const RegId& reg, 344 const LaneData<LaneSize::Byte>& val) 345 { return setVecLaneT(reg, val); } 346 virtual void setVecLane(const RegId& reg, 347 const LaneData<LaneSize::TwoByte>& val) 348 { return setVecLaneT(reg, val); } 349 virtual void setVecLane(const RegId& reg, 350 const LaneData<LaneSize::FourByte>& val) 351 { return setVecLaneT(reg, val); } 352 virtual void setVecLane(const RegId& reg, 353 const LaneData<LaneSize::EightByte>& val) 354 { return setVecLaneT(reg, val); } 355 /** @} */ 356 357 const VecElem& readVecElem(const RegId& reg) const 358 { 359 int flatIndex = isa->flattenVecElemIndex(reg.index()); 360 assert(flatIndex < TheISA::NumVecRegs); 361 const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex()); 362 DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as" 363 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal); 364 return regVal; 365 } 366 367 368 CCReg readCCReg(int reg_idx) 369 { 370#ifdef ISA_HAS_CC_REGS 371 int flatIndex = isa->flattenCCIndex(reg_idx); 372 assert(0 <= flatIndex); 373 assert(flatIndex < TheISA::NumCCRegs); 374 uint64_t regVal(readCCRegFlat(flatIndex)); 375 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 376 reg_idx, flatIndex, regVal); 377 return regVal; 378#else 379 panic("Tried to read a CC register."); 380 return 0; 381#endif 382 } 383 384 void setIntReg(int reg_idx, uint64_t val) 385 { 386 int flatIndex = isa->flattenIntIndex(reg_idx); 387 assert(flatIndex < TheISA::NumIntRegs); 388 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 389 reg_idx, flatIndex, val); 390 setIntRegFlat(flatIndex, val); 391 } 392 393 void setFloatReg(int reg_idx, FloatReg val) 394 { 395 int flatIndex = isa->flattenFloatIndex(reg_idx); 396 assert(flatIndex < TheISA::NumFloatRegs); 397 setFloatRegFlat(flatIndex, val); 398 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 399 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 400 } 401 402 void setFloatRegBits(int reg_idx, FloatRegBits val) 403 { 404 int flatIndex = isa->flattenFloatIndex(reg_idx); 405 assert(flatIndex < TheISA::NumFloatRegs); 406 // XXX: Fix array out of bounds compiler error for gem5.fast 407 // when checkercpu enabled 408 if (flatIndex < TheISA::NumFloatRegs) 409 setFloatRegBitsFlat(flatIndex, val); 410 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 411 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 412 } 413 414 void setVecReg(const RegId& reg, const VecRegContainer& val) 415 { 416 int flatIndex = isa->flattenVecIndex(reg.index()); 417 assert(flatIndex < TheISA::NumVecRegs); 418 setVecRegFlat(flatIndex, val); 419 DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n", 420 reg.index(), flatIndex, val.print()); 421 } 422 423 void setVecElem(const RegId& reg, const VecElem& val) 424 { 425 int flatIndex = isa->flattenVecElemIndex(reg.index()); 426 assert(flatIndex < TheISA::NumVecRegs); 427 setVecElemFlat(flatIndex, reg.elemIndex(), val); 428 DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 429 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 430 } 431 432 void setCCReg(int reg_idx, CCReg val) 433 { 434#ifdef ISA_HAS_CC_REGS 435 int flatIndex = isa->flattenCCIndex(reg_idx); 436 assert(flatIndex < TheISA::NumCCRegs); 437 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 438 reg_idx, flatIndex, val); 439 setCCRegFlat(flatIndex, val); 440#else 441 panic("Tried to set a CC register."); 442#endif 443 } 444 445 TheISA::PCState 446 pcState() 447 { 448 return _pcState; 449 } 450 451 void 452 pcState(const TheISA::PCState &val) 453 { 454 _pcState = val; 455 } 456 457 void 458 pcStateNoRecord(const TheISA::PCState &val) 459 { 460 _pcState = val; 461 } 462 463 Addr 464 instAddr() 465 { 466 return _pcState.instAddr(); 467 } 468 469 Addr 470 nextInstAddr() 471 { 472 return _pcState.nextInstAddr(); 473 } 474 475 void 476 setNPC(Addr val) 477 { 478 _pcState.setNPC(val); 479 } 480 481 MicroPC 482 microPC() 483 { 484 return _pcState.microPC(); 485 } 486 487 bool readPredicate() 488 { 489 return predicate; 490 } 491 492 void setPredicate(bool val) 493 { 494 predicate = val; 495 } 496 497 MiscReg 498 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const 499 { 500 return isa->readMiscRegNoEffect(misc_reg); 501 } 502 503 MiscReg 504 readMiscReg(int misc_reg, ThreadID tid = 0) 505 { 506 return isa->readMiscReg(misc_reg, tc); 507 } 508 509 void 510 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 511 { 512 return isa->setMiscRegNoEffect(misc_reg, val); 513 } 514 515 void 516 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 517 { 518 return isa->setMiscReg(misc_reg, val, tc); 519 } 520 521 RegId 522 flattenRegId(const RegId& regId) const 523 { 524 return isa->flattenRegId(regId); 525 } 526 527 unsigned readStCondFailures() { return storeCondFailures; } 528 529 void setStCondFailures(unsigned sc_failures) 530 { storeCondFailures = sc_failures; } 531 532 void syscall(int64_t callnum, Fault *fault) 533 { 534 process->syscall(callnum, tc, fault); 535 } 536 537 uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } 538 void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } 539 540 FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; } 541 void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; } 542 543 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; } 544 void setFloatRegBitsFlat(int idx, FloatRegBits val) { 545 floatRegs.i[idx] = val; 546 } 547 548 const VecRegContainer& readVecRegFlat(const RegIndex& reg) const 549 { 550 return vecRegs[reg]; 551 } 552 553 VecRegContainer& getWritableVecRegFlat(const RegIndex& reg) 554 { 555 return vecRegs[reg]; 556 } 557 558 void setVecRegFlat(const RegIndex& reg, const VecRegContainer& val) 559 { 560 vecRegs[reg] = val; 561 } 562 563 template <typename T> 564 VecLaneT<T, true> readVecLaneFlat(const RegIndex& reg, int lId) const 565 { 566 return vecRegs[reg].laneView<T>(lId); 567 } 568 569 template <typename LD> 570 void setVecLaneFlat(const RegIndex& reg, int lId, const LD& val) 571 { 572 vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; 573 } 574 575 const VecElem& readVecElemFlat(const RegIndex& reg, 576 const ElemIndex& elemIndex) const 577 { 578 return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; 579 } 580 581 void setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex, 582 const VecElem val) 583 { 584 vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 585 } 586 587#ifdef ISA_HAS_CC_REGS 588 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 589 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 590#else 591 CCReg readCCRegFlat(int idx) 592 { panic("readCCRegFlat w/no CC regs!\n"); } 593 594 void setCCRegFlat(int idx, CCReg val) 595 { panic("setCCRegFlat w/no CC regs!\n"); } 596#endif 597}; 598 599 600#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 601