simple_thread.hh revision 10338:8bee5f4edb92
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2001-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 */ 44 45#ifndef __CPU_SIMPLE_THREAD_HH__ 46#define __CPU_SIMPLE_THREAD_HH__ 47 48#include "arch/decoder.hh" 49#include "arch/isa.hh" 50#include "arch/isa_traits.hh" 51#include "arch/registers.hh" 52#include "arch/tlb.hh" 53#include "arch/types.hh" 54#include "base/types.hh" 55#include "config/the_isa.hh" 56#include "cpu/thread_context.hh" 57#include "cpu/thread_state.hh" 58#include "debug/CCRegs.hh" 59#include "debug/FloatRegs.hh" 60#include "debug/IntRegs.hh" 61#include "mem/page_table.hh" 62#include "mem/request.hh" 63#include "sim/byteswap.hh" 64#include "sim/eventq.hh" 65#include "sim/process.hh" 66#include "sim/serialize.hh" 67#include "sim/system.hh" 68 69class BaseCPU; 70class CheckerCPU; 71 72class FunctionProfile; 73class ProfileNode; 74 75namespace TheISA { 76 namespace Kernel { 77 class Statistics; 78 } 79} 80 81/** 82 * The SimpleThread object provides a combination of the ThreadState 83 * object and the ThreadContext interface. It implements the 84 * ThreadContext interface so that a ProxyThreadContext class can be 85 * made using SimpleThread as the template parameter (see 86 * thread_context.hh). It adds to the ThreadState object by adding all 87 * the objects needed for simple functional execution, including a 88 * simple architectural register file, and pointers to the ITB and DTB 89 * in full system mode. For CPU models that do not need more advanced 90 * ways to hold state (i.e. a separate physical register file, or 91 * separate fetch and commit PC's), this SimpleThread class provides 92 * all the necessary state for full architecture-level functional 93 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 94 * examples. 95 */ 96 97class SimpleThread : public ThreadState 98{ 99 protected: 100 typedef TheISA::MachInst MachInst; 101 typedef TheISA::MiscReg MiscReg; 102 typedef TheISA::FloatReg FloatReg; 103 typedef TheISA::FloatRegBits FloatRegBits; 104 typedef TheISA::CCReg CCReg; 105 public: 106 typedef ThreadContext::Status Status; 107 108 protected: 109 union { 110 FloatReg f[TheISA::NumFloatRegs]; 111 FloatRegBits i[TheISA::NumFloatRegs]; 112 } floatRegs; 113 TheISA::IntReg intRegs[TheISA::NumIntRegs]; 114#ifdef ISA_HAS_CC_REGS 115 TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 116#endif 117 TheISA::ISA *const isa; // one "instance" of the current ISA. 118 119 TheISA::PCState _pcState; 120 121 /** Did this instruction execute or is it predicated false */ 122 bool predicate; 123 124 public: 125 std::string name() const 126 { 127 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 128 } 129 130 ProxyThreadContext<SimpleThread> *tc; 131 132 System *system; 133 134 TheISA::TLB *itb; 135 TheISA::TLB *dtb; 136 137 TheISA::Decoder decoder; 138 139 // constructor: initialize SimpleThread from given process structure 140 // FS 141 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 142 TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa, 143 bool use_kernel_stats = true); 144 // SE 145 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 146 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb, 147 TheISA::ISA *_isa); 148 149 virtual ~SimpleThread(); 150 151 virtual void takeOverFrom(ThreadContext *oldContext); 152 153 void regStats(const std::string &name); 154 155 void copyState(ThreadContext *oldContext); 156 157 void serialize(std::ostream &os); 158 void unserialize(Checkpoint *cp, const std::string §ion); 159 void startup(); 160 161 /*************************************************************** 162 * SimpleThread functions to provide CPU with access to various 163 * state. 164 **************************************************************/ 165 166 /** Returns the pointer to this SimpleThread's ThreadContext. Used 167 * when a ThreadContext must be passed to objects outside of the 168 * CPU. 169 */ 170 ThreadContext *getTC() { return tc; } 171 172 void demapPage(Addr vaddr, uint64_t asn) 173 { 174 itb->demapPage(vaddr, asn); 175 dtb->demapPage(vaddr, asn); 176 } 177 178 void demapInstPage(Addr vaddr, uint64_t asn) 179 { 180 itb->demapPage(vaddr, asn); 181 } 182 183 void demapDataPage(Addr vaddr, uint64_t asn) 184 { 185 dtb->demapPage(vaddr, asn); 186 } 187 188 void dumpFuncProfile(); 189 190 Fault hwrei(); 191 192 bool simPalCheck(int palFunc); 193 194 /******************************************* 195 * ThreadContext interface functions. 196 ******************************************/ 197 198 BaseCPU *getCpuPtr() { return baseCpu; } 199 200 TheISA::TLB *getITBPtr() { return itb; } 201 202 TheISA::TLB *getDTBPtr() { return dtb; } 203 204 CheckerCPU *getCheckerCpuPtr() { return NULL; } 205 206 TheISA::Decoder *getDecoderPtr() { return &decoder; } 207 208 System *getSystemPtr() { return system; } 209 210 Status status() const { return _status; } 211 212 void setStatus(Status newStatus) { _status = newStatus; } 213 214 /// Set the status to Active. Optional delay indicates number of 215 /// cycles to wait before beginning execution. 216 void activate(Cycles delay = Cycles(1)); 217 218 /// Set the status to Suspended. 219 void suspend(); 220 221 /// Set the status to Halted. 222 void halt(); 223 224 virtual bool misspeculating(); 225 226 void copyArchRegs(ThreadContext *tc); 227 228 void clearArchRegs() 229 { 230 _pcState = 0; 231 memset(intRegs, 0, sizeof(intRegs)); 232 memset(floatRegs.i, 0, sizeof(floatRegs.i)); 233#ifdef ISA_HAS_CC_REGS 234 memset(ccRegs, 0, sizeof(ccRegs)); 235#endif 236 isa->clear(); 237 } 238 239 // 240 // New accessors for new decoder. 241 // 242 uint64_t readIntReg(int reg_idx) 243 { 244 int flatIndex = isa->flattenIntIndex(reg_idx); 245 assert(flatIndex < TheISA::NumIntRegs); 246 uint64_t regVal(readIntRegFlat(flatIndex)); 247 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 248 reg_idx, flatIndex, regVal); 249 return regVal; 250 } 251 252 FloatReg readFloatReg(int reg_idx) 253 { 254 int flatIndex = isa->flattenFloatIndex(reg_idx); 255 assert(flatIndex < TheISA::NumFloatRegs); 256 FloatReg regVal(readFloatRegFlat(flatIndex)); 257 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 258 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 259 return regVal; 260 } 261 262 FloatRegBits readFloatRegBits(int reg_idx) 263 { 264 int flatIndex = isa->flattenFloatIndex(reg_idx); 265 assert(flatIndex < TheISA::NumFloatRegs); 266 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); 267 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 268 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 269 return regVal; 270 } 271 272 CCReg readCCReg(int reg_idx) 273 { 274#ifdef ISA_HAS_CC_REGS 275 int flatIndex = isa->flattenCCIndex(reg_idx); 276 assert(0 <= flatIndex); 277 assert(flatIndex < TheISA::NumCCRegs); 278 uint64_t regVal(readCCRegFlat(flatIndex)); 279 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 280 reg_idx, flatIndex, regVal); 281 return regVal; 282#else 283 panic("Tried to read a CC register."); 284 return 0; 285#endif 286 } 287 288 void setIntReg(int reg_idx, uint64_t val) 289 { 290 int flatIndex = isa->flattenIntIndex(reg_idx); 291 assert(flatIndex < TheISA::NumIntRegs); 292 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 293 reg_idx, flatIndex, val); 294 setIntRegFlat(flatIndex, val); 295 } 296 297 void setFloatReg(int reg_idx, FloatReg val) 298 { 299 int flatIndex = isa->flattenFloatIndex(reg_idx); 300 assert(flatIndex < TheISA::NumFloatRegs); 301 setFloatRegFlat(flatIndex, val); 302 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 303 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 304 } 305 306 void setFloatRegBits(int reg_idx, FloatRegBits val) 307 { 308 int flatIndex = isa->flattenFloatIndex(reg_idx); 309 assert(flatIndex < TheISA::NumFloatRegs); 310 // XXX: Fix array out of bounds compiler error for gem5.fast 311 // when checkercpu enabled 312 if (flatIndex < TheISA::NumFloatRegs) 313 setFloatRegBitsFlat(flatIndex, val); 314 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 315 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 316 } 317 318 void setCCReg(int reg_idx, CCReg val) 319 { 320#ifdef ISA_HAS_CC_REGS 321 int flatIndex = isa->flattenCCIndex(reg_idx); 322 assert(flatIndex < TheISA::NumCCRegs); 323 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 324 reg_idx, flatIndex, val); 325 setCCRegFlat(flatIndex, val); 326#else 327 panic("Tried to set a CC register."); 328#endif 329 } 330 331 TheISA::PCState 332 pcState() 333 { 334 return _pcState; 335 } 336 337 void 338 pcState(const TheISA::PCState &val) 339 { 340 _pcState = val; 341 } 342 343 void 344 pcStateNoRecord(const TheISA::PCState &val) 345 { 346 _pcState = val; 347 } 348 349 Addr 350 instAddr() 351 { 352 return _pcState.instAddr(); 353 } 354 355 Addr 356 nextInstAddr() 357 { 358 return _pcState.nextInstAddr(); 359 } 360 361 MicroPC 362 microPC() 363 { 364 return _pcState.microPC(); 365 } 366 367 bool readPredicate() 368 { 369 return predicate; 370 } 371 372 void setPredicate(bool val) 373 { 374 predicate = val; 375 } 376 377 MiscReg 378 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 379 { 380 return isa->readMiscRegNoEffect(misc_reg); 381 } 382 383 MiscReg 384 readMiscReg(int misc_reg, ThreadID tid = 0) 385 { 386 return isa->readMiscReg(misc_reg, tc); 387 } 388 389 void 390 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 391 { 392 return isa->setMiscRegNoEffect(misc_reg, val); 393 } 394 395 void 396 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 397 { 398 return isa->setMiscReg(misc_reg, val, tc); 399 } 400 401 int 402 flattenIntIndex(int reg) 403 { 404 return isa->flattenIntIndex(reg); 405 } 406 407 int 408 flattenFloatIndex(int reg) 409 { 410 return isa->flattenFloatIndex(reg); 411 } 412 413 int 414 flattenCCIndex(int reg) 415 { 416 return isa->flattenCCIndex(reg); 417 } 418 419 int 420 flattenMiscIndex(int reg) 421 { 422 return isa->flattenMiscIndex(reg); 423 } 424 425 unsigned readStCondFailures() { return storeCondFailures; } 426 427 void setStCondFailures(unsigned sc_failures) 428 { storeCondFailures = sc_failures; } 429 430 void syscall(int64_t callnum) 431 { 432 process->syscall(callnum, tc); 433 } 434 435 uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } 436 void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } 437 438 FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; } 439 void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; } 440 441 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; } 442 void setFloatRegBitsFlat(int idx, FloatRegBits val) { 443 floatRegs.i[idx] = val; 444 } 445 446#ifdef ISA_HAS_CC_REGS 447 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 448 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 449#else 450 CCReg readCCRegFlat(int idx) 451 { panic("readCCRegFlat w/no CC regs!\n"); } 452 453 void setCCRegFlat(int idx, CCReg val) 454 { panic("setCCRegFlat w/no CC regs!\n"); } 455#endif 456}; 457 458 459// for non-speculative execution context, spec_mode is always false 460inline bool 461SimpleThread::misspeculating() 462{ 463 return false; 464} 465 466#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 467