simple_thread.hh revision 9461
12SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 142188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Steve Reinhardt 412665SN/A * Nathan Binkert 422SN/A */ 432SN/A 442683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 452683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 462SN/A 479020Sgblack@eecs.umich.edu#include "arch/decoder.hh" 486313Sgblack@eecs.umich.edu#include "arch/isa.hh" 492190SN/A#include "arch/isa_traits.hh" 506329Sgblack@eecs.umich.edu#include "arch/registers.hh" 514997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 526316Sgblack@eecs.umich.edu#include "arch/types.hh" 536216Snate@binkert.org#include "base/types.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 552680SN/A#include "cpu/thread_context.hh" 562683Sktlim@umich.edu#include "cpu/thread_state.hh" 578232Snate@binkert.org#include "debug/FloatRegs.hh" 588232Snate@binkert.org#include "debug/IntRegs.hh" 598777Sgblack@eecs.umich.edu#include "mem/page_table.hh" 602395SN/A#include "mem/request.hh" 612190SN/A#include "sim/byteswap.hh" 622188SN/A#include "sim/eventq.hh" 638777Sgblack@eecs.umich.edu#include "sim/process.hh" 64217SN/A#include "sim/serialize.hh" 658777Sgblack@eecs.umich.edu#include "sim/system.hh" 662SN/A 672SN/Aclass BaseCPU; 688887Sgeoffrey.blake@arm.comclass CheckerCPU; 691070SN/A 701917SN/Aclass FunctionProfile; 711917SN/Aclass ProfileNode; 722521SN/A 733548Sgblack@eecs.umich.edunamespace TheISA { 743548Sgblack@eecs.umich.edu namespace Kernel { 753548Sgblack@eecs.umich.edu class Statistics; 768902Sandreas.hansson@arm.com } 778902Sandreas.hansson@arm.com} 782330SN/A 792683Sktlim@umich.edu/** 802683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 812683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 822683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 832683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 842683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 852683Sktlim@umich.edu * the objects needed for simple functional execution, including a 862683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 872683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 882683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 892683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 902683Sktlim@umich.edu * all the necessary state for full architecture-level functional 912683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 922683Sktlim@umich.edu * examples. 932683Sktlim@umich.edu */ 942SN/A 952683Sktlim@umich.educlass SimpleThread : public ThreadState 962SN/A{ 972107SN/A protected: 982107SN/A typedef TheISA::MachInst MachInst; 992159SN/A typedef TheISA::MiscReg MiscReg; 1002455SN/A typedef TheISA::FloatReg FloatReg; 1012455SN/A typedef TheISA::FloatRegBits FloatRegBits; 1022SN/A public: 1032680SN/A typedef ThreadContext::Status Status; 1042SN/A 1052190SN/A protected: 1066315Sgblack@eecs.umich.edu union { 1076315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1086315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1096315Sgblack@eecs.umich.edu } floatRegs; 1106316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 1119384SAndreas.Sandberg@arm.com TheISA::ISA *const isa; // one "instance" of the current ISA. 1122SN/A 1137720Sgblack@eecs.umich.edu TheISA::PCState _pcState; 1146324Sgblack@eecs.umich.edu 1157597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1167597Sminkyu.jeong@arm.com bool predicate; 1177597Sminkyu.jeong@arm.com 1182190SN/A public: 1198357Sksewell@umich.edu std::string name() const 1208357Sksewell@umich.edu { 1218735Sandreas.hanson@arm.com return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 1228357Sksewell@umich.edu } 1238357Sksewell@umich.edu 1242683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1252188SN/A 1262378SN/A System *system; 1272400SN/A 1286022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1296022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1302SN/A 1319020Sgblack@eecs.umich.edu TheISA::Decoder decoder; 1328541Sgblack@eecs.umich.edu 1332683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1348793Sgblack@eecs.umich.edu // FS 1352683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1369384SAndreas.Sandberg@arm.com TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa, 1372683Sktlim@umich.edu bool use_kernel_stats = true); 1388793Sgblack@eecs.umich.edu // SE 1398820Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1409384SAndreas.Sandberg@arm.com Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb, 1419384SAndreas.Sandberg@arm.com TheISA::ISA *_isa); 1422862Sktlim@umich.edu 1432683Sktlim@umich.edu virtual ~SimpleThread(); 1442SN/A 1452680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 146180SN/A 1472SN/A void regStats(const std::string &name); 1482SN/A 1492862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1502862Sktlim@umich.edu 151217SN/A void serialize(std::ostream &os); 152237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 1539461Snilay@cs.wisc.edu void startup(); 154217SN/A 1552683Sktlim@umich.edu /*************************************************************** 1562683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1575891Sgblack@eecs.umich.edu * state. 1582683Sktlim@umich.edu **************************************************************/ 1592190SN/A 1602683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1612683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1622683Sktlim@umich.edu * CPU. 1632683Sktlim@umich.edu */ 1642680SN/A ThreadContext *getTC() { return tc; } 1652190SN/A 1665358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1675358Sgblack@eecs.umich.edu { 1685358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1695358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1705358Sgblack@eecs.umich.edu } 1715358Sgblack@eecs.umich.edu 1725358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1735358Sgblack@eecs.umich.edu { 1745358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1755358Sgblack@eecs.umich.edu } 1765358Sgblack@eecs.umich.edu 1775358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1785358Sgblack@eecs.umich.edu { 1795358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1805358Sgblack@eecs.umich.edu } 1815358Sgblack@eecs.umich.edu 1822683Sktlim@umich.edu void dumpFuncProfile(); 1832521SN/A 1845702Ssaidi@eecs.umich.edu Fault hwrei(); 1855702Ssaidi@eecs.umich.edu 1865702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1875702Ssaidi@eecs.umich.edu 1882683Sktlim@umich.edu /******************************************* 1892683Sktlim@umich.edu * ThreadContext interface functions. 1902683Sktlim@umich.edu ******************************************/ 1912683Sktlim@umich.edu 1928735Sandreas.hanson@arm.com BaseCPU *getCpuPtr() { return baseCpu; } 1932683Sktlim@umich.edu 1946022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 1952683Sktlim@umich.edu 1966022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 1972683Sktlim@umich.edu 1988887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return NULL; } 1998733Sgeoffrey.blake@arm.com 2009020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return &decoder; } 2018541Sgblack@eecs.umich.edu 2024997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2034997Sgblack@eecs.umich.edu 2042683Sktlim@umich.edu Status status() const { return _status; } 2052683Sktlim@umich.edu 2062683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2072683Sktlim@umich.edu 2082683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2092683Sktlim@umich.edu /// cycles to wait before beginning execution. 2109180Sandreas.hansson@arm.com void activate(Cycles delay = Cycles(1)); 2112683Sktlim@umich.edu 2122683Sktlim@umich.edu /// Set the status to Suspended. 2132683Sktlim@umich.edu void suspend(); 2142683Sktlim@umich.edu 2152683Sktlim@umich.edu /// Set the status to Halted. 2162683Sktlim@umich.edu void halt(); 2172683Sktlim@umich.edu 2182SN/A virtual bool misspeculating(); 2192SN/A 2202683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2212190SN/A 2226315Sgblack@eecs.umich.edu void clearArchRegs() 2236315Sgblack@eecs.umich.edu { 2247720Sgblack@eecs.umich.edu _pcState = 0; 2256316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 2266315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2279384SAndreas.Sandberg@arm.com isa->clear(); 2286315Sgblack@eecs.umich.edu } 2292190SN/A 2302SN/A // 2312SN/A // New accessors for new decoder. 2322SN/A // 2332SN/A uint64_t readIntReg(int reg_idx) 2342SN/A { 2359384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 2366323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2379426SAndreas.Sandberg@ARM.com uint64_t regVal(readIntRegFlat(flatIndex)); 2387601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2397601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 2406418Sgblack@eecs.umich.edu return regVal; 2412SN/A } 2422SN/A 2432455SN/A FloatReg readFloatReg(int reg_idx) 2442SN/A { 2459384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 2466323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2479426SAndreas.Sandberg@ARM.com FloatReg regVal(readFloatRegFlat(flatIndex)); 2487601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 2497601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 2507341Sgblack@eecs.umich.edu return regVal; 2512SN/A } 2522SN/A 2532455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2542455SN/A { 2559384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 2566323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2579426SAndreas.Sandberg@ARM.com FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); 2587601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 2597601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 2607341Sgblack@eecs.umich.edu return regVal; 2612SN/A } 2622SN/A 2632SN/A void setIntReg(int reg_idx, uint64_t val) 2642SN/A { 2659384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 2666323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2677601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 2687601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 2699426SAndreas.Sandberg@ARM.com setIntRegFlat(flatIndex, val); 2702SN/A } 2712SN/A 2722455SN/A void setFloatReg(int reg_idx, FloatReg val) 2732SN/A { 2749384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 2756323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2769426SAndreas.Sandberg@ARM.com setFloatRegFlat(flatIndex, val); 2777601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 2787601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 2792SN/A } 2802SN/A 2812455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2822455SN/A { 2839384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 2846323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2858733Sgeoffrey.blake@arm.com // XXX: Fix array out of bounds compiler error for gem5.fast 2868733Sgeoffrey.blake@arm.com // when checkercpu enabled 2878733Sgeoffrey.blake@arm.com if (flatIndex < TheISA::NumFloatRegs) 2889426SAndreas.Sandberg@ARM.com setFloatRegBitsFlat(flatIndex, val); 2897601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 2907601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 2912SN/A } 2922SN/A 2937720Sgblack@eecs.umich.edu TheISA::PCState 2947720Sgblack@eecs.umich.edu pcState() 2952SN/A { 2967720Sgblack@eecs.umich.edu return _pcState; 2972SN/A } 2982SN/A 2997720Sgblack@eecs.umich.edu void 3007720Sgblack@eecs.umich.edu pcState(const TheISA::PCState &val) 3012190SN/A { 3027720Sgblack@eecs.umich.edu _pcState = val; 3032190SN/A } 3042190SN/A 3058733Sgeoffrey.blake@arm.com void 3068733Sgeoffrey.blake@arm.com pcStateNoRecord(const TheISA::PCState &val) 3078733Sgeoffrey.blake@arm.com { 3088733Sgeoffrey.blake@arm.com _pcState = val; 3098733Sgeoffrey.blake@arm.com } 3108733Sgeoffrey.blake@arm.com 3117720Sgblack@eecs.umich.edu Addr 3127720Sgblack@eecs.umich.edu instAddr() 3133276Sgblack@eecs.umich.edu { 3147720Sgblack@eecs.umich.edu return _pcState.instAddr(); 3153276Sgblack@eecs.umich.edu } 3163276Sgblack@eecs.umich.edu 3177720Sgblack@eecs.umich.edu Addr 3187720Sgblack@eecs.umich.edu nextInstAddr() 3193276Sgblack@eecs.umich.edu { 3207720Sgblack@eecs.umich.edu return _pcState.nextInstAddr(); 3213276Sgblack@eecs.umich.edu } 3223276Sgblack@eecs.umich.edu 3237720Sgblack@eecs.umich.edu MicroPC 3247720Sgblack@eecs.umich.edu microPC() 3252190SN/A { 3267720Sgblack@eecs.umich.edu return _pcState.microPC(); 3272251SN/A } 3282251SN/A 3297597Sminkyu.jeong@arm.com bool readPredicate() 3307597Sminkyu.jeong@arm.com { 3317597Sminkyu.jeong@arm.com return predicate; 3327597Sminkyu.jeong@arm.com } 3337597Sminkyu.jeong@arm.com 3347597Sminkyu.jeong@arm.com void setPredicate(bool val) 3357597Sminkyu.jeong@arm.com { 3367597Sminkyu.jeong@arm.com predicate = val; 3377597Sminkyu.jeong@arm.com } 3387597Sminkyu.jeong@arm.com 3396221Snate@binkert.org MiscReg 3406221Snate@binkert.org readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 3414172Ssaidi@eecs.umich.edu { 3429384SAndreas.Sandberg@arm.com return isa->readMiscRegNoEffect(misc_reg); 3434172Ssaidi@eecs.umich.edu } 3444172Ssaidi@eecs.umich.edu 3456221Snate@binkert.org MiscReg 3466221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 3472SN/A { 3489384SAndreas.Sandberg@arm.com return isa->readMiscReg(misc_reg, tc); 3492SN/A } 3502SN/A 3516221Snate@binkert.org void 3526221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3532SN/A { 3549384SAndreas.Sandberg@arm.com return isa->setMiscRegNoEffect(misc_reg, val); 3552SN/A } 3562SN/A 3576221Snate@binkert.org void 3586221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3592SN/A { 3609384SAndreas.Sandberg@arm.com return isa->setMiscReg(misc_reg, val, tc); 3616313Sgblack@eecs.umich.edu } 3626313Sgblack@eecs.umich.edu 3636313Sgblack@eecs.umich.edu int 3646313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 3656313Sgblack@eecs.umich.edu { 3669384SAndreas.Sandberg@arm.com return isa->flattenIntIndex(reg); 3676313Sgblack@eecs.umich.edu } 3686313Sgblack@eecs.umich.edu 3696313Sgblack@eecs.umich.edu int 3706313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 3716313Sgblack@eecs.umich.edu { 3729384SAndreas.Sandberg@arm.com return isa->flattenFloatIndex(reg); 3732SN/A } 3742SN/A 3752190SN/A unsigned readStCondFailures() { return storeCondFailures; } 3762190SN/A 3772190SN/A void setStCondFailures(unsigned sc_failures) 3782190SN/A { storeCondFailures = sc_failures; } 3792190SN/A 3802561SN/A void syscall(int64_t callnum) 3812SN/A { 3822680SN/A process->syscall(callnum, tc); 3832SN/A } 3849426SAndreas.Sandberg@ARM.com 3859426SAndreas.Sandberg@ARM.com uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } 3869426SAndreas.Sandberg@ARM.com void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } 3879426SAndreas.Sandberg@ARM.com 3889426SAndreas.Sandberg@ARM.com FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; } 3899426SAndreas.Sandberg@ARM.com void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; } 3909426SAndreas.Sandberg@ARM.com 3919426SAndreas.Sandberg@ARM.com FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; } 3929426SAndreas.Sandberg@ARM.com void setFloatRegBitsFlat(int idx, FloatRegBits val) { 3939426SAndreas.Sandberg@ARM.com floatRegs.i[idx] = val; 3949426SAndreas.Sandberg@ARM.com } 3959426SAndreas.Sandberg@ARM.com 3962SN/A}; 3972SN/A 3982SN/A 3992SN/A// for non-speculative execution context, spec_mode is always false 4002SN/Ainline bool 4012683Sktlim@umich.eduSimpleThread::misspeculating() 4022SN/A{ 4032SN/A return false; 4042SN/A} 4052SN/A 4062190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 407