simple_thread.hh revision 9020
12SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 142188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Steve Reinhardt 412665SN/A * Nathan Binkert 422SN/A */ 432SN/A 442683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 452683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 462SN/A 479020Sgblack@eecs.umich.edu#include "arch/decoder.hh" 486313Sgblack@eecs.umich.edu#include "arch/isa.hh" 492190SN/A#include "arch/isa_traits.hh" 506329Sgblack@eecs.umich.edu#include "arch/registers.hh" 514997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 526316Sgblack@eecs.umich.edu#include "arch/types.hh" 536216Snate@binkert.org#include "base/types.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 552680SN/A#include "cpu/thread_context.hh" 562683Sktlim@umich.edu#include "cpu/thread_state.hh" 578232Snate@binkert.org#include "debug/FloatRegs.hh" 588232Snate@binkert.org#include "debug/IntRegs.hh" 598777Sgblack@eecs.umich.edu#include "mem/page_table.hh" 602395SN/A#include "mem/request.hh" 612190SN/A#include "sim/byteswap.hh" 622188SN/A#include "sim/eventq.hh" 638777Sgblack@eecs.umich.edu#include "sim/process.hh" 64217SN/A#include "sim/serialize.hh" 658777Sgblack@eecs.umich.edu#include "sim/system.hh" 662SN/A 672SN/Aclass BaseCPU; 688887Sgeoffrey.blake@arm.comclass CheckerCPU; 691070SN/A 701917SN/Aclass FunctionProfile; 711917SN/Aclass ProfileNode; 722521SN/A 733548Sgblack@eecs.umich.edunamespace TheISA { 743548Sgblack@eecs.umich.edu namespace Kernel { 753548Sgblack@eecs.umich.edu class Statistics; 768902Sandreas.hansson@arm.com } 778902Sandreas.hansson@arm.com} 782330SN/A 792683Sktlim@umich.edu/** 802683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 812683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 822683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 832683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 842683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 852683Sktlim@umich.edu * the objects needed for simple functional execution, including a 862683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 872683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 882683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 892683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 902683Sktlim@umich.edu * all the necessary state for full architecture-level functional 912683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 922683Sktlim@umich.edu * examples. 932683Sktlim@umich.edu */ 942SN/A 952683Sktlim@umich.educlass SimpleThread : public ThreadState 962SN/A{ 972107SN/A protected: 982107SN/A typedef TheISA::MachInst MachInst; 992159SN/A typedef TheISA::MiscReg MiscReg; 1002455SN/A typedef TheISA::FloatReg FloatReg; 1012455SN/A typedef TheISA::FloatRegBits FloatRegBits; 1022SN/A public: 1032680SN/A typedef ThreadContext::Status Status; 1042SN/A 1052190SN/A protected: 1066315Sgblack@eecs.umich.edu union { 1076315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1086315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1096315Sgblack@eecs.umich.edu } floatRegs; 1106316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 1116313Sgblack@eecs.umich.edu TheISA::ISA isa; // one "instance" of the current ISA. 1122SN/A 1137720Sgblack@eecs.umich.edu TheISA::PCState _pcState; 1146324Sgblack@eecs.umich.edu 1157597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1167597Sminkyu.jeong@arm.com bool predicate; 1177597Sminkyu.jeong@arm.com 1182190SN/A public: 1198357Sksewell@umich.edu std::string name() const 1208357Sksewell@umich.edu { 1218735Sandreas.hanson@arm.com return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 1228357Sksewell@umich.edu } 1238357Sksewell@umich.edu 1242683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1252188SN/A 1262378SN/A System *system; 1272400SN/A 1286022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1296022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1302SN/A 1319020Sgblack@eecs.umich.edu TheISA::Decoder decoder; 1328541Sgblack@eecs.umich.edu 1332683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1348793Sgblack@eecs.umich.edu // FS 1352683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1366022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 1372683Sktlim@umich.edu bool use_kernel_stats = true); 1388793Sgblack@eecs.umich.edu // SE 1398820Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1408820Sgblack@eecs.umich.edu Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb); 1412862Sktlim@umich.edu 1422864Sktlim@umich.edu SimpleThread(); 1432862Sktlim@umich.edu 1442683Sktlim@umich.edu virtual ~SimpleThread(); 1452SN/A 1462680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 147180SN/A 1482SN/A void regStats(const std::string &name); 1492SN/A 1502864Sktlim@umich.edu void copyTC(ThreadContext *context); 1512864Sktlim@umich.edu 1522862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1532862Sktlim@umich.edu 154217SN/A void serialize(std::ostream &os); 155237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 156217SN/A 1572683Sktlim@umich.edu /*************************************************************** 1582683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1595891Sgblack@eecs.umich.edu * state. 1602683Sktlim@umich.edu **************************************************************/ 1612190SN/A 1622683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1632683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1642683Sktlim@umich.edu * CPU. 1652683Sktlim@umich.edu */ 1662680SN/A ThreadContext *getTC() { return tc; } 1672190SN/A 1685358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1695358Sgblack@eecs.umich.edu { 1705358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1715358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1725358Sgblack@eecs.umich.edu } 1735358Sgblack@eecs.umich.edu 1745358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1755358Sgblack@eecs.umich.edu { 1765358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1775358Sgblack@eecs.umich.edu } 1785358Sgblack@eecs.umich.edu 1795358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1805358Sgblack@eecs.umich.edu { 1815358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1825358Sgblack@eecs.umich.edu } 1835358Sgblack@eecs.umich.edu 1842683Sktlim@umich.edu void dumpFuncProfile(); 1852521SN/A 1865702Ssaidi@eecs.umich.edu Fault hwrei(); 1875702Ssaidi@eecs.umich.edu 1885702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1895702Ssaidi@eecs.umich.edu 1902683Sktlim@umich.edu /******************************************* 1912683Sktlim@umich.edu * ThreadContext interface functions. 1922683Sktlim@umich.edu ******************************************/ 1932683Sktlim@umich.edu 1948735Sandreas.hanson@arm.com BaseCPU *getCpuPtr() { return baseCpu; } 1952683Sktlim@umich.edu 1966022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 1972683Sktlim@umich.edu 1986022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 1992683Sktlim@umich.edu 2008887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return NULL; } 2018733Sgeoffrey.blake@arm.com 2029020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return &decoder; } 2038541Sgblack@eecs.umich.edu 2044997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2054997Sgblack@eecs.umich.edu 2062683Sktlim@umich.edu Status status() const { return _status; } 2072683Sktlim@umich.edu 2082683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2092683Sktlim@umich.edu 2102683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2112683Sktlim@umich.edu /// cycles to wait before beginning execution. 2122683Sktlim@umich.edu void activate(int delay = 1); 2132683Sktlim@umich.edu 2142683Sktlim@umich.edu /// Set the status to Suspended. 2152683Sktlim@umich.edu void suspend(); 2162683Sktlim@umich.edu 2172683Sktlim@umich.edu /// Set the status to Halted. 2182683Sktlim@umich.edu void halt(); 2192683Sktlim@umich.edu 2202SN/A virtual bool misspeculating(); 2212SN/A 2222683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2232190SN/A 2246315Sgblack@eecs.umich.edu void clearArchRegs() 2256315Sgblack@eecs.umich.edu { 2267720Sgblack@eecs.umich.edu _pcState = 0; 2276316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 2286315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2297400SAli.Saidi@ARM.com isa.clear(); 2306315Sgblack@eecs.umich.edu } 2312190SN/A 2322SN/A // 2332SN/A // New accessors for new decoder. 2342SN/A // 2352SN/A uint64_t readIntReg(int reg_idx) 2362SN/A { 2376313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2386323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2396418Sgblack@eecs.umich.edu uint64_t regVal = intRegs[flatIndex]; 2407601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2417601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 2426418Sgblack@eecs.umich.edu return regVal; 2432SN/A } 2442SN/A 2452455SN/A FloatReg readFloatReg(int reg_idx) 2462SN/A { 2476313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2486323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2497341Sgblack@eecs.umich.edu FloatReg regVal = floatRegs.f[flatIndex]; 2507601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 2517601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 2527341Sgblack@eecs.umich.edu return regVal; 2532SN/A } 2542SN/A 2552455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2562455SN/A { 2576313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2586323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2597341Sgblack@eecs.umich.edu FloatRegBits regVal = floatRegs.i[flatIndex]; 2607601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 2617601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 2627341Sgblack@eecs.umich.edu return regVal; 2632SN/A } 2642SN/A 2652SN/A void setIntReg(int reg_idx, uint64_t val) 2662SN/A { 2676313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2686323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2697601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 2707601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 2716316Sgblack@eecs.umich.edu intRegs[flatIndex] = val; 2722SN/A } 2732SN/A 2742455SN/A void setFloatReg(int reg_idx, FloatReg val) 2752SN/A { 2766313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2776323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2786315Sgblack@eecs.umich.edu floatRegs.f[flatIndex] = val; 2797601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 2807601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 2812SN/A } 2822SN/A 2832455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2842455SN/A { 2856313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2866323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2878733Sgeoffrey.blake@arm.com // XXX: Fix array out of bounds compiler error for gem5.fast 2888733Sgeoffrey.blake@arm.com // when checkercpu enabled 2898733Sgeoffrey.blake@arm.com if (flatIndex < TheISA::NumFloatRegs) 2908733Sgeoffrey.blake@arm.com floatRegs.i[flatIndex] = val; 2917601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 2927601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 2932SN/A } 2942SN/A 2957720Sgblack@eecs.umich.edu TheISA::PCState 2967720Sgblack@eecs.umich.edu pcState() 2972SN/A { 2987720Sgblack@eecs.umich.edu return _pcState; 2992SN/A } 3002SN/A 3017720Sgblack@eecs.umich.edu void 3027720Sgblack@eecs.umich.edu pcState(const TheISA::PCState &val) 3032190SN/A { 3047720Sgblack@eecs.umich.edu _pcState = val; 3052190SN/A } 3062190SN/A 3078733Sgeoffrey.blake@arm.com void 3088733Sgeoffrey.blake@arm.com pcStateNoRecord(const TheISA::PCState &val) 3098733Sgeoffrey.blake@arm.com { 3108733Sgeoffrey.blake@arm.com _pcState = val; 3118733Sgeoffrey.blake@arm.com } 3128733Sgeoffrey.blake@arm.com 3137720Sgblack@eecs.umich.edu Addr 3147720Sgblack@eecs.umich.edu instAddr() 3153276Sgblack@eecs.umich.edu { 3167720Sgblack@eecs.umich.edu return _pcState.instAddr(); 3173276Sgblack@eecs.umich.edu } 3183276Sgblack@eecs.umich.edu 3197720Sgblack@eecs.umich.edu Addr 3207720Sgblack@eecs.umich.edu nextInstAddr() 3213276Sgblack@eecs.umich.edu { 3227720Sgblack@eecs.umich.edu return _pcState.nextInstAddr(); 3233276Sgblack@eecs.umich.edu } 3243276Sgblack@eecs.umich.edu 3257720Sgblack@eecs.umich.edu MicroPC 3267720Sgblack@eecs.umich.edu microPC() 3272190SN/A { 3287720Sgblack@eecs.umich.edu return _pcState.microPC(); 3292251SN/A } 3302251SN/A 3317597Sminkyu.jeong@arm.com bool readPredicate() 3327597Sminkyu.jeong@arm.com { 3337597Sminkyu.jeong@arm.com return predicate; 3347597Sminkyu.jeong@arm.com } 3357597Sminkyu.jeong@arm.com 3367597Sminkyu.jeong@arm.com void setPredicate(bool val) 3377597Sminkyu.jeong@arm.com { 3387597Sminkyu.jeong@arm.com predicate = val; 3397597Sminkyu.jeong@arm.com } 3407597Sminkyu.jeong@arm.com 3416221Snate@binkert.org MiscReg 3426221Snate@binkert.org readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 3434172Ssaidi@eecs.umich.edu { 3446313Sgblack@eecs.umich.edu return isa.readMiscRegNoEffect(misc_reg); 3454172Ssaidi@eecs.umich.edu } 3464172Ssaidi@eecs.umich.edu 3476221Snate@binkert.org MiscReg 3486221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 3492SN/A { 3506313Sgblack@eecs.umich.edu return isa.readMiscReg(misc_reg, tc); 3512SN/A } 3522SN/A 3536221Snate@binkert.org void 3546221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3552SN/A { 3566313Sgblack@eecs.umich.edu return isa.setMiscRegNoEffect(misc_reg, val); 3572SN/A } 3582SN/A 3596221Snate@binkert.org void 3606221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3612SN/A { 3626313Sgblack@eecs.umich.edu return isa.setMiscReg(misc_reg, val, tc); 3636313Sgblack@eecs.umich.edu } 3646313Sgblack@eecs.umich.edu 3656313Sgblack@eecs.umich.edu int 3666313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 3676313Sgblack@eecs.umich.edu { 3686313Sgblack@eecs.umich.edu return isa.flattenIntIndex(reg); 3696313Sgblack@eecs.umich.edu } 3706313Sgblack@eecs.umich.edu 3716313Sgblack@eecs.umich.edu int 3726313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 3736313Sgblack@eecs.umich.edu { 3746313Sgblack@eecs.umich.edu return isa.flattenFloatIndex(reg); 3752SN/A } 3762SN/A 3772190SN/A unsigned readStCondFailures() { return storeCondFailures; } 3782190SN/A 3792190SN/A void setStCondFailures(unsigned sc_failures) 3802190SN/A { storeCondFailures = sc_failures; } 3812190SN/A 3822561SN/A void syscall(int64_t callnum) 3832SN/A { 3842680SN/A process->syscall(callnum, tc); 3852SN/A } 3862SN/A}; 3872SN/A 3882SN/A 3892SN/A// for non-speculative execution context, spec_mode is always false 3902SN/Ainline bool 3912683Sktlim@umich.eduSimpleThread::misspeculating() 3922SN/A{ 3932SN/A return false; 3942SN/A} 3952SN/A 3962190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 397