simple_thread.hh revision 8820
12SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 142188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Steve Reinhardt 412665SN/A * Nathan Binkert 422SN/A */ 432SN/A 442683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 452683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 462SN/A 476313Sgblack@eecs.umich.edu#include "arch/isa.hh" 482190SN/A#include "arch/isa_traits.hh" 496329Sgblack@eecs.umich.edu#include "arch/registers.hh" 504997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 516316Sgblack@eecs.umich.edu#include "arch/types.hh" 526216Snate@binkert.org#include "base/types.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 548733Sgeoffrey.blake@arm.com#include "config/use_checker.hh" 558541Sgblack@eecs.umich.edu#include "cpu/decode.hh" 562680SN/A#include "cpu/thread_context.hh" 572683Sktlim@umich.edu#include "cpu/thread_state.hh" 588232Snate@binkert.org#include "debug/FloatRegs.hh" 598232Snate@binkert.org#include "debug/IntRegs.hh" 608777Sgblack@eecs.umich.edu#include "mem/page_table.hh" 612395SN/A#include "mem/request.hh" 622190SN/A#include "sim/byteswap.hh" 632188SN/A#include "sim/eventq.hh" 648777Sgblack@eecs.umich.edu#include "sim/process.hh" 65217SN/A#include "sim/serialize.hh" 668777Sgblack@eecs.umich.edu#include "sim/system.hh" 672SN/A 682SN/Aclass BaseCPU; 692SN/A 701070SN/A 711917SN/Aclass FunctionProfile; 721917SN/Aclass ProfileNode; 732521SN/A 743548Sgblack@eecs.umich.edunamespace TheISA { 753548Sgblack@eecs.umich.edu namespace Kernel { 763548Sgblack@eecs.umich.edu class Statistics; 773548Sgblack@eecs.umich.edu }; 782330SN/A}; 792330SN/A 802683Sktlim@umich.edu/** 812683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 822683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 832683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 842683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 852683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 862683Sktlim@umich.edu * the objects needed for simple functional execution, including a 872683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 882683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 892683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 902683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 912683Sktlim@umich.edu * all the necessary state for full architecture-level functional 922683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 932683Sktlim@umich.edu * examples. 942683Sktlim@umich.edu */ 952SN/A 962683Sktlim@umich.educlass SimpleThread : public ThreadState 972SN/A{ 982107SN/A protected: 992107SN/A typedef TheISA::MachInst MachInst; 1002159SN/A typedef TheISA::MiscReg MiscReg; 1012455SN/A typedef TheISA::FloatReg FloatReg; 1022455SN/A typedef TheISA::FloatRegBits FloatRegBits; 1032SN/A public: 1042680SN/A typedef ThreadContext::Status Status; 1052SN/A 1062190SN/A protected: 1076315Sgblack@eecs.umich.edu union { 1086315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1096315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1106315Sgblack@eecs.umich.edu } floatRegs; 1116316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 1126313Sgblack@eecs.umich.edu TheISA::ISA isa; // one "instance" of the current ISA. 1132SN/A 1147720Sgblack@eecs.umich.edu TheISA::PCState _pcState; 1156324Sgblack@eecs.umich.edu 1167597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1177597Sminkyu.jeong@arm.com bool predicate; 1187597Sminkyu.jeong@arm.com 1192190SN/A public: 1208357Sksewell@umich.edu std::string name() const 1218357Sksewell@umich.edu { 1228735Sandreas.hanson@arm.com return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 1238357Sksewell@umich.edu } 1248357Sksewell@umich.edu 1252683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1262188SN/A 1272378SN/A System *system; 1282400SN/A 1296022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1306022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1312SN/A 1328541Sgblack@eecs.umich.edu Decoder decoder; 1338541Sgblack@eecs.umich.edu 1342683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1358793Sgblack@eecs.umich.edu // FS 1362683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1376022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 1382683Sktlim@umich.edu bool use_kernel_stats = true); 1398793Sgblack@eecs.umich.edu // SE 1408820Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1418820Sgblack@eecs.umich.edu Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb); 1422862Sktlim@umich.edu 1432864Sktlim@umich.edu SimpleThread(); 1442862Sktlim@umich.edu 1452683Sktlim@umich.edu virtual ~SimpleThread(); 1462SN/A 1472680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 148180SN/A 1492SN/A void regStats(const std::string &name); 1502SN/A 1512864Sktlim@umich.edu void copyTC(ThreadContext *context); 1522864Sktlim@umich.edu 1532862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1542862Sktlim@umich.edu 155217SN/A void serialize(std::ostream &os); 156237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 157217SN/A 1582683Sktlim@umich.edu /*************************************************************** 1592683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1605891Sgblack@eecs.umich.edu * state. 1612683Sktlim@umich.edu **************************************************************/ 1622190SN/A 1632683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1642683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1652683Sktlim@umich.edu * CPU. 1662683Sktlim@umich.edu */ 1672680SN/A ThreadContext *getTC() { return tc; } 1682190SN/A 1695358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1705358Sgblack@eecs.umich.edu { 1715358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1725358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1735358Sgblack@eecs.umich.edu } 1745358Sgblack@eecs.umich.edu 1755358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1765358Sgblack@eecs.umich.edu { 1775358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1785358Sgblack@eecs.umich.edu } 1795358Sgblack@eecs.umich.edu 1805358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1815358Sgblack@eecs.umich.edu { 1825358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1835358Sgblack@eecs.umich.edu } 1845358Sgblack@eecs.umich.edu 1852683Sktlim@umich.edu void dumpFuncProfile(); 1862521SN/A 1875702Ssaidi@eecs.umich.edu Fault hwrei(); 1885702Ssaidi@eecs.umich.edu 1895702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1905702Ssaidi@eecs.umich.edu 1912683Sktlim@umich.edu /******************************************* 1922683Sktlim@umich.edu * ThreadContext interface functions. 1932683Sktlim@umich.edu ******************************************/ 1942683Sktlim@umich.edu 1958735Sandreas.hanson@arm.com BaseCPU *getCpuPtr() { return baseCpu; } 1962683Sktlim@umich.edu 1976022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 1982683Sktlim@umich.edu 1996022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 2002683Sktlim@umich.edu 2018733Sgeoffrey.blake@arm.com#if USE_CHECKER 2028733Sgeoffrey.blake@arm.com BaseCPU *getCheckerCpuPtr() { return NULL; } 2038733Sgeoffrey.blake@arm.com#endif 2048733Sgeoffrey.blake@arm.com 2058541Sgblack@eecs.umich.edu Decoder *getDecoderPtr() { return &decoder; } 2068541Sgblack@eecs.umich.edu 2074997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2084997Sgblack@eecs.umich.edu 2098706Sandreas.hansson@arm.com PortProxy* getPhysProxy() { return physProxy; } 2102683Sktlim@umich.edu 2115499Ssaidi@eecs.umich.edu /** Return a virtual port. This port cannot be cached locally in an object. 2125499Ssaidi@eecs.umich.edu * After a CPU switch it may point to the wrong memory object which could 2135499Ssaidi@eecs.umich.edu * mean stale data. 2145499Ssaidi@eecs.umich.edu */ 2158706Sandreas.hansson@arm.com FSTranslatingPortProxy* getVirtProxy() { return virtProxy; } 2162SN/A 2172683Sktlim@umich.edu Status status() const { return _status; } 2182683Sktlim@umich.edu 2192683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2202683Sktlim@umich.edu 2212683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2222683Sktlim@umich.edu /// cycles to wait before beginning execution. 2232683Sktlim@umich.edu void activate(int delay = 1); 2242683Sktlim@umich.edu 2252683Sktlim@umich.edu /// Set the status to Suspended. 2262683Sktlim@umich.edu void suspend(); 2272683Sktlim@umich.edu 2282683Sktlim@umich.edu /// Set the status to Halted. 2292683Sktlim@umich.edu void halt(); 2302683Sktlim@umich.edu 2312SN/A virtual bool misspeculating(); 2322SN/A 2332683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2342190SN/A 2356315Sgblack@eecs.umich.edu void clearArchRegs() 2366315Sgblack@eecs.umich.edu { 2377720Sgblack@eecs.umich.edu _pcState = 0; 2386316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 2396315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2407400SAli.Saidi@ARM.com isa.clear(); 2416315Sgblack@eecs.umich.edu } 2422190SN/A 2432SN/A // 2442SN/A // New accessors for new decoder. 2452SN/A // 2462SN/A uint64_t readIntReg(int reg_idx) 2472SN/A { 2486313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2496323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2506418Sgblack@eecs.umich.edu uint64_t regVal = intRegs[flatIndex]; 2517601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2527601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 2536418Sgblack@eecs.umich.edu return regVal; 2542SN/A } 2552SN/A 2562455SN/A FloatReg readFloatReg(int reg_idx) 2572SN/A { 2586313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2596323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2607341Sgblack@eecs.umich.edu FloatReg regVal = floatRegs.f[flatIndex]; 2617601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 2627601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 2637341Sgblack@eecs.umich.edu return regVal; 2642SN/A } 2652SN/A 2662455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2672455SN/A { 2686313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2696323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2707341Sgblack@eecs.umich.edu FloatRegBits regVal = floatRegs.i[flatIndex]; 2717601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 2727601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 2737341Sgblack@eecs.umich.edu return regVal; 2742SN/A } 2752SN/A 2762SN/A void setIntReg(int reg_idx, uint64_t val) 2772SN/A { 2786313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2796323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2807601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 2817601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 2826316Sgblack@eecs.umich.edu intRegs[flatIndex] = val; 2832SN/A } 2842SN/A 2852455SN/A void setFloatReg(int reg_idx, FloatReg val) 2862SN/A { 2876313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2886323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2896315Sgblack@eecs.umich.edu floatRegs.f[flatIndex] = val; 2907601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 2917601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 2922SN/A } 2932SN/A 2942455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2952455SN/A { 2966313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2976323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2988733Sgeoffrey.blake@arm.com // XXX: Fix array out of bounds compiler error for gem5.fast 2998733Sgeoffrey.blake@arm.com // when checkercpu enabled 3008733Sgeoffrey.blake@arm.com if (flatIndex < TheISA::NumFloatRegs) 3018733Sgeoffrey.blake@arm.com floatRegs.i[flatIndex] = val; 3027601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 3037601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 3042SN/A } 3052SN/A 3067720Sgblack@eecs.umich.edu TheISA::PCState 3077720Sgblack@eecs.umich.edu pcState() 3082SN/A { 3097720Sgblack@eecs.umich.edu return _pcState; 3102SN/A } 3112SN/A 3127720Sgblack@eecs.umich.edu void 3137720Sgblack@eecs.umich.edu pcState(const TheISA::PCState &val) 3142190SN/A { 3157720Sgblack@eecs.umich.edu _pcState = val; 3162190SN/A } 3172190SN/A 3188733Sgeoffrey.blake@arm.com#if USE_CHECKER 3198733Sgeoffrey.blake@arm.com void 3208733Sgeoffrey.blake@arm.com pcStateNoRecord(const TheISA::PCState &val) 3218733Sgeoffrey.blake@arm.com { 3228733Sgeoffrey.blake@arm.com _pcState = val; 3238733Sgeoffrey.blake@arm.com } 3248733Sgeoffrey.blake@arm.com#endif 3258733Sgeoffrey.blake@arm.com 3267720Sgblack@eecs.umich.edu Addr 3277720Sgblack@eecs.umich.edu instAddr() 3283276Sgblack@eecs.umich.edu { 3297720Sgblack@eecs.umich.edu return _pcState.instAddr(); 3303276Sgblack@eecs.umich.edu } 3313276Sgblack@eecs.umich.edu 3327720Sgblack@eecs.umich.edu Addr 3337720Sgblack@eecs.umich.edu nextInstAddr() 3343276Sgblack@eecs.umich.edu { 3357720Sgblack@eecs.umich.edu return _pcState.nextInstAddr(); 3363276Sgblack@eecs.umich.edu } 3373276Sgblack@eecs.umich.edu 3387720Sgblack@eecs.umich.edu MicroPC 3397720Sgblack@eecs.umich.edu microPC() 3402190SN/A { 3417720Sgblack@eecs.umich.edu return _pcState.microPC(); 3422251SN/A } 3432251SN/A 3447597Sminkyu.jeong@arm.com bool readPredicate() 3457597Sminkyu.jeong@arm.com { 3467597Sminkyu.jeong@arm.com return predicate; 3477597Sminkyu.jeong@arm.com } 3487597Sminkyu.jeong@arm.com 3497597Sminkyu.jeong@arm.com void setPredicate(bool val) 3507597Sminkyu.jeong@arm.com { 3517597Sminkyu.jeong@arm.com predicate = val; 3527597Sminkyu.jeong@arm.com } 3537597Sminkyu.jeong@arm.com 3546221Snate@binkert.org MiscReg 3556221Snate@binkert.org readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 3564172Ssaidi@eecs.umich.edu { 3576313Sgblack@eecs.umich.edu return isa.readMiscRegNoEffect(misc_reg); 3584172Ssaidi@eecs.umich.edu } 3594172Ssaidi@eecs.umich.edu 3606221Snate@binkert.org MiscReg 3616221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 3622SN/A { 3636313Sgblack@eecs.umich.edu return isa.readMiscReg(misc_reg, tc); 3642SN/A } 3652SN/A 3666221Snate@binkert.org void 3676221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3682SN/A { 3696313Sgblack@eecs.umich.edu return isa.setMiscRegNoEffect(misc_reg, val); 3702SN/A } 3712SN/A 3726221Snate@binkert.org void 3736221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3742SN/A { 3756313Sgblack@eecs.umich.edu return isa.setMiscReg(misc_reg, val, tc); 3766313Sgblack@eecs.umich.edu } 3776313Sgblack@eecs.umich.edu 3786313Sgblack@eecs.umich.edu int 3796313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 3806313Sgblack@eecs.umich.edu { 3816313Sgblack@eecs.umich.edu return isa.flattenIntIndex(reg); 3826313Sgblack@eecs.umich.edu } 3836313Sgblack@eecs.umich.edu 3846313Sgblack@eecs.umich.edu int 3856313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 3866313Sgblack@eecs.umich.edu { 3876313Sgblack@eecs.umich.edu return isa.flattenFloatIndex(reg); 3882SN/A } 3892SN/A 3902190SN/A unsigned readStCondFailures() { return storeCondFailures; } 3912190SN/A 3922190SN/A void setStCondFailures(unsigned sc_failures) 3932190SN/A { storeCondFailures = sc_failures; } 3942190SN/A 3952561SN/A void syscall(int64_t callnum) 3962SN/A { 3972680SN/A process->syscall(callnum, tc); 3982SN/A } 3992SN/A}; 4002SN/A 4012SN/A 4022SN/A// for non-speculative execution context, spec_mode is always false 4032SN/Ainline bool 4042683Sktlim@umich.eduSimpleThread::misspeculating() 4052SN/A{ 4062SN/A return false; 4072SN/A} 4082SN/A 4092190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 410