simple_thread.hh revision 8777
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302SN/A */ 312SN/A 322683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 332683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 342SN/A 356313Sgblack@eecs.umich.edu#include "arch/isa.hh" 362190SN/A#include "arch/isa_traits.hh" 376329Sgblack@eecs.umich.edu#include "arch/registers.hh" 384997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 396316Sgblack@eecs.umich.edu#include "arch/types.hh" 406216Snate@binkert.org#include "base/types.hh" 411858SN/A#include "config/full_system.hh" 426658Snate@binkert.org#include "config/the_isa.hh" 438541Sgblack@eecs.umich.edu#include "cpu/decode.hh" 442680SN/A#include "cpu/thread_context.hh" 452683Sktlim@umich.edu#include "cpu/thread_state.hh" 468232Snate@binkert.org#include "debug/FloatRegs.hh" 478232Snate@binkert.org#include "debug/IntRegs.hh" 488777Sgblack@eecs.umich.edu#include "mem/page_table.hh" 492395SN/A#include "mem/request.hh" 502190SN/A#include "sim/byteswap.hh" 512188SN/A#include "sim/eventq.hh" 528777Sgblack@eecs.umich.edu#include "sim/process.hh" 53217SN/A#include "sim/serialize.hh" 548777Sgblack@eecs.umich.edu#include "sim/system.hh" 552SN/A 562SN/Aclass BaseCPU; 572SN/A 581070SN/A 591917SN/Aclass FunctionProfile; 601917SN/Aclass ProfileNode; 612521SN/Aclass FunctionalPort; 622521SN/Aclass PhysicalPort; 638777Sgblack@eecs.umich.educlass TranslatingPort; 642521SN/A 653548Sgblack@eecs.umich.edunamespace TheISA { 663548Sgblack@eecs.umich.edu namespace Kernel { 673548Sgblack@eecs.umich.edu class Statistics; 683548Sgblack@eecs.umich.edu }; 692330SN/A}; 702330SN/A 712683Sktlim@umich.edu/** 722683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 732683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 742683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 752683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 762683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 772683Sktlim@umich.edu * the objects needed for simple functional execution, including a 782683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 792683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 802683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 812683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 822683Sktlim@umich.edu * all the necessary state for full architecture-level functional 832683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 842683Sktlim@umich.edu * examples. 852683Sktlim@umich.edu */ 862SN/A 872683Sktlim@umich.educlass SimpleThread : public ThreadState 882SN/A{ 892107SN/A protected: 902107SN/A typedef TheISA::MachInst MachInst; 912159SN/A typedef TheISA::MiscReg MiscReg; 922455SN/A typedef TheISA::FloatReg FloatReg; 932455SN/A typedef TheISA::FloatRegBits FloatRegBits; 942SN/A public: 952680SN/A typedef ThreadContext::Status Status; 962SN/A 972190SN/A protected: 986315Sgblack@eecs.umich.edu union { 996315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1006315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1016315Sgblack@eecs.umich.edu } floatRegs; 1026316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 1036313Sgblack@eecs.umich.edu TheISA::ISA isa; // one "instance" of the current ISA. 1042SN/A 1057720Sgblack@eecs.umich.edu TheISA::PCState _pcState; 1066324Sgblack@eecs.umich.edu 1077597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1087597Sminkyu.jeong@arm.com bool predicate; 1097597Sminkyu.jeong@arm.com 1102190SN/A public: 1118357Sksewell@umich.edu std::string name() const 1128357Sksewell@umich.edu { 1138357Sksewell@umich.edu return csprintf("%s.[tid:%i]", cpu->name(), tc->threadId()); 1148357Sksewell@umich.edu } 1158357Sksewell@umich.edu 1162683Sktlim@umich.edu // pointer to CPU associated with this SimpleThread 1172SN/A BaseCPU *cpu; 1182SN/A 1192683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1202188SN/A 1212378SN/A System *system; 1222400SN/A 1236022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1246022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1252SN/A 1268541Sgblack@eecs.umich.edu Decoder decoder; 1278541Sgblack@eecs.umich.edu 1282683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1291858SN/A#if FULL_SYSTEM 1302683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1316022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 1322683Sktlim@umich.edu bool use_kernel_stats = true); 1332SN/A#else 1344997Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 1356331Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb); 1362SN/A#endif 1372862Sktlim@umich.edu 1382864Sktlim@umich.edu SimpleThread(); 1392862Sktlim@umich.edu 1402683Sktlim@umich.edu virtual ~SimpleThread(); 1412SN/A 1422680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 143180SN/A 1442SN/A void regStats(const std::string &name); 1452SN/A 1462864Sktlim@umich.edu void copyTC(ThreadContext *context); 1472864Sktlim@umich.edu 1482862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1492862Sktlim@umich.edu 150217SN/A void serialize(std::ostream &os); 151237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 152217SN/A 1532683Sktlim@umich.edu /*************************************************************** 1542683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1555891Sgblack@eecs.umich.edu * state. 1562683Sktlim@umich.edu **************************************************************/ 1572190SN/A 1582683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1592683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1602683Sktlim@umich.edu * CPU. 1612683Sktlim@umich.edu */ 1622680SN/A ThreadContext *getTC() { return tc; } 1632190SN/A 1645358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1655358Sgblack@eecs.umich.edu { 1665358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1675358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1685358Sgblack@eecs.umich.edu } 1695358Sgblack@eecs.umich.edu 1705358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1715358Sgblack@eecs.umich.edu { 1725358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1735358Sgblack@eecs.umich.edu } 1745358Sgblack@eecs.umich.edu 1755358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1765358Sgblack@eecs.umich.edu { 1775358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1785358Sgblack@eecs.umich.edu } 1795358Sgblack@eecs.umich.edu 1802683Sktlim@umich.edu void dumpFuncProfile(); 1812521SN/A 1825702Ssaidi@eecs.umich.edu Fault hwrei(); 1835702Ssaidi@eecs.umich.edu 1845702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1855702Ssaidi@eecs.umich.edu 1862683Sktlim@umich.edu /******************************************* 1872683Sktlim@umich.edu * ThreadContext interface functions. 1882683Sktlim@umich.edu ******************************************/ 1892683Sktlim@umich.edu 1902683Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 1912683Sktlim@umich.edu 1926022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 1932683Sktlim@umich.edu 1946022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 1952683Sktlim@umich.edu 1968541Sgblack@eecs.umich.edu Decoder *getDecoderPtr() { return &decoder; } 1978541Sgblack@eecs.umich.edu 1984997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 1994997Sgblack@eecs.umich.edu 2008761Sgblack@eecs.umich.edu FunctionalPort *getPhysPort() { return physPort; } 2018761Sgblack@eecs.umich.edu 2025499Ssaidi@eecs.umich.edu /** Return a virtual port. This port cannot be cached locally in an object. 2035499Ssaidi@eecs.umich.edu * After a CPU switch it may point to the wrong memory object which could 2045499Ssaidi@eecs.umich.edu * mean stale data. 2055499Ssaidi@eecs.umich.edu */ 2065499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return virtPort; } 2078754Sgblack@eecs.umich.edu 2082683Sktlim@umich.edu Status status() const { return _status; } 2092683Sktlim@umich.edu 2102683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2112683Sktlim@umich.edu 2122683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2132683Sktlim@umich.edu /// cycles to wait before beginning execution. 2142683Sktlim@umich.edu void activate(int delay = 1); 2152683Sktlim@umich.edu 2162683Sktlim@umich.edu /// Set the status to Suspended. 2172683Sktlim@umich.edu void suspend(); 2182683Sktlim@umich.edu 2192683Sktlim@umich.edu /// Set the status to Halted. 2202683Sktlim@umich.edu void halt(); 2212683Sktlim@umich.edu 2222SN/A virtual bool misspeculating(); 2232SN/A 2242683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2252190SN/A 2266315Sgblack@eecs.umich.edu void clearArchRegs() 2276315Sgblack@eecs.umich.edu { 2287720Sgblack@eecs.umich.edu _pcState = 0; 2296316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 2306315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2317400SAli.Saidi@ARM.com isa.clear(); 2326315Sgblack@eecs.umich.edu } 2332190SN/A 2342SN/A // 2352SN/A // New accessors for new decoder. 2362SN/A // 2372SN/A uint64_t readIntReg(int reg_idx) 2382SN/A { 2396313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2406323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2416418Sgblack@eecs.umich.edu uint64_t regVal = intRegs[flatIndex]; 2427601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2437601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 2446418Sgblack@eecs.umich.edu return regVal; 2452SN/A } 2462SN/A 2472455SN/A FloatReg readFloatReg(int reg_idx) 2482SN/A { 2496313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2506323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2517341Sgblack@eecs.umich.edu FloatReg regVal = floatRegs.f[flatIndex]; 2527601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 2537601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 2547341Sgblack@eecs.umich.edu return regVal; 2552SN/A } 2562SN/A 2572455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2582455SN/A { 2596313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2606323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2617341Sgblack@eecs.umich.edu FloatRegBits regVal = floatRegs.i[flatIndex]; 2627601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 2637601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 2647341Sgblack@eecs.umich.edu return regVal; 2652SN/A } 2662SN/A 2672SN/A void setIntReg(int reg_idx, uint64_t val) 2682SN/A { 2696313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2706323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2717601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 2727601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 2736316Sgblack@eecs.umich.edu intRegs[flatIndex] = val; 2742SN/A } 2752SN/A 2762455SN/A void setFloatReg(int reg_idx, FloatReg val) 2772SN/A { 2786313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2796323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2806315Sgblack@eecs.umich.edu floatRegs.f[flatIndex] = val; 2817601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 2827601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 2832SN/A } 2842SN/A 2852455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2862455SN/A { 2876313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2886323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2896315Sgblack@eecs.umich.edu floatRegs.i[flatIndex] = val; 2907601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 2917601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 2922SN/A } 2932SN/A 2947720Sgblack@eecs.umich.edu TheISA::PCState 2957720Sgblack@eecs.umich.edu pcState() 2962SN/A { 2977720Sgblack@eecs.umich.edu return _pcState; 2982SN/A } 2992SN/A 3007720Sgblack@eecs.umich.edu void 3017720Sgblack@eecs.umich.edu pcState(const TheISA::PCState &val) 3022190SN/A { 3037720Sgblack@eecs.umich.edu _pcState = val; 3042190SN/A } 3052190SN/A 3067720Sgblack@eecs.umich.edu Addr 3077720Sgblack@eecs.umich.edu instAddr() 3083276Sgblack@eecs.umich.edu { 3097720Sgblack@eecs.umich.edu return _pcState.instAddr(); 3103276Sgblack@eecs.umich.edu } 3113276Sgblack@eecs.umich.edu 3127720Sgblack@eecs.umich.edu Addr 3137720Sgblack@eecs.umich.edu nextInstAddr() 3143276Sgblack@eecs.umich.edu { 3157720Sgblack@eecs.umich.edu return _pcState.nextInstAddr(); 3163276Sgblack@eecs.umich.edu } 3173276Sgblack@eecs.umich.edu 3187720Sgblack@eecs.umich.edu MicroPC 3197720Sgblack@eecs.umich.edu microPC() 3202190SN/A { 3217720Sgblack@eecs.umich.edu return _pcState.microPC(); 3222251SN/A } 3232251SN/A 3247597Sminkyu.jeong@arm.com bool readPredicate() 3257597Sminkyu.jeong@arm.com { 3267597Sminkyu.jeong@arm.com return predicate; 3277597Sminkyu.jeong@arm.com } 3287597Sminkyu.jeong@arm.com 3297597Sminkyu.jeong@arm.com void setPredicate(bool val) 3307597Sminkyu.jeong@arm.com { 3317597Sminkyu.jeong@arm.com predicate = val; 3327597Sminkyu.jeong@arm.com } 3337597Sminkyu.jeong@arm.com 3346221Snate@binkert.org MiscReg 3356221Snate@binkert.org readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 3364172Ssaidi@eecs.umich.edu { 3376313Sgblack@eecs.umich.edu return isa.readMiscRegNoEffect(misc_reg); 3384172Ssaidi@eecs.umich.edu } 3394172Ssaidi@eecs.umich.edu 3406221Snate@binkert.org MiscReg 3416221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 3422SN/A { 3436313Sgblack@eecs.umich.edu return isa.readMiscReg(misc_reg, tc); 3442SN/A } 3452SN/A 3466221Snate@binkert.org void 3476221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3482SN/A { 3496313Sgblack@eecs.umich.edu return isa.setMiscRegNoEffect(misc_reg, val); 3502SN/A } 3512SN/A 3526221Snate@binkert.org void 3536221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3542SN/A { 3556313Sgblack@eecs.umich.edu return isa.setMiscReg(misc_reg, val, tc); 3566313Sgblack@eecs.umich.edu } 3576313Sgblack@eecs.umich.edu 3586313Sgblack@eecs.umich.edu int 3596313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 3606313Sgblack@eecs.umich.edu { 3616313Sgblack@eecs.umich.edu return isa.flattenIntIndex(reg); 3626313Sgblack@eecs.umich.edu } 3636313Sgblack@eecs.umich.edu 3646313Sgblack@eecs.umich.edu int 3656313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 3666313Sgblack@eecs.umich.edu { 3676313Sgblack@eecs.umich.edu return isa.flattenFloatIndex(reg); 3682SN/A } 3692SN/A 3702190SN/A unsigned readStCondFailures() { return storeCondFailures; } 3712190SN/A 3722190SN/A void setStCondFailures(unsigned sc_failures) 3732190SN/A { storeCondFailures = sc_failures; } 3742190SN/A 3752561SN/A void syscall(int64_t callnum) 3762SN/A { 3772680SN/A process->syscall(callnum, tc); 3782SN/A } 3792SN/A}; 3802SN/A 3812SN/A 3822SN/A// for non-speculative execution context, spec_mode is always false 3832SN/Ainline bool 3842683Sktlim@umich.eduSimpleThread::misspeculating() 3852SN/A{ 3862SN/A return false; 3872SN/A} 3882SN/A 3892190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 390