simple_thread.hh revision 8735
12SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 142188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Steve Reinhardt 412665SN/A * Nathan Binkert 422SN/A */ 432SN/A 442683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 452683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 462SN/A 476313Sgblack@eecs.umich.edu#include "arch/isa.hh" 482190SN/A#include "arch/isa_traits.hh" 496329Sgblack@eecs.umich.edu#include "arch/registers.hh" 504997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 516316Sgblack@eecs.umich.edu#include "arch/types.hh" 526216Snate@binkert.org#include "base/types.hh" 531858SN/A#include "config/full_system.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 558733Sgeoffrey.blake@arm.com#include "config/use_checker.hh" 568541Sgblack@eecs.umich.edu#include "cpu/decode.hh" 572680SN/A#include "cpu/thread_context.hh" 582683Sktlim@umich.edu#include "cpu/thread_state.hh" 598232Snate@binkert.org#include "debug/FloatRegs.hh" 608232Snate@binkert.org#include "debug/IntRegs.hh" 612395SN/A#include "mem/request.hh" 622190SN/A#include "sim/byteswap.hh" 632188SN/A#include "sim/eventq.hh" 64217SN/A#include "sim/serialize.hh" 652SN/A 662SN/Aclass BaseCPU; 672SN/A 681858SN/A#if FULL_SYSTEM 692SN/A 701070SN/A#include "sim/system.hh" 711070SN/A 721917SN/Aclass FunctionProfile; 731917SN/Aclass ProfileNode; 742521SN/A 753548Sgblack@eecs.umich.edunamespace TheISA { 763548Sgblack@eecs.umich.edu namespace Kernel { 773548Sgblack@eecs.umich.edu class Statistics; 783548Sgblack@eecs.umich.edu }; 792330SN/A}; 802330SN/A 812SN/A#else // !FULL_SYSTEM 822SN/A 838229Snate@binkert.org#include "mem/page_table.hh" 84360SN/A#include "sim/process.hh" 852SN/A 862SN/A#endif // FULL_SYSTEM 872SN/A 882683Sktlim@umich.edu/** 892683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 902683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 912683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 922683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 932683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 942683Sktlim@umich.edu * the objects needed for simple functional execution, including a 952683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 962683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 972683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 982683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 992683Sktlim@umich.edu * all the necessary state for full architecture-level functional 1002683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 1012683Sktlim@umich.edu * examples. 1022683Sktlim@umich.edu */ 1032SN/A 1042683Sktlim@umich.educlass SimpleThread : public ThreadState 1052SN/A{ 1062107SN/A protected: 1072107SN/A typedef TheISA::MachInst MachInst; 1082159SN/A typedef TheISA::MiscReg MiscReg; 1092455SN/A typedef TheISA::FloatReg FloatReg; 1102455SN/A typedef TheISA::FloatRegBits FloatRegBits; 1112SN/A public: 1122680SN/A typedef ThreadContext::Status Status; 1132SN/A 1142190SN/A protected: 1156315Sgblack@eecs.umich.edu union { 1166315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1176315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1186315Sgblack@eecs.umich.edu } floatRegs; 1196316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 1206313Sgblack@eecs.umich.edu TheISA::ISA isa; // one "instance" of the current ISA. 1212SN/A 1227720Sgblack@eecs.umich.edu TheISA::PCState _pcState; 1236324Sgblack@eecs.umich.edu 1247597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1257597Sminkyu.jeong@arm.com bool predicate; 1267597Sminkyu.jeong@arm.com 1272190SN/A public: 1288357Sksewell@umich.edu std::string name() const 1298357Sksewell@umich.edu { 1308735Sandreas.hanson@arm.com return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 1318357Sksewell@umich.edu } 1328357Sksewell@umich.edu 1332683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1342188SN/A 1352378SN/A System *system; 1362400SN/A 1376022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1386022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1392SN/A 1408541Sgblack@eecs.umich.edu Decoder decoder; 1418541Sgblack@eecs.umich.edu 1422683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1431858SN/A#if FULL_SYSTEM 1442683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1456022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 1462683Sktlim@umich.edu bool use_kernel_stats = true); 1472SN/A#else 1484997Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 1496331Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb); 1502SN/A#endif 1512862Sktlim@umich.edu 1522864Sktlim@umich.edu SimpleThread(); 1532862Sktlim@umich.edu 1542683Sktlim@umich.edu virtual ~SimpleThread(); 1552SN/A 1562680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 157180SN/A 1582SN/A void regStats(const std::string &name); 1592SN/A 1602864Sktlim@umich.edu void copyTC(ThreadContext *context); 1612864Sktlim@umich.edu 1622862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1632862Sktlim@umich.edu 164217SN/A void serialize(std::ostream &os); 165237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 166217SN/A 1672683Sktlim@umich.edu /*************************************************************** 1682683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1695891Sgblack@eecs.umich.edu * state. 1702683Sktlim@umich.edu **************************************************************/ 1712190SN/A 1722683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1732683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1742683Sktlim@umich.edu * CPU. 1752683Sktlim@umich.edu */ 1762680SN/A ThreadContext *getTC() { return tc; } 1772190SN/A 1785358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1795358Sgblack@eecs.umich.edu { 1805358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1815358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1825358Sgblack@eecs.umich.edu } 1835358Sgblack@eecs.umich.edu 1845358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1855358Sgblack@eecs.umich.edu { 1865358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1875358Sgblack@eecs.umich.edu } 1885358Sgblack@eecs.umich.edu 1895358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1905358Sgblack@eecs.umich.edu { 1915358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1925358Sgblack@eecs.umich.edu } 1935358Sgblack@eecs.umich.edu 1944997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1952683Sktlim@umich.edu void dumpFuncProfile(); 1962521SN/A 1975702Ssaidi@eecs.umich.edu Fault hwrei(); 1985702Ssaidi@eecs.umich.edu 1995702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 2005702Ssaidi@eecs.umich.edu 2012683Sktlim@umich.edu#endif 2022SN/A 2032683Sktlim@umich.edu /******************************************* 2042683Sktlim@umich.edu * ThreadContext interface functions. 2052683Sktlim@umich.edu ******************************************/ 2062683Sktlim@umich.edu 2078735Sandreas.hanson@arm.com BaseCPU *getCpuPtr() { return baseCpu; } 2082683Sktlim@umich.edu 2096022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 2102683Sktlim@umich.edu 2116022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 2122683Sktlim@umich.edu 2138733Sgeoffrey.blake@arm.com#if USE_CHECKER 2148733Sgeoffrey.blake@arm.com BaseCPU *getCheckerCpuPtr() { return NULL; } 2158733Sgeoffrey.blake@arm.com#endif 2168733Sgeoffrey.blake@arm.com 2178541Sgblack@eecs.umich.edu Decoder *getDecoderPtr() { return &decoder; } 2188541Sgblack@eecs.umich.edu 2194997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2204997Sgblack@eecs.umich.edu 2215803Snate@binkert.org#if FULL_SYSTEM 2228706Sandreas.hansson@arm.com PortProxy* getPhysProxy() { return physProxy; } 2232683Sktlim@umich.edu 2245499Ssaidi@eecs.umich.edu /** Return a virtual port. This port cannot be cached locally in an object. 2255499Ssaidi@eecs.umich.edu * After a CPU switch it may point to the wrong memory object which could 2265499Ssaidi@eecs.umich.edu * mean stale data. 2275499Ssaidi@eecs.umich.edu */ 2288706Sandreas.hansson@arm.com FSTranslatingPortProxy* getVirtProxy() { return virtProxy; } 2292SN/A#endif 2302SN/A 2312683Sktlim@umich.edu Status status() const { return _status; } 2322683Sktlim@umich.edu 2332683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2342683Sktlim@umich.edu 2352683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2362683Sktlim@umich.edu /// cycles to wait before beginning execution. 2372683Sktlim@umich.edu void activate(int delay = 1); 2382683Sktlim@umich.edu 2392683Sktlim@umich.edu /// Set the status to Suspended. 2402683Sktlim@umich.edu void suspend(); 2412683Sktlim@umich.edu 2422683Sktlim@umich.edu /// Set the status to Halted. 2432683Sktlim@umich.edu void halt(); 2442683Sktlim@umich.edu 2452SN/A virtual bool misspeculating(); 2462SN/A 2472683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2482190SN/A 2496315Sgblack@eecs.umich.edu void clearArchRegs() 2506315Sgblack@eecs.umich.edu { 2517720Sgblack@eecs.umich.edu _pcState = 0; 2526316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 2536315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2547400SAli.Saidi@ARM.com isa.clear(); 2556315Sgblack@eecs.umich.edu } 2562190SN/A 2572SN/A // 2582SN/A // New accessors for new decoder. 2592SN/A // 2602SN/A uint64_t readIntReg(int reg_idx) 2612SN/A { 2626313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2636323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2646418Sgblack@eecs.umich.edu uint64_t regVal = intRegs[flatIndex]; 2657601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2667601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 2676418Sgblack@eecs.umich.edu return regVal; 2682SN/A } 2692SN/A 2702455SN/A FloatReg readFloatReg(int reg_idx) 2712SN/A { 2726313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2736323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2747341Sgblack@eecs.umich.edu FloatReg regVal = floatRegs.f[flatIndex]; 2757601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 2767601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 2777341Sgblack@eecs.umich.edu return regVal; 2782SN/A } 2792SN/A 2802455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2812455SN/A { 2826313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2836323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2847341Sgblack@eecs.umich.edu FloatRegBits regVal = floatRegs.i[flatIndex]; 2857601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 2867601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 2877341Sgblack@eecs.umich.edu return regVal; 2882SN/A } 2892SN/A 2902SN/A void setIntReg(int reg_idx, uint64_t val) 2912SN/A { 2926313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2936323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2947601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 2957601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 2966316Sgblack@eecs.umich.edu intRegs[flatIndex] = val; 2972SN/A } 2982SN/A 2992455SN/A void setFloatReg(int reg_idx, FloatReg val) 3002SN/A { 3016313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 3026323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 3036315Sgblack@eecs.umich.edu floatRegs.f[flatIndex] = val; 3047601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 3057601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 3062SN/A } 3072SN/A 3082455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3092455SN/A { 3106313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 3116323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 3128733Sgeoffrey.blake@arm.com // XXX: Fix array out of bounds compiler error for gem5.fast 3138733Sgeoffrey.blake@arm.com // when checkercpu enabled 3148733Sgeoffrey.blake@arm.com if (flatIndex < TheISA::NumFloatRegs) 3158733Sgeoffrey.blake@arm.com floatRegs.i[flatIndex] = val; 3167601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 3177601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 3182SN/A } 3192SN/A 3207720Sgblack@eecs.umich.edu TheISA::PCState 3217720Sgblack@eecs.umich.edu pcState() 3222SN/A { 3237720Sgblack@eecs.umich.edu return _pcState; 3242SN/A } 3252SN/A 3267720Sgblack@eecs.umich.edu void 3277720Sgblack@eecs.umich.edu pcState(const TheISA::PCState &val) 3282190SN/A { 3297720Sgblack@eecs.umich.edu _pcState = val; 3302190SN/A } 3312190SN/A 3328733Sgeoffrey.blake@arm.com#if USE_CHECKER 3338733Sgeoffrey.blake@arm.com void 3348733Sgeoffrey.blake@arm.com pcStateNoRecord(const TheISA::PCState &val) 3358733Sgeoffrey.blake@arm.com { 3368733Sgeoffrey.blake@arm.com _pcState = val; 3378733Sgeoffrey.blake@arm.com } 3388733Sgeoffrey.blake@arm.com#endif 3398733Sgeoffrey.blake@arm.com 3407720Sgblack@eecs.umich.edu Addr 3417720Sgblack@eecs.umich.edu instAddr() 3423276Sgblack@eecs.umich.edu { 3437720Sgblack@eecs.umich.edu return _pcState.instAddr(); 3443276Sgblack@eecs.umich.edu } 3453276Sgblack@eecs.umich.edu 3467720Sgblack@eecs.umich.edu Addr 3477720Sgblack@eecs.umich.edu nextInstAddr() 3483276Sgblack@eecs.umich.edu { 3497720Sgblack@eecs.umich.edu return _pcState.nextInstAddr(); 3503276Sgblack@eecs.umich.edu } 3513276Sgblack@eecs.umich.edu 3527720Sgblack@eecs.umich.edu MicroPC 3537720Sgblack@eecs.umich.edu microPC() 3542190SN/A { 3557720Sgblack@eecs.umich.edu return _pcState.microPC(); 3562251SN/A } 3572251SN/A 3587597Sminkyu.jeong@arm.com bool readPredicate() 3597597Sminkyu.jeong@arm.com { 3607597Sminkyu.jeong@arm.com return predicate; 3617597Sminkyu.jeong@arm.com } 3627597Sminkyu.jeong@arm.com 3637597Sminkyu.jeong@arm.com void setPredicate(bool val) 3647597Sminkyu.jeong@arm.com { 3657597Sminkyu.jeong@arm.com predicate = val; 3667597Sminkyu.jeong@arm.com } 3677597Sminkyu.jeong@arm.com 3686221Snate@binkert.org MiscReg 3696221Snate@binkert.org readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 3704172Ssaidi@eecs.umich.edu { 3716313Sgblack@eecs.umich.edu return isa.readMiscRegNoEffect(misc_reg); 3724172Ssaidi@eecs.umich.edu } 3734172Ssaidi@eecs.umich.edu 3746221Snate@binkert.org MiscReg 3756221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 3762SN/A { 3776313Sgblack@eecs.umich.edu return isa.readMiscReg(misc_reg, tc); 3782SN/A } 3792SN/A 3806221Snate@binkert.org void 3816221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3822SN/A { 3836313Sgblack@eecs.umich.edu return isa.setMiscRegNoEffect(misc_reg, val); 3842SN/A } 3852SN/A 3866221Snate@binkert.org void 3876221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3882SN/A { 3896313Sgblack@eecs.umich.edu return isa.setMiscReg(misc_reg, val, tc); 3906313Sgblack@eecs.umich.edu } 3916313Sgblack@eecs.umich.edu 3926313Sgblack@eecs.umich.edu int 3936313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 3946313Sgblack@eecs.umich.edu { 3956313Sgblack@eecs.umich.edu return isa.flattenIntIndex(reg); 3966313Sgblack@eecs.umich.edu } 3976313Sgblack@eecs.umich.edu 3986313Sgblack@eecs.umich.edu int 3996313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 4006313Sgblack@eecs.umich.edu { 4016313Sgblack@eecs.umich.edu return isa.flattenFloatIndex(reg); 4022SN/A } 4032SN/A 4042190SN/A unsigned readStCondFailures() { return storeCondFailures; } 4052190SN/A 4062190SN/A void setStCondFailures(unsigned sc_failures) 4072190SN/A { storeCondFailures = sc_failures; } 4082190SN/A 4091858SN/A#if !FULL_SYSTEM 4102561SN/A void syscall(int64_t callnum) 4112SN/A { 4122680SN/A process->syscall(callnum, tc); 4132SN/A } 4142SN/A#endif 4152SN/A}; 4162SN/A 4172SN/A 4182SN/A// for non-speculative execution context, spec_mode is always false 4192SN/Ainline bool 4202683Sktlim@umich.eduSimpleThread::misspeculating() 4212SN/A{ 4222SN/A return false; 4232SN/A} 4242SN/A 4252190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 426