simple_thread.hh revision 8706
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302SN/A */ 312SN/A 322683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 332683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 342SN/A 356313Sgblack@eecs.umich.edu#include "arch/isa.hh" 362190SN/A#include "arch/isa_traits.hh" 376329Sgblack@eecs.umich.edu#include "arch/registers.hh" 384997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 396316Sgblack@eecs.umich.edu#include "arch/types.hh" 406216Snate@binkert.org#include "base/types.hh" 411858SN/A#include "config/full_system.hh" 426658Snate@binkert.org#include "config/the_isa.hh" 438541Sgblack@eecs.umich.edu#include "cpu/decode.hh" 442680SN/A#include "cpu/thread_context.hh" 452683Sktlim@umich.edu#include "cpu/thread_state.hh" 468232Snate@binkert.org#include "debug/FloatRegs.hh" 478232Snate@binkert.org#include "debug/IntRegs.hh" 482395SN/A#include "mem/request.hh" 492190SN/A#include "sim/byteswap.hh" 502188SN/A#include "sim/eventq.hh" 51217SN/A#include "sim/serialize.hh" 522SN/A 532SN/Aclass BaseCPU; 542SN/A 551858SN/A#if FULL_SYSTEM 562SN/A 571070SN/A#include "sim/system.hh" 581070SN/A 591917SN/Aclass FunctionProfile; 601917SN/Aclass ProfileNode; 612521SN/Aclass FunctionalPort; 622521SN/Aclass PhysicalPort; 632521SN/A 643548Sgblack@eecs.umich.edunamespace TheISA { 653548Sgblack@eecs.umich.edu namespace Kernel { 663548Sgblack@eecs.umich.edu class Statistics; 673548Sgblack@eecs.umich.edu }; 682330SN/A}; 692330SN/A 702SN/A#else // !FULL_SYSTEM 712SN/A 728229Snate@binkert.org#include "mem/page_table.hh" 73360SN/A#include "sim/process.hh" 742420SN/Aclass TranslatingPort; 752SN/A 762SN/A#endif // FULL_SYSTEM 772SN/A 782683Sktlim@umich.edu/** 792683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 802683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 812683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 822683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 832683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 842683Sktlim@umich.edu * the objects needed for simple functional execution, including a 852683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 862683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 872683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 882683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 892683Sktlim@umich.edu * all the necessary state for full architecture-level functional 902683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 912683Sktlim@umich.edu * examples. 922683Sktlim@umich.edu */ 932SN/A 942683Sktlim@umich.educlass SimpleThread : public ThreadState 952SN/A{ 962107SN/A protected: 972107SN/A typedef TheISA::MachInst MachInst; 982159SN/A typedef TheISA::MiscReg MiscReg; 992455SN/A typedef TheISA::FloatReg FloatReg; 1002455SN/A typedef TheISA::FloatRegBits FloatRegBits; 1012SN/A public: 1022680SN/A typedef ThreadContext::Status Status; 1032SN/A 1042190SN/A protected: 1056315Sgblack@eecs.umich.edu union { 1066315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1076315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1086315Sgblack@eecs.umich.edu } floatRegs; 1096316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 1106313Sgblack@eecs.umich.edu TheISA::ISA isa; // one "instance" of the current ISA. 1112SN/A 1127720Sgblack@eecs.umich.edu TheISA::PCState _pcState; 1136324Sgblack@eecs.umich.edu 1147597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1157597Sminkyu.jeong@arm.com bool predicate; 1167597Sminkyu.jeong@arm.com 1172190SN/A public: 1188357Sksewell@umich.edu std::string name() const 1198357Sksewell@umich.edu { 1208357Sksewell@umich.edu return csprintf("%s.[tid:%i]", cpu->name(), tc->threadId()); 1218357Sksewell@umich.edu } 1228357Sksewell@umich.edu 1232683Sktlim@umich.edu // pointer to CPU associated with this SimpleThread 1242SN/A BaseCPU *cpu; 1252SN/A 1262683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1272188SN/A 1282378SN/A System *system; 1292400SN/A 1306022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1316022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1322SN/A 1338541Sgblack@eecs.umich.edu Decoder decoder; 1348541Sgblack@eecs.umich.edu 1352683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1361858SN/A#if FULL_SYSTEM 1372683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1386022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 1392683Sktlim@umich.edu bool use_kernel_stats = true); 1402SN/A#else 1414997Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 1426331Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb); 1432SN/A#endif 1442862Sktlim@umich.edu 1452864Sktlim@umich.edu SimpleThread(); 1462862Sktlim@umich.edu 1472683Sktlim@umich.edu virtual ~SimpleThread(); 1482SN/A 1492680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 150180SN/A 1512SN/A void regStats(const std::string &name); 1522SN/A 1532864Sktlim@umich.edu void copyTC(ThreadContext *context); 1542864Sktlim@umich.edu 1552862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1562862Sktlim@umich.edu 157217SN/A void serialize(std::ostream &os); 158237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 159217SN/A 1602683Sktlim@umich.edu /*************************************************************** 1612683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1625891Sgblack@eecs.umich.edu * state. 1632683Sktlim@umich.edu **************************************************************/ 1642190SN/A 1652683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1662683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1672683Sktlim@umich.edu * CPU. 1682683Sktlim@umich.edu */ 1692680SN/A ThreadContext *getTC() { return tc; } 1702190SN/A 1715358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1725358Sgblack@eecs.umich.edu { 1735358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1745358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1755358Sgblack@eecs.umich.edu } 1765358Sgblack@eecs.umich.edu 1775358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1785358Sgblack@eecs.umich.edu { 1795358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1805358Sgblack@eecs.umich.edu } 1815358Sgblack@eecs.umich.edu 1825358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1835358Sgblack@eecs.umich.edu { 1845358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1855358Sgblack@eecs.umich.edu } 1865358Sgblack@eecs.umich.edu 1874997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1882683Sktlim@umich.edu void dumpFuncProfile(); 1892521SN/A 1905702Ssaidi@eecs.umich.edu Fault hwrei(); 1915702Ssaidi@eecs.umich.edu 1925702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1935702Ssaidi@eecs.umich.edu 1942683Sktlim@umich.edu#endif 1952SN/A 1962683Sktlim@umich.edu /******************************************* 1972683Sktlim@umich.edu * ThreadContext interface functions. 1982683Sktlim@umich.edu ******************************************/ 1992683Sktlim@umich.edu 2002683Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 2012683Sktlim@umich.edu 2026022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 2032683Sktlim@umich.edu 2046022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 2052683Sktlim@umich.edu 2068541Sgblack@eecs.umich.edu Decoder *getDecoderPtr() { return &decoder; } 2078541Sgblack@eecs.umich.edu 2084997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2094997Sgblack@eecs.umich.edu 2105803Snate@binkert.org#if FULL_SYSTEM 2118706Sandreas.hansson@arm.com PortProxy* getPhysProxy() { return physProxy; } 2122683Sktlim@umich.edu 2135499Ssaidi@eecs.umich.edu /** Return a virtual port. This port cannot be cached locally in an object. 2145499Ssaidi@eecs.umich.edu * After a CPU switch it may point to the wrong memory object which could 2155499Ssaidi@eecs.umich.edu * mean stale data. 2165499Ssaidi@eecs.umich.edu */ 2178706Sandreas.hansson@arm.com FSTranslatingPortProxy* getVirtProxy() { return virtProxy; } 2182SN/A#endif 2192SN/A 2202683Sktlim@umich.edu Status status() const { return _status; } 2212683Sktlim@umich.edu 2222683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2232683Sktlim@umich.edu 2242683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2252683Sktlim@umich.edu /// cycles to wait before beginning execution. 2262683Sktlim@umich.edu void activate(int delay = 1); 2272683Sktlim@umich.edu 2282683Sktlim@umich.edu /// Set the status to Suspended. 2292683Sktlim@umich.edu void suspend(); 2302683Sktlim@umich.edu 2312683Sktlim@umich.edu /// Set the status to Halted. 2322683Sktlim@umich.edu void halt(); 2332683Sktlim@umich.edu 2342SN/A virtual bool misspeculating(); 2352SN/A 2362683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2372190SN/A 2386315Sgblack@eecs.umich.edu void clearArchRegs() 2396315Sgblack@eecs.umich.edu { 2407720Sgblack@eecs.umich.edu _pcState = 0; 2416316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 2426315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2437400SAli.Saidi@ARM.com isa.clear(); 2446315Sgblack@eecs.umich.edu } 2452190SN/A 2462SN/A // 2472SN/A // New accessors for new decoder. 2482SN/A // 2492SN/A uint64_t readIntReg(int reg_idx) 2502SN/A { 2516313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2526323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2536418Sgblack@eecs.umich.edu uint64_t regVal = intRegs[flatIndex]; 2547601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2557601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 2566418Sgblack@eecs.umich.edu return regVal; 2572SN/A } 2582SN/A 2592455SN/A FloatReg readFloatReg(int reg_idx) 2602SN/A { 2616313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2626323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2637341Sgblack@eecs.umich.edu FloatReg regVal = floatRegs.f[flatIndex]; 2647601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 2657601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 2667341Sgblack@eecs.umich.edu return regVal; 2672SN/A } 2682SN/A 2692455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2702455SN/A { 2716313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2726323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2737341Sgblack@eecs.umich.edu FloatRegBits regVal = floatRegs.i[flatIndex]; 2747601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 2757601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 2767341Sgblack@eecs.umich.edu return regVal; 2772SN/A } 2782SN/A 2792SN/A void setIntReg(int reg_idx, uint64_t val) 2802SN/A { 2816313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2826323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2837601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 2847601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 2856316Sgblack@eecs.umich.edu intRegs[flatIndex] = val; 2862SN/A } 2872SN/A 2882455SN/A void setFloatReg(int reg_idx, FloatReg val) 2892SN/A { 2906313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2916323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2926315Sgblack@eecs.umich.edu floatRegs.f[flatIndex] = val; 2937601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 2947601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 2952SN/A } 2962SN/A 2972455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2982455SN/A { 2996313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 3006323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 3016315Sgblack@eecs.umich.edu floatRegs.i[flatIndex] = val; 3027601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 3037601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 3042SN/A } 3052SN/A 3067720Sgblack@eecs.umich.edu TheISA::PCState 3077720Sgblack@eecs.umich.edu pcState() 3082SN/A { 3097720Sgblack@eecs.umich.edu return _pcState; 3102SN/A } 3112SN/A 3127720Sgblack@eecs.umich.edu void 3137720Sgblack@eecs.umich.edu pcState(const TheISA::PCState &val) 3142190SN/A { 3157720Sgblack@eecs.umich.edu _pcState = val; 3162190SN/A } 3172190SN/A 3187720Sgblack@eecs.umich.edu Addr 3197720Sgblack@eecs.umich.edu instAddr() 3203276Sgblack@eecs.umich.edu { 3217720Sgblack@eecs.umich.edu return _pcState.instAddr(); 3223276Sgblack@eecs.umich.edu } 3233276Sgblack@eecs.umich.edu 3247720Sgblack@eecs.umich.edu Addr 3257720Sgblack@eecs.umich.edu nextInstAddr() 3263276Sgblack@eecs.umich.edu { 3277720Sgblack@eecs.umich.edu return _pcState.nextInstAddr(); 3283276Sgblack@eecs.umich.edu } 3293276Sgblack@eecs.umich.edu 3307720Sgblack@eecs.umich.edu MicroPC 3317720Sgblack@eecs.umich.edu microPC() 3322190SN/A { 3337720Sgblack@eecs.umich.edu return _pcState.microPC(); 3342251SN/A } 3352251SN/A 3367597Sminkyu.jeong@arm.com bool readPredicate() 3377597Sminkyu.jeong@arm.com { 3387597Sminkyu.jeong@arm.com return predicate; 3397597Sminkyu.jeong@arm.com } 3407597Sminkyu.jeong@arm.com 3417597Sminkyu.jeong@arm.com void setPredicate(bool val) 3427597Sminkyu.jeong@arm.com { 3437597Sminkyu.jeong@arm.com predicate = val; 3447597Sminkyu.jeong@arm.com } 3457597Sminkyu.jeong@arm.com 3466221Snate@binkert.org MiscReg 3476221Snate@binkert.org readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 3484172Ssaidi@eecs.umich.edu { 3496313Sgblack@eecs.umich.edu return isa.readMiscRegNoEffect(misc_reg); 3504172Ssaidi@eecs.umich.edu } 3514172Ssaidi@eecs.umich.edu 3526221Snate@binkert.org MiscReg 3536221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 3542SN/A { 3556313Sgblack@eecs.umich.edu return isa.readMiscReg(misc_reg, tc); 3562SN/A } 3572SN/A 3586221Snate@binkert.org void 3596221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3602SN/A { 3616313Sgblack@eecs.umich.edu return isa.setMiscRegNoEffect(misc_reg, val); 3622SN/A } 3632SN/A 3646221Snate@binkert.org void 3656221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3662SN/A { 3676313Sgblack@eecs.umich.edu return isa.setMiscReg(misc_reg, val, tc); 3686313Sgblack@eecs.umich.edu } 3696313Sgblack@eecs.umich.edu 3706313Sgblack@eecs.umich.edu int 3716313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 3726313Sgblack@eecs.umich.edu { 3736313Sgblack@eecs.umich.edu return isa.flattenIntIndex(reg); 3746313Sgblack@eecs.umich.edu } 3756313Sgblack@eecs.umich.edu 3766313Sgblack@eecs.umich.edu int 3776313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 3786313Sgblack@eecs.umich.edu { 3796313Sgblack@eecs.umich.edu return isa.flattenFloatIndex(reg); 3802SN/A } 3812SN/A 3822190SN/A unsigned readStCondFailures() { return storeCondFailures; } 3832190SN/A 3842190SN/A void setStCondFailures(unsigned sc_failures) 3852190SN/A { storeCondFailures = sc_failures; } 3862190SN/A 3871858SN/A#if !FULL_SYSTEM 3882561SN/A void syscall(int64_t callnum) 3892SN/A { 3902680SN/A process->syscall(callnum, tc); 3912SN/A } 3922SN/A#endif 3932SN/A}; 3942SN/A 3952SN/A 3962SN/A// for non-speculative execution context, spec_mode is always false 3972SN/Ainline bool 3982683Sktlim@umich.eduSimpleThread::misspeculating() 3992SN/A{ 4002SN/A return false; 4012SN/A} 4022SN/A 4032190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 404