simple_thread.hh revision 8232
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302SN/A */ 312SN/A 322683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 332683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 342SN/A 356313Sgblack@eecs.umich.edu#include "arch/isa.hh" 362190SN/A#include "arch/isa_traits.hh" 376329Sgblack@eecs.umich.edu#include "arch/registers.hh" 384997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 396316Sgblack@eecs.umich.edu#include "arch/types.hh" 406216Snate@binkert.org#include "base/types.hh" 411858SN/A#include "config/full_system.hh" 426658Snate@binkert.org#include "config/the_isa.hh" 432680SN/A#include "cpu/thread_context.hh" 442683Sktlim@umich.edu#include "cpu/thread_state.hh" 458232Snate@binkert.org#include "debug/FloatRegs.hh" 468232Snate@binkert.org#include "debug/IntRegs.hh" 472395SN/A#include "mem/request.hh" 482190SN/A#include "sim/byteswap.hh" 492188SN/A#include "sim/eventq.hh" 50217SN/A#include "sim/serialize.hh" 512SN/A 522SN/Aclass BaseCPU; 532SN/A 541858SN/A#if FULL_SYSTEM 552SN/A 561070SN/A#include "sim/system.hh" 571070SN/A 581917SN/Aclass FunctionProfile; 591917SN/Aclass ProfileNode; 602521SN/Aclass FunctionalPort; 612521SN/Aclass PhysicalPort; 622521SN/A 633548Sgblack@eecs.umich.edunamespace TheISA { 643548Sgblack@eecs.umich.edu namespace Kernel { 653548Sgblack@eecs.umich.edu class Statistics; 663548Sgblack@eecs.umich.edu }; 672330SN/A}; 682330SN/A 692SN/A#else // !FULL_SYSTEM 702SN/A 718229Snate@binkert.org#include "mem/page_table.hh" 72360SN/A#include "sim/process.hh" 732420SN/Aclass TranslatingPort; 742SN/A 752SN/A#endif // FULL_SYSTEM 762SN/A 772683Sktlim@umich.edu/** 782683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 792683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 802683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 812683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 822683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 832683Sktlim@umich.edu * the objects needed for simple functional execution, including a 842683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 852683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 862683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 872683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 882683Sktlim@umich.edu * all the necessary state for full architecture-level functional 892683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 902683Sktlim@umich.edu * examples. 912683Sktlim@umich.edu */ 922SN/A 932683Sktlim@umich.educlass SimpleThread : public ThreadState 942SN/A{ 952107SN/A protected: 962107SN/A typedef TheISA::MachInst MachInst; 972159SN/A typedef TheISA::MiscReg MiscReg; 982455SN/A typedef TheISA::FloatReg FloatReg; 992455SN/A typedef TheISA::FloatRegBits FloatRegBits; 1002SN/A public: 1012680SN/A typedef ThreadContext::Status Status; 1022SN/A 1032190SN/A protected: 1046315Sgblack@eecs.umich.edu union { 1056315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1066315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1076315Sgblack@eecs.umich.edu } floatRegs; 1086316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 1096313Sgblack@eecs.umich.edu TheISA::ISA isa; // one "instance" of the current ISA. 1102SN/A 1117720Sgblack@eecs.umich.edu TheISA::PCState _pcState; 1126324Sgblack@eecs.umich.edu 1137597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1147597Sminkyu.jeong@arm.com bool predicate; 1157597Sminkyu.jeong@arm.com 1162190SN/A public: 1172683Sktlim@umich.edu // pointer to CPU associated with this SimpleThread 1182SN/A BaseCPU *cpu; 1192SN/A 1202683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1212188SN/A 1222378SN/A System *system; 1232400SN/A 1246022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1256022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1262SN/A 1272683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1281858SN/A#if FULL_SYSTEM 1292683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1306022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 1312683Sktlim@umich.edu bool use_kernel_stats = true); 1322SN/A#else 1334997Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 1346331Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb); 1352SN/A#endif 1362862Sktlim@umich.edu 1372864Sktlim@umich.edu SimpleThread(); 1382862Sktlim@umich.edu 1392683Sktlim@umich.edu virtual ~SimpleThread(); 1402SN/A 1412680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 142180SN/A 1432SN/A void regStats(const std::string &name); 1442SN/A 1452864Sktlim@umich.edu void copyTC(ThreadContext *context); 1462864Sktlim@umich.edu 1472862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1482862Sktlim@umich.edu 149217SN/A void serialize(std::ostream &os); 150237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 151217SN/A 1522683Sktlim@umich.edu /*************************************************************** 1532683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1545891Sgblack@eecs.umich.edu * state. 1552683Sktlim@umich.edu **************************************************************/ 1562190SN/A 1572683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1582683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1592683Sktlim@umich.edu * CPU. 1602683Sktlim@umich.edu */ 1612680SN/A ThreadContext *getTC() { return tc; } 1622190SN/A 1635358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1645358Sgblack@eecs.umich.edu { 1655358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1665358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1675358Sgblack@eecs.umich.edu } 1685358Sgblack@eecs.umich.edu 1695358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1705358Sgblack@eecs.umich.edu { 1715358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1725358Sgblack@eecs.umich.edu } 1735358Sgblack@eecs.umich.edu 1745358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1755358Sgblack@eecs.umich.edu { 1765358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1775358Sgblack@eecs.umich.edu } 1785358Sgblack@eecs.umich.edu 1794997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1802683Sktlim@umich.edu void dumpFuncProfile(); 1812521SN/A 1825702Ssaidi@eecs.umich.edu Fault hwrei(); 1835702Ssaidi@eecs.umich.edu 1845702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1855702Ssaidi@eecs.umich.edu 1862683Sktlim@umich.edu#endif 1872SN/A 1882683Sktlim@umich.edu /******************************************* 1892683Sktlim@umich.edu * ThreadContext interface functions. 1902683Sktlim@umich.edu ******************************************/ 1912683Sktlim@umich.edu 1922683Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 1932683Sktlim@umich.edu 1946022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 1952683Sktlim@umich.edu 1966022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 1972683Sktlim@umich.edu 1984997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 1994997Sgblack@eecs.umich.edu 2005803Snate@binkert.org#if FULL_SYSTEM 2012683Sktlim@umich.edu FunctionalPort *getPhysPort() { return physPort; } 2022683Sktlim@umich.edu 2035499Ssaidi@eecs.umich.edu /** Return a virtual port. This port cannot be cached locally in an object. 2045499Ssaidi@eecs.umich.edu * After a CPU switch it may point to the wrong memory object which could 2055499Ssaidi@eecs.umich.edu * mean stale data. 2065499Ssaidi@eecs.umich.edu */ 2075499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return virtPort; } 2082SN/A#endif 2092SN/A 2102683Sktlim@umich.edu Status status() const { return _status; } 2112683Sktlim@umich.edu 2122683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2132683Sktlim@umich.edu 2142683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2152683Sktlim@umich.edu /// cycles to wait before beginning execution. 2162683Sktlim@umich.edu void activate(int delay = 1); 2172683Sktlim@umich.edu 2182683Sktlim@umich.edu /// Set the status to Suspended. 2192683Sktlim@umich.edu void suspend(); 2202683Sktlim@umich.edu 2212683Sktlim@umich.edu /// Set the status to Halted. 2222683Sktlim@umich.edu void halt(); 2232683Sktlim@umich.edu 2242SN/A virtual bool misspeculating(); 2252SN/A 2262683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2272190SN/A 2286315Sgblack@eecs.umich.edu void clearArchRegs() 2296315Sgblack@eecs.umich.edu { 2307720Sgblack@eecs.umich.edu _pcState = 0; 2316316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 2326315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2337400SAli.Saidi@ARM.com isa.clear(); 2346315Sgblack@eecs.umich.edu } 2352190SN/A 2362SN/A // 2372SN/A // New accessors for new decoder. 2382SN/A // 2392SN/A uint64_t readIntReg(int reg_idx) 2402SN/A { 2416313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2426323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2436418Sgblack@eecs.umich.edu uint64_t regVal = intRegs[flatIndex]; 2447601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2457601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 2466418Sgblack@eecs.umich.edu return regVal; 2472SN/A } 2482SN/A 2492455SN/A FloatReg readFloatReg(int reg_idx) 2502SN/A { 2516313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2526323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2537341Sgblack@eecs.umich.edu FloatReg regVal = floatRegs.f[flatIndex]; 2547601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 2557601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 2567341Sgblack@eecs.umich.edu return regVal; 2572SN/A } 2582SN/A 2592455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2602455SN/A { 2616313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2626323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2637341Sgblack@eecs.umich.edu FloatRegBits regVal = floatRegs.i[flatIndex]; 2647601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 2657601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 2667341Sgblack@eecs.umich.edu return regVal; 2672SN/A } 2682SN/A 2692SN/A void setIntReg(int reg_idx, uint64_t val) 2702SN/A { 2716313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2726323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2737601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 2747601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 2756316Sgblack@eecs.umich.edu intRegs[flatIndex] = val; 2762SN/A } 2772SN/A 2782455SN/A void setFloatReg(int reg_idx, FloatReg val) 2792SN/A { 2806313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2816323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2826315Sgblack@eecs.umich.edu floatRegs.f[flatIndex] = val; 2837601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 2847601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 2852SN/A } 2862SN/A 2872455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2882455SN/A { 2896313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2906323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2916315Sgblack@eecs.umich.edu floatRegs.i[flatIndex] = val; 2927601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 2937601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 2942SN/A } 2952SN/A 2967720Sgblack@eecs.umich.edu TheISA::PCState 2977720Sgblack@eecs.umich.edu pcState() 2982SN/A { 2997720Sgblack@eecs.umich.edu return _pcState; 3002SN/A } 3012SN/A 3027720Sgblack@eecs.umich.edu void 3037720Sgblack@eecs.umich.edu pcState(const TheISA::PCState &val) 3042190SN/A { 3057720Sgblack@eecs.umich.edu _pcState = val; 3062190SN/A } 3072190SN/A 3087720Sgblack@eecs.umich.edu Addr 3097720Sgblack@eecs.umich.edu instAddr() 3103276Sgblack@eecs.umich.edu { 3117720Sgblack@eecs.umich.edu return _pcState.instAddr(); 3123276Sgblack@eecs.umich.edu } 3133276Sgblack@eecs.umich.edu 3147720Sgblack@eecs.umich.edu Addr 3157720Sgblack@eecs.umich.edu nextInstAddr() 3163276Sgblack@eecs.umich.edu { 3177720Sgblack@eecs.umich.edu return _pcState.nextInstAddr(); 3183276Sgblack@eecs.umich.edu } 3193276Sgblack@eecs.umich.edu 3207720Sgblack@eecs.umich.edu MicroPC 3217720Sgblack@eecs.umich.edu microPC() 3222190SN/A { 3237720Sgblack@eecs.umich.edu return _pcState.microPC(); 3242251SN/A } 3252251SN/A 3267597Sminkyu.jeong@arm.com bool readPredicate() 3277597Sminkyu.jeong@arm.com { 3287597Sminkyu.jeong@arm.com return predicate; 3297597Sminkyu.jeong@arm.com } 3307597Sminkyu.jeong@arm.com 3317597Sminkyu.jeong@arm.com void setPredicate(bool val) 3327597Sminkyu.jeong@arm.com { 3337597Sminkyu.jeong@arm.com predicate = val; 3347597Sminkyu.jeong@arm.com } 3357597Sminkyu.jeong@arm.com 3366221Snate@binkert.org MiscReg 3376221Snate@binkert.org readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 3384172Ssaidi@eecs.umich.edu { 3396313Sgblack@eecs.umich.edu return isa.readMiscRegNoEffect(misc_reg); 3404172Ssaidi@eecs.umich.edu } 3414172Ssaidi@eecs.umich.edu 3426221Snate@binkert.org MiscReg 3436221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 3442SN/A { 3456313Sgblack@eecs.umich.edu return isa.readMiscReg(misc_reg, tc); 3462SN/A } 3472SN/A 3486221Snate@binkert.org void 3496221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3502SN/A { 3516313Sgblack@eecs.umich.edu return isa.setMiscRegNoEffect(misc_reg, val); 3522SN/A } 3532SN/A 3546221Snate@binkert.org void 3556221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3562SN/A { 3576313Sgblack@eecs.umich.edu return isa.setMiscReg(misc_reg, val, tc); 3586313Sgblack@eecs.umich.edu } 3596313Sgblack@eecs.umich.edu 3606313Sgblack@eecs.umich.edu int 3616313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 3626313Sgblack@eecs.umich.edu { 3636313Sgblack@eecs.umich.edu return isa.flattenIntIndex(reg); 3646313Sgblack@eecs.umich.edu } 3656313Sgblack@eecs.umich.edu 3666313Sgblack@eecs.umich.edu int 3676313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 3686313Sgblack@eecs.umich.edu { 3696313Sgblack@eecs.umich.edu return isa.flattenFloatIndex(reg); 3702SN/A } 3712SN/A 3722190SN/A unsigned readStCondFailures() { return storeCondFailures; } 3732190SN/A 3742190SN/A void setStCondFailures(unsigned sc_failures) 3752190SN/A { storeCondFailures = sc_failures; } 3762190SN/A 3771858SN/A#if !FULL_SYSTEM 3782561SN/A void syscall(int64_t callnum) 3792SN/A { 3802680SN/A process->syscall(callnum, tc); 3812SN/A } 3822SN/A#endif 3832SN/A}; 3842SN/A 3852SN/A 3862SN/A// for non-speculative execution context, spec_mode is always false 3872SN/Ainline bool 3882683Sktlim@umich.eduSimpleThread::misspeculating() 3892SN/A{ 3902SN/A return false; 3912SN/A} 3922SN/A 3932190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 394