simple_thread.hh revision 7601
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302SN/A */ 312SN/A 322683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 332683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 342SN/A 356313Sgblack@eecs.umich.edu#include "arch/isa.hh" 362190SN/A#include "arch/isa_traits.hh" 376329Sgblack@eecs.umich.edu#include "arch/registers.hh" 384997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 396316Sgblack@eecs.umich.edu#include "arch/types.hh" 406216Snate@binkert.org#include "base/types.hh" 411858SN/A#include "config/full_system.hh" 426658Snate@binkert.org#include "config/the_isa.hh" 432680SN/A#include "cpu/thread_context.hh" 442683Sktlim@umich.edu#include "cpu/thread_state.hh" 452395SN/A#include "mem/request.hh" 462190SN/A#include "sim/byteswap.hh" 472188SN/A#include "sim/eventq.hh" 48217SN/A#include "sim/serialize.hh" 492SN/A 502SN/Aclass BaseCPU; 512SN/A 521858SN/A#if FULL_SYSTEM 532SN/A 541070SN/A#include "sim/system.hh" 551070SN/A 561917SN/Aclass FunctionProfile; 571917SN/Aclass ProfileNode; 582521SN/Aclass FunctionalPort; 592521SN/Aclass PhysicalPort; 602521SN/A 613548Sgblack@eecs.umich.edunamespace TheISA { 623548Sgblack@eecs.umich.edu namespace Kernel { 633548Sgblack@eecs.umich.edu class Statistics; 643548Sgblack@eecs.umich.edu }; 652330SN/A}; 662330SN/A 672SN/A#else // !FULL_SYSTEM 682SN/A 69360SN/A#include "sim/process.hh" 702462SN/A#include "mem/page_table.hh" 712420SN/Aclass TranslatingPort; 722SN/A 732SN/A#endif // FULL_SYSTEM 742SN/A 752683Sktlim@umich.edu/** 762683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 772683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 782683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 792683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 802683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 812683Sktlim@umich.edu * the objects needed for simple functional execution, including a 822683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 832683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 842683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 852683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 862683Sktlim@umich.edu * all the necessary state for full architecture-level functional 872683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 882683Sktlim@umich.edu * examples. 892683Sktlim@umich.edu */ 902SN/A 912683Sktlim@umich.educlass SimpleThread : public ThreadState 922SN/A{ 932107SN/A protected: 942107SN/A typedef TheISA::MachInst MachInst; 952159SN/A typedef TheISA::MiscReg MiscReg; 962455SN/A typedef TheISA::FloatReg FloatReg; 972455SN/A typedef TheISA::FloatRegBits FloatRegBits; 982SN/A public: 992680SN/A typedef ThreadContext::Status Status; 1002SN/A 1012190SN/A protected: 1026315Sgblack@eecs.umich.edu union { 1036315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1046315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1056315Sgblack@eecs.umich.edu } floatRegs; 1066316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 1076313Sgblack@eecs.umich.edu TheISA::ISA isa; // one "instance" of the current ISA. 1082SN/A 1096324Sgblack@eecs.umich.edu /** The current microcode pc for the currently executing macro 1106324Sgblack@eecs.umich.edu * operation. 1116324Sgblack@eecs.umich.edu */ 1126324Sgblack@eecs.umich.edu MicroPC microPC; 1136324Sgblack@eecs.umich.edu 1146324Sgblack@eecs.umich.edu /** The next microcode pc for the currently executing macro 1156324Sgblack@eecs.umich.edu * operation. 1166324Sgblack@eecs.umich.edu */ 1176324Sgblack@eecs.umich.edu MicroPC nextMicroPC; 1186324Sgblack@eecs.umich.edu 1196324Sgblack@eecs.umich.edu /** The current pc. 1206324Sgblack@eecs.umich.edu */ 1216324Sgblack@eecs.umich.edu Addr PC; 1226324Sgblack@eecs.umich.edu 1236324Sgblack@eecs.umich.edu /** The next pc. 1246324Sgblack@eecs.umich.edu */ 1256324Sgblack@eecs.umich.edu Addr nextPC; 1266324Sgblack@eecs.umich.edu 1276324Sgblack@eecs.umich.edu /** The next next pc. 1286324Sgblack@eecs.umich.edu */ 1296324Sgblack@eecs.umich.edu Addr nextNPC; 1306324Sgblack@eecs.umich.edu 1317597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1327597Sminkyu.jeong@arm.com bool predicate; 1337597Sminkyu.jeong@arm.com 1342190SN/A public: 1352683Sktlim@umich.edu // pointer to CPU associated with this SimpleThread 1362SN/A BaseCPU *cpu; 1372SN/A 1382683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1392188SN/A 1402378SN/A System *system; 1412400SN/A 1426022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1436022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1442SN/A 1452683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1461858SN/A#if FULL_SYSTEM 1472683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1486022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 1492683Sktlim@umich.edu bool use_kernel_stats = true); 1502SN/A#else 1514997Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 1526331Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb); 1532SN/A#endif 1542862Sktlim@umich.edu 1552864Sktlim@umich.edu SimpleThread(); 1562862Sktlim@umich.edu 1572683Sktlim@umich.edu virtual ~SimpleThread(); 1582SN/A 1592680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 160180SN/A 1612SN/A void regStats(const std::string &name); 1622SN/A 1632864Sktlim@umich.edu void copyTC(ThreadContext *context); 1642864Sktlim@umich.edu 1652862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1662862Sktlim@umich.edu 167217SN/A void serialize(std::ostream &os); 168237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 169217SN/A 1702683Sktlim@umich.edu /*************************************************************** 1712683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1725891Sgblack@eecs.umich.edu * state. 1732683Sktlim@umich.edu **************************************************************/ 1742190SN/A 1752683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1762683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1772683Sktlim@umich.edu * CPU. 1782683Sktlim@umich.edu */ 1792680SN/A ThreadContext *getTC() { return tc; } 1802190SN/A 1815358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1825358Sgblack@eecs.umich.edu { 1835358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1845358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1855358Sgblack@eecs.umich.edu } 1865358Sgblack@eecs.umich.edu 1875358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1885358Sgblack@eecs.umich.edu { 1895358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1905358Sgblack@eecs.umich.edu } 1915358Sgblack@eecs.umich.edu 1925358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1935358Sgblack@eecs.umich.edu { 1945358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1955358Sgblack@eecs.umich.edu } 1965358Sgblack@eecs.umich.edu 1974997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1982683Sktlim@umich.edu void dumpFuncProfile(); 1992521SN/A 2005702Ssaidi@eecs.umich.edu Fault hwrei(); 2015702Ssaidi@eecs.umich.edu 2025702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 2035702Ssaidi@eecs.umich.edu 2042683Sktlim@umich.edu#endif 2052SN/A 2062683Sktlim@umich.edu /******************************************* 2072683Sktlim@umich.edu * ThreadContext interface functions. 2082683Sktlim@umich.edu ******************************************/ 2092683Sktlim@umich.edu 2102683Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 2112683Sktlim@umich.edu 2126022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 2132683Sktlim@umich.edu 2146022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 2152683Sktlim@umich.edu 2164997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2174997Sgblack@eecs.umich.edu 2185803Snate@binkert.org#if FULL_SYSTEM 2192683Sktlim@umich.edu FunctionalPort *getPhysPort() { return physPort; } 2202683Sktlim@umich.edu 2215499Ssaidi@eecs.umich.edu /** Return a virtual port. This port cannot be cached locally in an object. 2225499Ssaidi@eecs.umich.edu * After a CPU switch it may point to the wrong memory object which could 2235499Ssaidi@eecs.umich.edu * mean stale data. 2245499Ssaidi@eecs.umich.edu */ 2255499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return virtPort; } 2262SN/A#endif 2272SN/A 2282683Sktlim@umich.edu Status status() const { return _status; } 2292683Sktlim@umich.edu 2302683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2312683Sktlim@umich.edu 2322683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2332683Sktlim@umich.edu /// cycles to wait before beginning execution. 2342683Sktlim@umich.edu void activate(int delay = 1); 2352683Sktlim@umich.edu 2362683Sktlim@umich.edu /// Set the status to Suspended. 2372683Sktlim@umich.edu void suspend(); 2382683Sktlim@umich.edu 2392683Sktlim@umich.edu /// Set the status to Halted. 2402683Sktlim@umich.edu void halt(); 2412683Sktlim@umich.edu 2422SN/A virtual bool misspeculating(); 2432SN/A 2442532SN/A Fault instRead(RequestPtr &req) 245716SN/A { 2462378SN/A panic("instRead not implemented"); 2472378SN/A // return funcPhysMem->read(req, inst); 2482423SN/A return NoFault; 249716SN/A } 250716SN/A 2512683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2522190SN/A 2536315Sgblack@eecs.umich.edu void clearArchRegs() 2546315Sgblack@eecs.umich.edu { 2556324Sgblack@eecs.umich.edu microPC = 0; 2566324Sgblack@eecs.umich.edu nextMicroPC = 1; 2576324Sgblack@eecs.umich.edu PC = nextPC = nextNPC = 0; 2586316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 2596315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2607400SAli.Saidi@ARM.com isa.clear(); 2616315Sgblack@eecs.umich.edu } 2622190SN/A 2632SN/A // 2642SN/A // New accessors for new decoder. 2652SN/A // 2662SN/A uint64_t readIntReg(int reg_idx) 2672SN/A { 2686313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2696323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2706418Sgblack@eecs.umich.edu uint64_t regVal = intRegs[flatIndex]; 2717601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2727601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 2736418Sgblack@eecs.umich.edu return regVal; 2742SN/A } 2752SN/A 2762455SN/A FloatReg readFloatReg(int reg_idx) 2772SN/A { 2786313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2796323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2807341Sgblack@eecs.umich.edu FloatReg regVal = floatRegs.f[flatIndex]; 2817601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 2827601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 2837341Sgblack@eecs.umich.edu return regVal; 2842SN/A } 2852SN/A 2862455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2872455SN/A { 2886313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2896323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2907341Sgblack@eecs.umich.edu FloatRegBits regVal = floatRegs.i[flatIndex]; 2917601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 2927601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 2937341Sgblack@eecs.umich.edu return regVal; 2942SN/A } 2952SN/A 2962SN/A void setIntReg(int reg_idx, uint64_t val) 2972SN/A { 2986313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2996323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 3007601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 3017601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 3026316Sgblack@eecs.umich.edu intRegs[flatIndex] = val; 3032SN/A } 3042SN/A 3052455SN/A void setFloatReg(int reg_idx, FloatReg val) 3062SN/A { 3076313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 3086323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 3096315Sgblack@eecs.umich.edu floatRegs.f[flatIndex] = val; 3107601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 3117601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 3122SN/A } 3132SN/A 3142455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3152455SN/A { 3166313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 3176323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 3186315Sgblack@eecs.umich.edu floatRegs.i[flatIndex] = val; 3197601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 3207601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 3212SN/A } 3222SN/A 3232SN/A uint64_t readPC() 3242SN/A { 3256324Sgblack@eecs.umich.edu return PC; 3262SN/A } 3272SN/A 3282190SN/A void setPC(uint64_t val) 3292190SN/A { 3306324Sgblack@eecs.umich.edu PC = val; 3312190SN/A } 3322190SN/A 3333276Sgblack@eecs.umich.edu uint64_t readMicroPC() 3343276Sgblack@eecs.umich.edu { 3353276Sgblack@eecs.umich.edu return microPC; 3363276Sgblack@eecs.umich.edu } 3373276Sgblack@eecs.umich.edu 3383276Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) 3393276Sgblack@eecs.umich.edu { 3403276Sgblack@eecs.umich.edu microPC = val; 3413276Sgblack@eecs.umich.edu } 3423276Sgblack@eecs.umich.edu 3432190SN/A uint64_t readNextPC() 3442190SN/A { 3456324Sgblack@eecs.umich.edu return nextPC; 3462190SN/A } 3472190SN/A 3482SN/A void setNextPC(uint64_t val) 3492SN/A { 3506324Sgblack@eecs.umich.edu nextPC = val; 3512SN/A } 3522SN/A 3533276Sgblack@eecs.umich.edu uint64_t readNextMicroPC() 3543276Sgblack@eecs.umich.edu { 3553276Sgblack@eecs.umich.edu return nextMicroPC; 3563276Sgblack@eecs.umich.edu } 3573276Sgblack@eecs.umich.edu 3583276Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) 3593276Sgblack@eecs.umich.edu { 3603276Sgblack@eecs.umich.edu nextMicroPC = val; 3613276Sgblack@eecs.umich.edu } 3623276Sgblack@eecs.umich.edu 3632252SN/A uint64_t readNextNPC() 3642252SN/A { 3656324Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 3666324Sgblack@eecs.umich.edu return nextNPC; 3676324Sgblack@eecs.umich.edu#else 3686324Sgblack@eecs.umich.edu return nextPC + sizeof(TheISA::MachInst); 3696324Sgblack@eecs.umich.edu#endif 3702252SN/A } 3712252SN/A 3722251SN/A void setNextNPC(uint64_t val) 3732251SN/A { 3746324Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 3756324Sgblack@eecs.umich.edu nextNPC = val; 3766324Sgblack@eecs.umich.edu#endif 3772251SN/A } 3782251SN/A 3797597Sminkyu.jeong@arm.com bool readPredicate() 3807597Sminkyu.jeong@arm.com { 3817597Sminkyu.jeong@arm.com return predicate; 3827597Sminkyu.jeong@arm.com } 3837597Sminkyu.jeong@arm.com 3847597Sminkyu.jeong@arm.com void setPredicate(bool val) 3857597Sminkyu.jeong@arm.com { 3867597Sminkyu.jeong@arm.com predicate = val; 3877597Sminkyu.jeong@arm.com } 3887597Sminkyu.jeong@arm.com 3896221Snate@binkert.org MiscReg 3906221Snate@binkert.org readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 3914172Ssaidi@eecs.umich.edu { 3926313Sgblack@eecs.umich.edu return isa.readMiscRegNoEffect(misc_reg); 3934172Ssaidi@eecs.umich.edu } 3944172Ssaidi@eecs.umich.edu 3956221Snate@binkert.org MiscReg 3966221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 3972SN/A { 3986313Sgblack@eecs.umich.edu return isa.readMiscReg(misc_reg, tc); 3992SN/A } 4002SN/A 4016221Snate@binkert.org void 4026221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 4032SN/A { 4046313Sgblack@eecs.umich.edu return isa.setMiscRegNoEffect(misc_reg, val); 4052SN/A } 4062SN/A 4076221Snate@binkert.org void 4086221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 4092SN/A { 4106313Sgblack@eecs.umich.edu return isa.setMiscReg(misc_reg, val, tc); 4116313Sgblack@eecs.umich.edu } 4126313Sgblack@eecs.umich.edu 4136313Sgblack@eecs.umich.edu int 4146313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 4156313Sgblack@eecs.umich.edu { 4166313Sgblack@eecs.umich.edu return isa.flattenIntIndex(reg); 4176313Sgblack@eecs.umich.edu } 4186313Sgblack@eecs.umich.edu 4196313Sgblack@eecs.umich.edu int 4206313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 4216313Sgblack@eecs.umich.edu { 4226313Sgblack@eecs.umich.edu return isa.flattenFloatIndex(reg); 4232SN/A } 4242SN/A 4252190SN/A unsigned readStCondFailures() { return storeCondFailures; } 4262190SN/A 4272190SN/A void setStCondFailures(unsigned sc_failures) 4282190SN/A { storeCondFailures = sc_failures; } 4292190SN/A 4301858SN/A#if !FULL_SYSTEM 4312561SN/A void syscall(int64_t callnum) 4322SN/A { 4332680SN/A process->syscall(callnum, tc); 4342SN/A } 4352SN/A#endif 4362SN/A}; 4372SN/A 4382SN/A 4392SN/A// for non-speculative execution context, spec_mode is always false 4402SN/Ainline bool 4412683Sktlim@umich.eduSimpleThread::misspeculating() 4422SN/A{ 4432SN/A return false; 4442SN/A} 4452SN/A 4462190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 447