simple_thread.hh revision 676
12SN/A/* 22188SN/A * Copyright (c) 2003 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A */ 282665SN/A 292665SN/A#ifndef __EXEC_CONTEXT_HH__ 302SN/A#define __EXEC_CONTEXT_HH__ 312SN/A 322683Sktlim@umich.edu#include "sim/host.hh" 332683Sktlim@umich.edu#include "mem/mem_req.hh" 342SN/A#include "sim/serialize.hh" 356313Sgblack@eecs.umich.edu 362190SN/A// forward declaration: see functional_memory.hh 376329Sgblack@eecs.umich.educlass FunctionalMemory; 384997Sgblack@eecs.umich.educlass PhysicalMemory; 396316Sgblack@eecs.umich.educlass BaseCPU; 406216Snate@binkert.org 411858SN/A#ifdef FULL_SYSTEM 426658Snate@binkert.org 438541Sgblack@eecs.umich.edu#include "targetarch/alpha_memory.hh" 442680SN/Aclass MemoryController; 452683Sktlim@umich.edu 468232Snate@binkert.org#include "kern/tru64/kernel_stats.hh" 478232Snate@binkert.org#include "sim/system.hh" 482395SN/A#include "sim/sw_context.hh" 492190SN/A 502188SN/A#else // !FULL_SYSTEM 51217SN/A 522SN/A#include "sim/process.hh" 532SN/A 542SN/A#endif // FULL_SYSTEM 551858SN/A 562SN/A// 571070SN/A// The ExecContext object represents a functional context for 581070SN/A// instruction execution. It incorporates everything required for 591917SN/A// architecture-level functional simulation of a single thread. 601917SN/A// 612521SN/A 622521SN/Aclass ExecContext 632521SN/A{ 643548Sgblack@eecs.umich.edu public: 653548Sgblack@eecs.umich.edu enum Status 663548Sgblack@eecs.umich.edu { 673548Sgblack@eecs.umich.edu /// Initialized but not running yet. All CPUs start in 682330SN/A /// this state, but most transition to Active on cycle 1. 692330SN/A /// In MP or SMT systems, non-primary contexts will stay 702SN/A /// in this state until a thread is assigned to them. 712SN/A Unallocated, 728229Snate@binkert.org 73360SN/A /// Running. Instructions should be executed only when 742420SN/A /// the context is in this state. 752SN/A Active, 762SN/A 772SN/A /// Temporarily inactive. Entered while waiting for 782683Sktlim@umich.edu /// synchronization, etc. 792683Sktlim@umich.edu Suspended, 802683Sktlim@umich.edu 812683Sktlim@umich.edu /// Permanently shut down. Entered when target executes 822683Sktlim@umich.edu /// m5exit pseudo-instruction. When all contexts enter 832683Sktlim@umich.edu /// this state, the simulation will terminate. 842683Sktlim@umich.edu Halted 852683Sktlim@umich.edu }; 862683Sktlim@umich.edu 872683Sktlim@umich.edu private: 882683Sktlim@umich.edu Status _status; 892683Sktlim@umich.edu 902683Sktlim@umich.edu public: 912683Sktlim@umich.edu Status status() const { return _status; } 922683Sktlim@umich.edu 932SN/A /// Set the status to Active. Optional delay indicates number of 942683Sktlim@umich.edu /// cycles to wait before beginning execution. 952SN/A void activate(int delay = 1); 962107SN/A 972107SN/A /// Set the status to Suspended. 982159SN/A void suspend(); 992455SN/A 1002455SN/A /// Set the status to Unallocated. 1012SN/A void deallocate(); 1022680SN/A 1032SN/A /// Set the status to Halted. 1042190SN/A void halt(); 1056315Sgblack@eecs.umich.edu 1066315Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 1076315Sgblack@eecs.umich.edu public: 1086315Sgblack@eecs.umich.edu KernelStats kernelStats; 1096316Sgblack@eecs.umich.edu#endif 1106313Sgblack@eecs.umich.edu 1112SN/A public: 1127720Sgblack@eecs.umich.edu RegFile regs; // correct-path register context 1136324Sgblack@eecs.umich.edu 1147597Sminkyu.jeong@arm.com // pointer to CPU associated with this context 1157597Sminkyu.jeong@arm.com BaseCPU *cpu; 1167597Sminkyu.jeong@arm.com 1172190SN/A // Index of hardware thread context on the CPU that this represents. 1188357Sksewell@umich.edu int thread_num; 1198357Sksewell@umich.edu 1208357Sksewell@umich.edu // ID of this context w.r.t. the System or Process object to which 1218357Sksewell@umich.edu // it belongs. For full-system mode, this is the system CPU ID. 1228357Sksewell@umich.edu int cpu_id; 1232683Sktlim@umich.edu 1242SN/A#ifdef FULL_SYSTEM 1252SN/A 1262683Sktlim@umich.edu FunctionalMemory *mem; 1272188SN/A AlphaITB *itb; 1282378SN/A AlphaDTB *dtb; 1292400SN/A System *system; 1306022Sgblack@eecs.umich.edu 1316022Sgblack@eecs.umich.edu // the following two fields are redundant, since we can always 1322SN/A // look them up through the system pointer, but we'll leave them 1338541Sgblack@eecs.umich.edu // here for now for convenience 1348541Sgblack@eecs.umich.edu MemoryController *memCtrl; 1352683Sktlim@umich.edu PhysicalMemory *physmem; 1361858SN/A 1372683Sktlim@umich.edu SWContext *swCtx; 1386022Sgblack@eecs.umich.edu#else 1392683Sktlim@umich.edu Process *process; 1402SN/A 1414997Sgblack@eecs.umich.edu FunctionalMemory *mem; // functional storage for process address space 1426331Sgblack@eecs.umich.edu 1432SN/A // Address space ID. Note that this is used for TIMING cache 1442862Sktlim@umich.edu // simulation only; all functional memory accesses should use 1452864Sktlim@umich.edu // one of the FunctionalMemory pointers above. 1462862Sktlim@umich.edu short asid; 1472683Sktlim@umich.edu 1482SN/A#endif 1492680SN/A 150180SN/A /** 1512SN/A * Temporary storage to pass the source address from copy_load to 1522SN/A * copy_store. 1532864Sktlim@umich.edu * @todo Remove this temporary when we have a better way to do it. 1542864Sktlim@umich.edu */ 1552862Sktlim@umich.edu Addr copySrcAddr; 1562862Sktlim@umich.edu /** 157217SN/A * Temp storage for the physical source address of a copy. 158237SN/A * @todo Remove this temporary when we have a better way to do it. 159217SN/A */ 1602683Sktlim@umich.edu Addr copySrcPhysAddr; 1612683Sktlim@umich.edu 1625891Sgblack@eecs.umich.edu 1632683Sktlim@umich.edu /* 1642190SN/A * number of executed instructions, for matching with syscall trace 1652683Sktlim@umich.edu * points in EIO files. 1662683Sktlim@umich.edu */ 1672683Sktlim@umich.edu Counter func_exe_inst; 1682683Sktlim@umich.edu 1692680SN/A // 1702190SN/A // Count failed store conditionals so we can warn of apparent 1715358Sgblack@eecs.umich.edu // application deadlock situations. 1725358Sgblack@eecs.umich.edu unsigned storeCondFailures; 1735358Sgblack@eecs.umich.edu 1745358Sgblack@eecs.umich.edu // constructor: initialize context from given process structure 1755358Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 1765358Sgblack@eecs.umich.edu ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 1775358Sgblack@eecs.umich.edu AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); 1785358Sgblack@eecs.umich.edu#else 1795358Sgblack@eecs.umich.edu ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); 1805358Sgblack@eecs.umich.edu ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem, 1815358Sgblack@eecs.umich.edu int _asid); 1825358Sgblack@eecs.umich.edu#endif 1835358Sgblack@eecs.umich.edu virtual ~ExecContext() {} 1845358Sgblack@eecs.umich.edu 1855358Sgblack@eecs.umich.edu virtual void takeOverFrom(ExecContext *oldContext); 1865358Sgblack@eecs.umich.edu 1874997Sgblack@eecs.umich.edu void regStats(const std::string &name); 1882683Sktlim@umich.edu 1892521SN/A void serialize(std::ostream &os); 1905702Ssaidi@eecs.umich.edu void unserialize(Checkpoint *cp, const std::string §ion); 1915702Ssaidi@eecs.umich.edu 1925702Ssaidi@eecs.umich.edu#ifdef FULL_SYSTEM 1935702Ssaidi@eecs.umich.edu bool validInstAddr(Addr addr) { return true; } 1942683Sktlim@umich.edu bool validDataAddr(Addr addr) { return true; } 1952SN/A int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); } 1962683Sktlim@umich.edu int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); } 1972683Sktlim@umich.edu 1982683Sktlim@umich.edu Fault translateInstReq(MemReqPtr &req) 1992683Sktlim@umich.edu { 2002683Sktlim@umich.edu return itb->translate(req); 2012683Sktlim@umich.edu } 2026022Sgblack@eecs.umich.edu 2032683Sktlim@umich.edu Fault translateDataReadReq(MemReqPtr &req) 2046022Sgblack@eecs.umich.edu { 2052683Sktlim@umich.edu return dtb->translate(req, false); 2068541Sgblack@eecs.umich.edu } 2078541Sgblack@eecs.umich.edu 2084997Sgblack@eecs.umich.edu Fault translateDataWriteReq(MemReqPtr &req) 2094997Sgblack@eecs.umich.edu { 2108761Sgblack@eecs.umich.edu return dtb->translate(req, true); 2118761Sgblack@eecs.umich.edu } 2125499Ssaidi@eecs.umich.edu 2135499Ssaidi@eecs.umich.edu#else 2145499Ssaidi@eecs.umich.edu bool validInstAddr(Addr addr) 2155499Ssaidi@eecs.umich.edu { return process->validInstAddr(addr); } 2165499Ssaidi@eecs.umich.edu 2178754Sgblack@eecs.umich.edu bool validDataAddr(Addr addr) 2182683Sktlim@umich.edu { return process->validDataAddr(addr); } 2192683Sktlim@umich.edu 2202683Sktlim@umich.edu int getInstAsid() { return asid; } 2212683Sktlim@umich.edu int getDataAsid() { return asid; } 2222683Sktlim@umich.edu 2232683Sktlim@umich.edu Fault dummyTranslation(MemReqPtr &req) 2242683Sktlim@umich.edu { 2252683Sktlim@umich.edu#if 0 2262683Sktlim@umich.edu assert((req->vaddr >> 48 & 0xffff) == 0); 2272683Sktlim@umich.edu#endif 2282683Sktlim@umich.edu 2292683Sktlim@umich.edu // put the asid in the upper 16 bits of the paddr 2302683Sktlim@umich.edu req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); 2312683Sktlim@umich.edu req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; 2322SN/A return No_Fault; 2332SN/A } 2342683Sktlim@umich.edu Fault translateInstReq(MemReqPtr &req) 2352190SN/A { 2366315Sgblack@eecs.umich.edu return dummyTranslation(req); 2376315Sgblack@eecs.umich.edu } 2387720Sgblack@eecs.umich.edu Fault translateDataReadReq(MemReqPtr &req) 2396316Sgblack@eecs.umich.edu { 2406315Sgblack@eecs.umich.edu return dummyTranslation(req); 2417400SAli.Saidi@ARM.com } 2426315Sgblack@eecs.umich.edu Fault translateDataWriteReq(MemReqPtr &req) 2432190SN/A { 2442SN/A return dummyTranslation(req); 2452SN/A } 2462SN/A 2472SN/A#endif 2482SN/A 2496313Sgblack@eecs.umich.edu template <class T> 2506323Sgblack@eecs.umich.edu Fault read(MemReqPtr &req, T &data) 2516418Sgblack@eecs.umich.edu { 2527601Sminkyu.jeong@arm.com#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) 2537601Sminkyu.jeong@arm.com if (req->flags & LOCKED) { 2546418Sgblack@eecs.umich.edu MiscRegFile *cregs = &req->xc->regs.miscRegs; 2552SN/A cregs->lock_addr = req->paddr; 2562SN/A cregs->lock_flag = true; 2572455SN/A } 2582SN/A#endif 2596313Sgblack@eecs.umich.edu return mem->read(req, data); 2606323Sgblack@eecs.umich.edu } 2617341Sgblack@eecs.umich.edu 2627601Sminkyu.jeong@arm.com template <class T> 2637601Sminkyu.jeong@arm.com Fault write(MemReqPtr &req, T &data) 2647341Sgblack@eecs.umich.edu { 2652SN/A#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) 2662SN/A 2672455SN/A MiscRegFile *cregs; 2682455SN/A 2696313Sgblack@eecs.umich.edu // If this is a store conditional, act appropriately 2706323Sgblack@eecs.umich.edu if (req->flags & LOCKED) { 2717341Sgblack@eecs.umich.edu cregs = &req->xc->regs.miscRegs; 2727601Sminkyu.jeong@arm.com 2737601Sminkyu.jeong@arm.com if (req->flags & UNCACHEABLE) { 2747341Sgblack@eecs.umich.edu // Don't update result register (see stq_c in isa_desc) 2752SN/A req->result = 2; 2762SN/A req->xc->storeCondFailures = 0;//Needed? [RGD] 2772SN/A } else { 2782SN/A req->result = cregs->lock_flag; 2796313Sgblack@eecs.umich.edu if (!cregs->lock_flag || 2806323Sgblack@eecs.umich.edu ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { 2817601Sminkyu.jeong@arm.com cregs->lock_flag = false; 2827601Sminkyu.jeong@arm.com if (((++req->xc->storeCondFailures) % 100000) == 0) { 2836316Sgblack@eecs.umich.edu std::cerr << "Warning: " 2842SN/A << req->xc->storeCondFailures 2852SN/A << " consecutive store conditional failures " 2862455SN/A << "on cpu " << req->xc->cpu_id 2872SN/A << std::endl; 2886313Sgblack@eecs.umich.edu } 2896323Sgblack@eecs.umich.edu return No_Fault; 2906315Sgblack@eecs.umich.edu } 2917601Sminkyu.jeong@arm.com else req->xc->storeCondFailures = 0; 2927601Sminkyu.jeong@arm.com } 2932SN/A } 2942SN/A 2952455SN/A // Need to clear any locked flags on other proccessors for 2962455SN/A // this address. Only do this for succsful Store Conditionals 2976313Sgblack@eecs.umich.edu // and all other stores (WH64?). Unsuccessful Store 2986323Sgblack@eecs.umich.edu // Conditionals would have returned above, and wouldn't fall 2996315Sgblack@eecs.umich.edu // through. 3007601Sminkyu.jeong@arm.com for (int i = 0; i < system->execContexts.size(); i++){ 3017601Sminkyu.jeong@arm.com cregs = &system->execContexts[i]->regs.miscRegs; 3022SN/A if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { 3032SN/A cregs->lock_flag = false; 3047720Sgblack@eecs.umich.edu } 3057720Sgblack@eecs.umich.edu } 3062SN/A 3077720Sgblack@eecs.umich.edu#endif 3082SN/A return mem->write(req, data); 3092SN/A } 3107720Sgblack@eecs.umich.edu 3117720Sgblack@eecs.umich.edu virtual bool misspeculating(); 3122190SN/A 3137720Sgblack@eecs.umich.edu 3142190SN/A // 3152190SN/A // New accessors for new decoder. 3167720Sgblack@eecs.umich.edu // 3177720Sgblack@eecs.umich.edu uint64_t readIntReg(int reg_idx) 3183276Sgblack@eecs.umich.edu { 3197720Sgblack@eecs.umich.edu return regs.intRegFile[reg_idx]; 3203276Sgblack@eecs.umich.edu } 3213276Sgblack@eecs.umich.edu 3227720Sgblack@eecs.umich.edu float readFloatRegSingle(int reg_idx) 3237720Sgblack@eecs.umich.edu { 3243276Sgblack@eecs.umich.edu return (float)regs.floatRegFile.d[reg_idx]; 3257720Sgblack@eecs.umich.edu } 3263276Sgblack@eecs.umich.edu 3273276Sgblack@eecs.umich.edu double readFloatRegDouble(int reg_idx) 3287720Sgblack@eecs.umich.edu { 3297720Sgblack@eecs.umich.edu return regs.floatRegFile.d[reg_idx]; 3302190SN/A } 3317720Sgblack@eecs.umich.edu 3322251SN/A uint64_t readFloatRegInt(int reg_idx) 3332251SN/A { 3347597Sminkyu.jeong@arm.com return regs.floatRegFile.q[reg_idx]; 3357597Sminkyu.jeong@arm.com } 3367597Sminkyu.jeong@arm.com 3377597Sminkyu.jeong@arm.com void setIntReg(int reg_idx, uint64_t val) 3387597Sminkyu.jeong@arm.com { 3397597Sminkyu.jeong@arm.com regs.intRegFile[reg_idx] = val; 3407597Sminkyu.jeong@arm.com } 3417597Sminkyu.jeong@arm.com 3427597Sminkyu.jeong@arm.com void setFloatRegSingle(int reg_idx, float val) 3437597Sminkyu.jeong@arm.com { 3446221Snate@binkert.org regs.floatRegFile.d[reg_idx] = (double)val; 3456221Snate@binkert.org } 3464172Ssaidi@eecs.umich.edu 3476313Sgblack@eecs.umich.edu void setFloatRegDouble(int reg_idx, double val) 3484172Ssaidi@eecs.umich.edu { 3494172Ssaidi@eecs.umich.edu regs.floatRegFile.d[reg_idx] = val; 3506221Snate@binkert.org } 3516221Snate@binkert.org 3522SN/A void setFloatRegInt(int reg_idx, uint64_t val) 3536313Sgblack@eecs.umich.edu { 3542SN/A regs.floatRegFile.q[reg_idx] = val; 3552SN/A } 3566221Snate@binkert.org 3576221Snate@binkert.org uint64_t readPC() 3582SN/A { 3596313Sgblack@eecs.umich.edu return regs.pc; 3602SN/A } 3612SN/A 3626221Snate@binkert.org void setNextPC(uint64_t val) 3636221Snate@binkert.org { 3642SN/A regs.npc = val; 3656313Sgblack@eecs.umich.edu } 3666313Sgblack@eecs.umich.edu 3676313Sgblack@eecs.umich.edu uint64_t readUniq() 3686313Sgblack@eecs.umich.edu { 3696313Sgblack@eecs.umich.edu return regs.miscRegs.uniq; 3706313Sgblack@eecs.umich.edu } 3716313Sgblack@eecs.umich.edu 3726313Sgblack@eecs.umich.edu void setUniq(uint64_t val) 3736313Sgblack@eecs.umich.edu { 3746313Sgblack@eecs.umich.edu regs.miscRegs.uniq = val; 3756313Sgblack@eecs.umich.edu } 3766313Sgblack@eecs.umich.edu 3776313Sgblack@eecs.umich.edu uint64_t readFpcr() 3782SN/A { 3792SN/A return regs.miscRegs.fpcr; 3802190SN/A } 3812190SN/A 3822190SN/A void setFpcr(uint64_t val) 3832190SN/A { 3842190SN/A regs.miscRegs.fpcr = val; 3851858SN/A } 3862561SN/A 3872SN/A#ifdef FULL_SYSTEM 3882680SN/A uint64_t readIpr(int idx, Fault &fault); 3892SN/A Fault setIpr(int idx, uint64_t val); 3902SN/A Fault hwrei(); 3912SN/A void ev5_trap(Fault fault); 3922SN/A bool simPalCheck(int palFunc); 3932SN/A#endif 3942SN/A 3952SN/A#ifndef FULL_SYSTEM 3962683Sktlim@umich.edu IntReg getSyscallArg(int i) 3972SN/A { 3982SN/A return regs.intRegFile[ArgumentReg0 + i]; 3992SN/A } 4002SN/A 4012190SN/A // used to shift args for indirect syscall 402 void setSyscallArg(int i, IntReg val) 403 { 404 regs.intRegFile[ArgumentReg0 + i] = val; 405 } 406 407 void setSyscallReturn(int64_t return_value) 408 { 409 // check for error condition. Alpha syscall convention is to 410 // indicate success/failure in reg a3 (r19) and put the 411 // return value itself in the standard return value reg (v0). 412 const int RegA3 = 19; // only place this is used 413 if (return_value >= 0) { 414 // no error 415 regs.intRegFile[RegA3] = 0; 416 regs.intRegFile[ReturnValueReg] = return_value; 417 } else { 418 // got an error, return details 419 regs.intRegFile[RegA3] = (IntReg) -1; 420 regs.intRegFile[ReturnValueReg] = -return_value; 421 } 422 } 423 424 void syscall() 425 { 426 process->syscall(this); 427 } 428#endif 429}; 430 431 432// for non-speculative execution context, spec_mode is always false 433inline bool 434ExecContext::misspeculating() 435{ 436 return false; 437} 438 439#endif // __EXEC_CONTEXT_HH__ 440