simple_thread.hh revision 6329
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302SN/A */ 312SN/A 322683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 332683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 342SN/A 356313Sgblack@eecs.umich.edu#include "arch/isa.hh" 362190SN/A#include "arch/isa_traits.hh" 376329Sgblack@eecs.umich.edu#include "arch/registers.hh" 384997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 396316Sgblack@eecs.umich.edu#include "arch/types.hh" 406216Snate@binkert.org#include "base/types.hh" 411858SN/A#include "config/full_system.hh" 422680SN/A#include "cpu/thread_context.hh" 432683Sktlim@umich.edu#include "cpu/thread_state.hh" 442395SN/A#include "mem/request.hh" 452190SN/A#include "sim/byteswap.hh" 462188SN/A#include "sim/eventq.hh" 47217SN/A#include "sim/serialize.hh" 482SN/A 492SN/Aclass BaseCPU; 502SN/A 511858SN/A#if FULL_SYSTEM 522SN/A 531070SN/A#include "sim/system.hh" 541070SN/A 551917SN/Aclass FunctionProfile; 561917SN/Aclass ProfileNode; 572521SN/Aclass FunctionalPort; 582521SN/Aclass PhysicalPort; 592521SN/A 603548Sgblack@eecs.umich.edunamespace TheISA { 613548Sgblack@eecs.umich.edu namespace Kernel { 623548Sgblack@eecs.umich.edu class Statistics; 633548Sgblack@eecs.umich.edu }; 642330SN/A}; 652330SN/A 662SN/A#else // !FULL_SYSTEM 672SN/A 68360SN/A#include "sim/process.hh" 692462SN/A#include "mem/page_table.hh" 702420SN/Aclass TranslatingPort; 712SN/A 722SN/A#endif // FULL_SYSTEM 732SN/A 742683Sktlim@umich.edu/** 752683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 762683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 772683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 782683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 792683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 802683Sktlim@umich.edu * the objects needed for simple functional execution, including a 812683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 822683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 832683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 842683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 852683Sktlim@umich.edu * all the necessary state for full architecture-level functional 862683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 872683Sktlim@umich.edu * examples. 882683Sktlim@umich.edu */ 892SN/A 902683Sktlim@umich.educlass SimpleThread : public ThreadState 912SN/A{ 922107SN/A protected: 932107SN/A typedef TheISA::MachInst MachInst; 942159SN/A typedef TheISA::MiscReg MiscReg; 952455SN/A typedef TheISA::FloatReg FloatReg; 962455SN/A typedef TheISA::FloatRegBits FloatRegBits; 972SN/A public: 982680SN/A typedef ThreadContext::Status Status; 992SN/A 1002190SN/A protected: 1016315Sgblack@eecs.umich.edu union { 1026315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1036315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1046315Sgblack@eecs.umich.edu } floatRegs; 1056316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 1066313Sgblack@eecs.umich.edu TheISA::ISA isa; // one "instance" of the current ISA. 1072SN/A 1086324Sgblack@eecs.umich.edu /** The current microcode pc for the currently executing macro 1096324Sgblack@eecs.umich.edu * operation. 1106324Sgblack@eecs.umich.edu */ 1116324Sgblack@eecs.umich.edu MicroPC microPC; 1126324Sgblack@eecs.umich.edu 1136324Sgblack@eecs.umich.edu /** The next microcode pc for the currently executing macro 1146324Sgblack@eecs.umich.edu * operation. 1156324Sgblack@eecs.umich.edu */ 1166324Sgblack@eecs.umich.edu MicroPC nextMicroPC; 1176324Sgblack@eecs.umich.edu 1186324Sgblack@eecs.umich.edu /** The current pc. 1196324Sgblack@eecs.umich.edu */ 1206324Sgblack@eecs.umich.edu Addr PC; 1216324Sgblack@eecs.umich.edu 1226324Sgblack@eecs.umich.edu /** The next pc. 1236324Sgblack@eecs.umich.edu */ 1246324Sgblack@eecs.umich.edu Addr nextPC; 1256324Sgblack@eecs.umich.edu 1266324Sgblack@eecs.umich.edu /** The next next pc. 1276324Sgblack@eecs.umich.edu */ 1286324Sgblack@eecs.umich.edu Addr nextNPC; 1296324Sgblack@eecs.umich.edu 1302190SN/A public: 1312683Sktlim@umich.edu // pointer to CPU associated with this SimpleThread 1322SN/A BaseCPU *cpu; 1332SN/A 1342683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1352188SN/A 1362378SN/A System *system; 1372400SN/A 1386022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1396022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1402SN/A 1412683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1421858SN/A#if FULL_SYSTEM 1432683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1446022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 1452683Sktlim@umich.edu bool use_kernel_stats = true); 1462SN/A#else 1474997Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 1486022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid); 1492SN/A#endif 1502862Sktlim@umich.edu 1512864Sktlim@umich.edu SimpleThread(); 1522862Sktlim@umich.edu 1532683Sktlim@umich.edu virtual ~SimpleThread(); 1542SN/A 1552680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 156180SN/A 1572SN/A void regStats(const std::string &name); 1582SN/A 1592864Sktlim@umich.edu void copyTC(ThreadContext *context); 1602864Sktlim@umich.edu 1612862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1622862Sktlim@umich.edu 163217SN/A void serialize(std::ostream &os); 164237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 165217SN/A 1662683Sktlim@umich.edu /*************************************************************** 1672683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1685891Sgblack@eecs.umich.edu * state. 1692683Sktlim@umich.edu **************************************************************/ 1702190SN/A 1712683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1722683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1732683Sktlim@umich.edu * CPU. 1742683Sktlim@umich.edu */ 1752680SN/A ThreadContext *getTC() { return tc; } 1762190SN/A 1775358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1785358Sgblack@eecs.umich.edu { 1795358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1805358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1815358Sgblack@eecs.umich.edu } 1825358Sgblack@eecs.umich.edu 1835358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1845358Sgblack@eecs.umich.edu { 1855358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1865358Sgblack@eecs.umich.edu } 1875358Sgblack@eecs.umich.edu 1885358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1895358Sgblack@eecs.umich.edu { 1905358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1915358Sgblack@eecs.umich.edu } 1925358Sgblack@eecs.umich.edu 1934997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1946313Sgblack@eecs.umich.edu int getInstAsid() { return isa.instAsid(); } 1956313Sgblack@eecs.umich.edu int getDataAsid() { return isa.dataAsid(); } 1964997Sgblack@eecs.umich.edu 1972683Sktlim@umich.edu void dumpFuncProfile(); 1982521SN/A 1995702Ssaidi@eecs.umich.edu Fault hwrei(); 2005702Ssaidi@eecs.umich.edu 2015702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 2025702Ssaidi@eecs.umich.edu 2032683Sktlim@umich.edu#endif 2042SN/A 2052683Sktlim@umich.edu /******************************************* 2062683Sktlim@umich.edu * ThreadContext interface functions. 2072683Sktlim@umich.edu ******************************************/ 2082683Sktlim@umich.edu 2092683Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 2102683Sktlim@umich.edu 2116022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 2122683Sktlim@umich.edu 2136022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 2142683Sktlim@umich.edu 2154997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2164997Sgblack@eecs.umich.edu 2175803Snate@binkert.org#if FULL_SYSTEM 2182683Sktlim@umich.edu FunctionalPort *getPhysPort() { return physPort; } 2192683Sktlim@umich.edu 2205499Ssaidi@eecs.umich.edu /** Return a virtual port. This port cannot be cached locally in an object. 2215499Ssaidi@eecs.umich.edu * After a CPU switch it may point to the wrong memory object which could 2225499Ssaidi@eecs.umich.edu * mean stale data. 2235499Ssaidi@eecs.umich.edu */ 2245499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return virtPort; } 2252SN/A#endif 2262SN/A 2272683Sktlim@umich.edu Status status() const { return _status; } 2282683Sktlim@umich.edu 2292683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2302683Sktlim@umich.edu 2312683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2322683Sktlim@umich.edu /// cycles to wait before beginning execution. 2332683Sktlim@umich.edu void activate(int delay = 1); 2342683Sktlim@umich.edu 2352683Sktlim@umich.edu /// Set the status to Suspended. 2362683Sktlim@umich.edu void suspend(); 2372683Sktlim@umich.edu 2382683Sktlim@umich.edu /// Set the status to Halted. 2392683Sktlim@umich.edu void halt(); 2402683Sktlim@umich.edu 2412SN/A virtual bool misspeculating(); 2422SN/A 2432532SN/A Fault instRead(RequestPtr &req) 244716SN/A { 2452378SN/A panic("instRead not implemented"); 2462378SN/A // return funcPhysMem->read(req, inst); 2472423SN/A return NoFault; 248716SN/A } 249716SN/A 2502683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2512190SN/A 2526315Sgblack@eecs.umich.edu void clearArchRegs() 2536315Sgblack@eecs.umich.edu { 2546324Sgblack@eecs.umich.edu microPC = 0; 2556324Sgblack@eecs.umich.edu nextMicroPC = 1; 2566324Sgblack@eecs.umich.edu PC = nextPC = nextNPC = 0; 2576316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 2586315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2596315Sgblack@eecs.umich.edu } 2602190SN/A 2612SN/A // 2622SN/A // New accessors for new decoder. 2632SN/A // 2642SN/A uint64_t readIntReg(int reg_idx) 2652SN/A { 2666313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2676323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2686316Sgblack@eecs.umich.edu return intRegs[flatIndex]; 2692SN/A } 2702SN/A 2712455SN/A FloatReg readFloatReg(int reg_idx) 2722SN/A { 2736313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2746323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2756315Sgblack@eecs.umich.edu return floatRegs.f[flatIndex]; 2762SN/A } 2772SN/A 2782455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2792455SN/A { 2806313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2816323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2826315Sgblack@eecs.umich.edu return floatRegs.i[flatIndex]; 2832SN/A } 2842SN/A 2852SN/A void setIntReg(int reg_idx, uint64_t val) 2862SN/A { 2876313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2886323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2896316Sgblack@eecs.umich.edu intRegs[flatIndex] = val; 2902SN/A } 2912SN/A 2922455SN/A void setFloatReg(int reg_idx, FloatReg val) 2932SN/A { 2946313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2956323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2966315Sgblack@eecs.umich.edu floatRegs.f[flatIndex] = val; 2972SN/A } 2982SN/A 2992455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3002455SN/A { 3016313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 3026323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 3036315Sgblack@eecs.umich.edu floatRegs.i[flatIndex] = val; 3042SN/A } 3052SN/A 3062SN/A uint64_t readPC() 3072SN/A { 3086324Sgblack@eecs.umich.edu return PC; 3092SN/A } 3102SN/A 3112190SN/A void setPC(uint64_t val) 3122190SN/A { 3136324Sgblack@eecs.umich.edu PC = val; 3142190SN/A } 3152190SN/A 3163276Sgblack@eecs.umich.edu uint64_t readMicroPC() 3173276Sgblack@eecs.umich.edu { 3183276Sgblack@eecs.umich.edu return microPC; 3193276Sgblack@eecs.umich.edu } 3203276Sgblack@eecs.umich.edu 3213276Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) 3223276Sgblack@eecs.umich.edu { 3233276Sgblack@eecs.umich.edu microPC = val; 3243276Sgblack@eecs.umich.edu } 3253276Sgblack@eecs.umich.edu 3262190SN/A uint64_t readNextPC() 3272190SN/A { 3286324Sgblack@eecs.umich.edu return nextPC; 3292190SN/A } 3302190SN/A 3312SN/A void setNextPC(uint64_t val) 3322SN/A { 3336324Sgblack@eecs.umich.edu nextPC = val; 3342SN/A } 3352SN/A 3363276Sgblack@eecs.umich.edu uint64_t readNextMicroPC() 3373276Sgblack@eecs.umich.edu { 3383276Sgblack@eecs.umich.edu return nextMicroPC; 3393276Sgblack@eecs.umich.edu } 3403276Sgblack@eecs.umich.edu 3413276Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) 3423276Sgblack@eecs.umich.edu { 3433276Sgblack@eecs.umich.edu nextMicroPC = val; 3443276Sgblack@eecs.umich.edu } 3453276Sgblack@eecs.umich.edu 3462252SN/A uint64_t readNextNPC() 3472252SN/A { 3486324Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 3496324Sgblack@eecs.umich.edu return nextNPC; 3506324Sgblack@eecs.umich.edu#else 3516324Sgblack@eecs.umich.edu return nextPC + sizeof(TheISA::MachInst); 3526324Sgblack@eecs.umich.edu#endif 3532252SN/A } 3542252SN/A 3552251SN/A void setNextNPC(uint64_t val) 3562251SN/A { 3576324Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 3586324Sgblack@eecs.umich.edu nextNPC = val; 3596324Sgblack@eecs.umich.edu#endif 3602251SN/A } 3612251SN/A 3626221Snate@binkert.org MiscReg 3636221Snate@binkert.org readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 3644172Ssaidi@eecs.umich.edu { 3656313Sgblack@eecs.umich.edu return isa.readMiscRegNoEffect(misc_reg); 3664172Ssaidi@eecs.umich.edu } 3674172Ssaidi@eecs.umich.edu 3686221Snate@binkert.org MiscReg 3696221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 3702SN/A { 3716313Sgblack@eecs.umich.edu return isa.readMiscReg(misc_reg, tc); 3722SN/A } 3732SN/A 3746221Snate@binkert.org void 3756221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3762SN/A { 3776313Sgblack@eecs.umich.edu return isa.setMiscRegNoEffect(misc_reg, val); 3782SN/A } 3792SN/A 3806221Snate@binkert.org void 3816221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3822SN/A { 3836313Sgblack@eecs.umich.edu return isa.setMiscReg(misc_reg, val, tc); 3846313Sgblack@eecs.umich.edu } 3856313Sgblack@eecs.umich.edu 3866313Sgblack@eecs.umich.edu int 3876313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 3886313Sgblack@eecs.umich.edu { 3896313Sgblack@eecs.umich.edu return isa.flattenIntIndex(reg); 3906313Sgblack@eecs.umich.edu } 3916313Sgblack@eecs.umich.edu 3926313Sgblack@eecs.umich.edu int 3936313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 3946313Sgblack@eecs.umich.edu { 3956313Sgblack@eecs.umich.edu return isa.flattenFloatIndex(reg); 3962SN/A } 3972SN/A 3982190SN/A unsigned readStCondFailures() { return storeCondFailures; } 3992190SN/A 4002190SN/A void setStCondFailures(unsigned sc_failures) 4012190SN/A { storeCondFailures = sc_failures; } 4022190SN/A 4031858SN/A#if !FULL_SYSTEM 4042561SN/A void syscall(int64_t callnum) 4052SN/A { 4062680SN/A process->syscall(callnum, tc); 4072SN/A } 4082SN/A#endif 4092SN/A}; 4102SN/A 4112SN/A 4122SN/A// for non-speculative execution context, spec_mode is always false 4132SN/Ainline bool 4142683Sktlim@umich.eduSimpleThread::misspeculating() 4152SN/A{ 4162SN/A return false; 4172SN/A} 4182SN/A 4192190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 420