simple_thread.hh revision 6324
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302SN/A */ 312SN/A 322683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 332683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 342SN/A 356313Sgblack@eecs.umich.edu#include "arch/isa.hh" 362190SN/A#include "arch/isa_traits.hh" 373776Sgblack@eecs.umich.edu#include "arch/regfile.hh" 384997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 396316Sgblack@eecs.umich.edu#include "arch/types.hh" 406216Snate@binkert.org#include "base/types.hh" 411858SN/A#include "config/full_system.hh" 422680SN/A#include "cpu/thread_context.hh" 432683Sktlim@umich.edu#include "cpu/thread_state.hh" 442395SN/A#include "mem/request.hh" 452190SN/A#include "sim/byteswap.hh" 462188SN/A#include "sim/eventq.hh" 47217SN/A#include "sim/serialize.hh" 482SN/A 492SN/Aclass BaseCPU; 502SN/A 511858SN/A#if FULL_SYSTEM 522SN/A 531070SN/A#include "sim/system.hh" 541070SN/A 551917SN/Aclass FunctionProfile; 561917SN/Aclass ProfileNode; 572521SN/Aclass FunctionalPort; 582521SN/Aclass PhysicalPort; 592521SN/A 603548Sgblack@eecs.umich.edunamespace TheISA { 613548Sgblack@eecs.umich.edu namespace Kernel { 623548Sgblack@eecs.umich.edu class Statistics; 633548Sgblack@eecs.umich.edu }; 642330SN/A}; 652330SN/A 662SN/A#else // !FULL_SYSTEM 672SN/A 68360SN/A#include "sim/process.hh" 692462SN/A#include "mem/page_table.hh" 702420SN/Aclass TranslatingPort; 712SN/A 722SN/A#endif // FULL_SYSTEM 732SN/A 742683Sktlim@umich.edu/** 752683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 762683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 772683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 782683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 792683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 802683Sktlim@umich.edu * the objects needed for simple functional execution, including a 812683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 822683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 832683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 842683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 852683Sktlim@umich.edu * all the necessary state for full architecture-level functional 862683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 872683Sktlim@umich.edu * examples. 882683Sktlim@umich.edu */ 892SN/A 902683Sktlim@umich.educlass SimpleThread : public ThreadState 912SN/A{ 922107SN/A protected: 932107SN/A typedef TheISA::RegFile RegFile; 942107SN/A typedef TheISA::MachInst MachInst; 952159SN/A typedef TheISA::MiscReg MiscReg; 962455SN/A typedef TheISA::FloatReg FloatReg; 972455SN/A typedef TheISA::FloatRegBits FloatRegBits; 982SN/A public: 992680SN/A typedef ThreadContext::Status Status; 1002SN/A 1012190SN/A protected: 1025543Ssaidi@eecs.umich.edu RegFile regs; // correct-path register context 1036315Sgblack@eecs.umich.edu union { 1046315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1056315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1066315Sgblack@eecs.umich.edu } floatRegs; 1076316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 1086313Sgblack@eecs.umich.edu TheISA::ISA isa; // one "instance" of the current ISA. 1092SN/A 1106324Sgblack@eecs.umich.edu /** The current microcode pc for the currently executing macro 1116324Sgblack@eecs.umich.edu * operation. 1126324Sgblack@eecs.umich.edu */ 1136324Sgblack@eecs.umich.edu MicroPC microPC; 1146324Sgblack@eecs.umich.edu 1156324Sgblack@eecs.umich.edu /** The next microcode pc for the currently executing macro 1166324Sgblack@eecs.umich.edu * operation. 1176324Sgblack@eecs.umich.edu */ 1186324Sgblack@eecs.umich.edu MicroPC nextMicroPC; 1196324Sgblack@eecs.umich.edu 1206324Sgblack@eecs.umich.edu /** The current pc. 1216324Sgblack@eecs.umich.edu */ 1226324Sgblack@eecs.umich.edu Addr PC; 1236324Sgblack@eecs.umich.edu 1246324Sgblack@eecs.umich.edu /** The next pc. 1256324Sgblack@eecs.umich.edu */ 1266324Sgblack@eecs.umich.edu Addr nextPC; 1276324Sgblack@eecs.umich.edu 1286324Sgblack@eecs.umich.edu /** The next next pc. 1296324Sgblack@eecs.umich.edu */ 1306324Sgblack@eecs.umich.edu Addr nextNPC; 1316324Sgblack@eecs.umich.edu 1322190SN/A public: 1332683Sktlim@umich.edu // pointer to CPU associated with this SimpleThread 1342SN/A BaseCPU *cpu; 1352SN/A 1362683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1372188SN/A 1382378SN/A System *system; 1392400SN/A 1406022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1416022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1422SN/A 1432683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1441858SN/A#if FULL_SYSTEM 1452683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1466022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 1472683Sktlim@umich.edu bool use_kernel_stats = true); 1482SN/A#else 1494997Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 1506022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid); 1512SN/A#endif 1522862Sktlim@umich.edu 1532864Sktlim@umich.edu SimpleThread(); 1542862Sktlim@umich.edu 1552683Sktlim@umich.edu virtual ~SimpleThread(); 1562SN/A 1572680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 158180SN/A 1592SN/A void regStats(const std::string &name); 1602SN/A 1612864Sktlim@umich.edu void copyTC(ThreadContext *context); 1622864Sktlim@umich.edu 1632862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1642862Sktlim@umich.edu 165217SN/A void serialize(std::ostream &os); 166237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 167217SN/A 1682683Sktlim@umich.edu /*************************************************************** 1692683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1705891Sgblack@eecs.umich.edu * state. 1712683Sktlim@umich.edu **************************************************************/ 1722190SN/A 1732683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1742683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1752683Sktlim@umich.edu * CPU. 1762683Sktlim@umich.edu */ 1772680SN/A ThreadContext *getTC() { return tc; } 1782190SN/A 1795358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1805358Sgblack@eecs.umich.edu { 1815358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1825358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1835358Sgblack@eecs.umich.edu } 1845358Sgblack@eecs.umich.edu 1855358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1865358Sgblack@eecs.umich.edu { 1875358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1885358Sgblack@eecs.umich.edu } 1895358Sgblack@eecs.umich.edu 1905358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1915358Sgblack@eecs.umich.edu { 1925358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1935358Sgblack@eecs.umich.edu } 1945358Sgblack@eecs.umich.edu 1954997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1966313Sgblack@eecs.umich.edu int getInstAsid() { return isa.instAsid(); } 1976313Sgblack@eecs.umich.edu int getDataAsid() { return isa.dataAsid(); } 1984997Sgblack@eecs.umich.edu 1992683Sktlim@umich.edu void dumpFuncProfile(); 2002521SN/A 2015702Ssaidi@eecs.umich.edu Fault hwrei(); 2025702Ssaidi@eecs.umich.edu 2035702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 2045702Ssaidi@eecs.umich.edu 2052683Sktlim@umich.edu#endif 2062SN/A 2072683Sktlim@umich.edu /******************************************* 2082683Sktlim@umich.edu * ThreadContext interface functions. 2092683Sktlim@umich.edu ******************************************/ 2102683Sktlim@umich.edu 2112683Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 2122683Sktlim@umich.edu 2136022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 2142683Sktlim@umich.edu 2156022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 2162683Sktlim@umich.edu 2174997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2184997Sgblack@eecs.umich.edu 2195803Snate@binkert.org#if FULL_SYSTEM 2202683Sktlim@umich.edu FunctionalPort *getPhysPort() { return physPort; } 2212683Sktlim@umich.edu 2225499Ssaidi@eecs.umich.edu /** Return a virtual port. This port cannot be cached locally in an object. 2235499Ssaidi@eecs.umich.edu * After a CPU switch it may point to the wrong memory object which could 2245499Ssaidi@eecs.umich.edu * mean stale data. 2255499Ssaidi@eecs.umich.edu */ 2265499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return virtPort; } 2272SN/A#endif 2282SN/A 2292683Sktlim@umich.edu Status status() const { return _status; } 2302683Sktlim@umich.edu 2312683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2322683Sktlim@umich.edu 2332683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2342683Sktlim@umich.edu /// cycles to wait before beginning execution. 2352683Sktlim@umich.edu void activate(int delay = 1); 2362683Sktlim@umich.edu 2372683Sktlim@umich.edu /// Set the status to Suspended. 2382683Sktlim@umich.edu void suspend(); 2392683Sktlim@umich.edu 2402683Sktlim@umich.edu /// Set the status to Halted. 2412683Sktlim@umich.edu void halt(); 2422683Sktlim@umich.edu 2432SN/A virtual bool misspeculating(); 2442SN/A 2452532SN/A Fault instRead(RequestPtr &req) 246716SN/A { 2472378SN/A panic("instRead not implemented"); 2482378SN/A // return funcPhysMem->read(req, inst); 2492423SN/A return NoFault; 250716SN/A } 251716SN/A 2522683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2532190SN/A 2546315Sgblack@eecs.umich.edu void clearArchRegs() 2556315Sgblack@eecs.umich.edu { 2566315Sgblack@eecs.umich.edu regs.clear(); 2576324Sgblack@eecs.umich.edu microPC = 0; 2586324Sgblack@eecs.umich.edu nextMicroPC = 1; 2596324Sgblack@eecs.umich.edu PC = nextPC = nextNPC = 0; 2606316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 2616315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2626315Sgblack@eecs.umich.edu } 2632190SN/A 2642SN/A // 2652SN/A // New accessors for new decoder. 2662SN/A // 2672SN/A uint64_t readIntReg(int reg_idx) 2682SN/A { 2696313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2706323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2716316Sgblack@eecs.umich.edu return intRegs[flatIndex]; 2722SN/A } 2732SN/A 2742455SN/A FloatReg readFloatReg(int reg_idx) 2752SN/A { 2766313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2776323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2786315Sgblack@eecs.umich.edu return floatRegs.f[flatIndex]; 2792SN/A } 2802SN/A 2812455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2822455SN/A { 2836313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2846323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2856315Sgblack@eecs.umich.edu return floatRegs.i[flatIndex]; 2862SN/A } 2872SN/A 2882SN/A void setIntReg(int reg_idx, uint64_t val) 2892SN/A { 2906313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2916323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2926316Sgblack@eecs.umich.edu intRegs[flatIndex] = val; 2932SN/A } 2942SN/A 2952455SN/A void setFloatReg(int reg_idx, FloatReg val) 2962SN/A { 2976313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2986323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2996315Sgblack@eecs.umich.edu floatRegs.f[flatIndex] = val; 3002SN/A } 3012SN/A 3022455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3032455SN/A { 3046313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 3056323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 3066315Sgblack@eecs.umich.edu floatRegs.i[flatIndex] = val; 3072SN/A } 3082SN/A 3092SN/A uint64_t readPC() 3102SN/A { 3116324Sgblack@eecs.umich.edu return PC; 3122SN/A } 3132SN/A 3142190SN/A void setPC(uint64_t val) 3152190SN/A { 3166324Sgblack@eecs.umich.edu PC = val; 3172190SN/A } 3182190SN/A 3193276Sgblack@eecs.umich.edu uint64_t readMicroPC() 3203276Sgblack@eecs.umich.edu { 3213276Sgblack@eecs.umich.edu return microPC; 3223276Sgblack@eecs.umich.edu } 3233276Sgblack@eecs.umich.edu 3243276Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) 3253276Sgblack@eecs.umich.edu { 3263276Sgblack@eecs.umich.edu microPC = val; 3273276Sgblack@eecs.umich.edu } 3283276Sgblack@eecs.umich.edu 3292190SN/A uint64_t readNextPC() 3302190SN/A { 3316324Sgblack@eecs.umich.edu return nextPC; 3322190SN/A } 3332190SN/A 3342SN/A void setNextPC(uint64_t val) 3352SN/A { 3366324Sgblack@eecs.umich.edu nextPC = val; 3372SN/A } 3382SN/A 3393276Sgblack@eecs.umich.edu uint64_t readNextMicroPC() 3403276Sgblack@eecs.umich.edu { 3413276Sgblack@eecs.umich.edu return nextMicroPC; 3423276Sgblack@eecs.umich.edu } 3433276Sgblack@eecs.umich.edu 3443276Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) 3453276Sgblack@eecs.umich.edu { 3463276Sgblack@eecs.umich.edu nextMicroPC = val; 3473276Sgblack@eecs.umich.edu } 3483276Sgblack@eecs.umich.edu 3492252SN/A uint64_t readNextNPC() 3502252SN/A { 3516324Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 3526324Sgblack@eecs.umich.edu return nextNPC; 3536324Sgblack@eecs.umich.edu#else 3546324Sgblack@eecs.umich.edu return nextPC + sizeof(TheISA::MachInst); 3556324Sgblack@eecs.umich.edu#endif 3562252SN/A } 3572252SN/A 3582251SN/A void setNextNPC(uint64_t val) 3592251SN/A { 3606324Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 3616324Sgblack@eecs.umich.edu nextNPC = val; 3626324Sgblack@eecs.umich.edu#endif 3632251SN/A } 3642251SN/A 3656221Snate@binkert.org MiscReg 3666221Snate@binkert.org readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 3674172Ssaidi@eecs.umich.edu { 3686313Sgblack@eecs.umich.edu return isa.readMiscRegNoEffect(misc_reg); 3694172Ssaidi@eecs.umich.edu } 3704172Ssaidi@eecs.umich.edu 3716221Snate@binkert.org MiscReg 3726221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 3732SN/A { 3746313Sgblack@eecs.umich.edu return isa.readMiscReg(misc_reg, tc); 3752SN/A } 3762SN/A 3776221Snate@binkert.org void 3786221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3792SN/A { 3806313Sgblack@eecs.umich.edu return isa.setMiscRegNoEffect(misc_reg, val); 3812SN/A } 3822SN/A 3836221Snate@binkert.org void 3846221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3852SN/A { 3866313Sgblack@eecs.umich.edu return isa.setMiscReg(misc_reg, val, tc); 3876313Sgblack@eecs.umich.edu } 3886313Sgblack@eecs.umich.edu 3896313Sgblack@eecs.umich.edu int 3906313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 3916313Sgblack@eecs.umich.edu { 3926313Sgblack@eecs.umich.edu return isa.flattenIntIndex(reg); 3936313Sgblack@eecs.umich.edu } 3946313Sgblack@eecs.umich.edu 3956313Sgblack@eecs.umich.edu int 3966313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 3976313Sgblack@eecs.umich.edu { 3986313Sgblack@eecs.umich.edu return isa.flattenFloatIndex(reg); 3992SN/A } 4002SN/A 4012190SN/A unsigned readStCondFailures() { return storeCondFailures; } 4022190SN/A 4032190SN/A void setStCondFailures(unsigned sc_failures) 4042190SN/A { storeCondFailures = sc_failures; } 4052190SN/A 4061858SN/A#if !FULL_SYSTEM 4072561SN/A void syscall(int64_t callnum) 4082SN/A { 4092680SN/A process->syscall(callnum, tc); 4102SN/A } 4112SN/A#endif 4122SN/A}; 4132SN/A 4142SN/A 4152SN/A// for non-speculative execution context, spec_mode is always false 4162SN/Ainline bool 4172683Sktlim@umich.eduSimpleThread::misspeculating() 4182SN/A{ 4192SN/A return false; 4202SN/A} 4212SN/A 4222190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 423