simple_thread.hh revision 6022
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302SN/A */ 312SN/A 322683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 332683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 342SN/A 352190SN/A#include "arch/isa_traits.hh" 363776Sgblack@eecs.umich.edu#include "arch/regfile.hh" 374997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 381858SN/A#include "config/full_system.hh" 392680SN/A#include "cpu/thread_context.hh" 402683Sktlim@umich.edu#include "cpu/thread_state.hh" 412395SN/A#include "mem/request.hh" 422190SN/A#include "sim/byteswap.hh" 432188SN/A#include "sim/eventq.hh" 4456SN/A#include "sim/host.hh" 45217SN/A#include "sim/serialize.hh" 462SN/A 472SN/Aclass BaseCPU; 482SN/A 491858SN/A#if FULL_SYSTEM 502SN/A 511070SN/A#include "sim/system.hh" 521070SN/A 531917SN/Aclass FunctionProfile; 541917SN/Aclass ProfileNode; 552521SN/Aclass FunctionalPort; 562521SN/Aclass PhysicalPort; 572521SN/A 583548Sgblack@eecs.umich.edunamespace TheISA { 593548Sgblack@eecs.umich.edu namespace Kernel { 603548Sgblack@eecs.umich.edu class Statistics; 613548Sgblack@eecs.umich.edu }; 622330SN/A}; 632330SN/A 642SN/A#else // !FULL_SYSTEM 652SN/A 66360SN/A#include "sim/process.hh" 672462SN/A#include "mem/page_table.hh" 682420SN/Aclass TranslatingPort; 692SN/A 702SN/A#endif // FULL_SYSTEM 712SN/A 722683Sktlim@umich.edu/** 732683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 742683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 752683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 762683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 772683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 782683Sktlim@umich.edu * the objects needed for simple functional execution, including a 792683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 802683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 812683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 822683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 832683Sktlim@umich.edu * all the necessary state for full architecture-level functional 842683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 852683Sktlim@umich.edu * examples. 862683Sktlim@umich.edu */ 872SN/A 882683Sktlim@umich.educlass SimpleThread : public ThreadState 892SN/A{ 902107SN/A protected: 912107SN/A typedef TheISA::RegFile RegFile; 922107SN/A typedef TheISA::MachInst MachInst; 932107SN/A typedef TheISA::MiscRegFile MiscRegFile; 942159SN/A typedef TheISA::MiscReg MiscReg; 952455SN/A typedef TheISA::FloatReg FloatReg; 962455SN/A typedef TheISA::FloatRegBits FloatRegBits; 972SN/A public: 982680SN/A typedef ThreadContext::Status Status; 992SN/A 1002190SN/A protected: 1015543Ssaidi@eecs.umich.edu RegFile regs; // correct-path register context 1022SN/A 1032190SN/A public: 1042683Sktlim@umich.edu // pointer to CPU associated with this SimpleThread 1052SN/A BaseCPU *cpu; 1062SN/A 1072683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1082188SN/A 1092378SN/A System *system; 1102400SN/A 1116022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1126022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1132SN/A 1142683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1151858SN/A#if FULL_SYSTEM 1162683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1176022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 1182683Sktlim@umich.edu bool use_kernel_stats = true); 1192SN/A#else 1204997Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 1216022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid); 1222SN/A#endif 1232862Sktlim@umich.edu 1242864Sktlim@umich.edu SimpleThread(); 1252862Sktlim@umich.edu 1262683Sktlim@umich.edu virtual ~SimpleThread(); 1272SN/A 1282680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 129180SN/A 1302SN/A void regStats(const std::string &name); 1312SN/A 1322864Sktlim@umich.edu void copyTC(ThreadContext *context); 1332864Sktlim@umich.edu 1342862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1352862Sktlim@umich.edu 136217SN/A void serialize(std::ostream &os); 137237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 138217SN/A 1392683Sktlim@umich.edu /*************************************************************** 1402683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1415891Sgblack@eecs.umich.edu * state. 1422683Sktlim@umich.edu **************************************************************/ 1432190SN/A 1442683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1452683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1462683Sktlim@umich.edu * CPU. 1472683Sktlim@umich.edu */ 1482680SN/A ThreadContext *getTC() { return tc; } 1492190SN/A 1505358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1515358Sgblack@eecs.umich.edu { 1525358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1535358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1545358Sgblack@eecs.umich.edu } 1555358Sgblack@eecs.umich.edu 1565358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1575358Sgblack@eecs.umich.edu { 1585358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1595358Sgblack@eecs.umich.edu } 1605358Sgblack@eecs.umich.edu 1615358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1625358Sgblack@eecs.umich.edu { 1635358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1645358Sgblack@eecs.umich.edu } 1655358Sgblack@eecs.umich.edu 1664997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1674997Sgblack@eecs.umich.edu int getInstAsid() { return regs.instAsid(); } 1684997Sgblack@eecs.umich.edu int getDataAsid() { return regs.dataAsid(); } 1694997Sgblack@eecs.umich.edu 1702683Sktlim@umich.edu void dumpFuncProfile(); 1712521SN/A 1725702Ssaidi@eecs.umich.edu Fault hwrei(); 1735702Ssaidi@eecs.umich.edu 1745702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1755702Ssaidi@eecs.umich.edu 1762683Sktlim@umich.edu#endif 1772SN/A 1782683Sktlim@umich.edu /******************************************* 1792683Sktlim@umich.edu * ThreadContext interface functions. 1802683Sktlim@umich.edu ******************************************/ 1812683Sktlim@umich.edu 1822683Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 1832683Sktlim@umich.edu 1846022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 1852683Sktlim@umich.edu 1866022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 1872683Sktlim@umich.edu 1884997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 1894997Sgblack@eecs.umich.edu 1905803Snate@binkert.org#if FULL_SYSTEM 1912683Sktlim@umich.edu FunctionalPort *getPhysPort() { return physPort; } 1922683Sktlim@umich.edu 1935499Ssaidi@eecs.umich.edu /** Return a virtual port. This port cannot be cached locally in an object. 1945499Ssaidi@eecs.umich.edu * After a CPU switch it may point to the wrong memory object which could 1955499Ssaidi@eecs.umich.edu * mean stale data. 1965499Ssaidi@eecs.umich.edu */ 1975499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return virtPort; } 1982SN/A#endif 1992SN/A 2002683Sktlim@umich.edu Status status() const { return _status; } 2012683Sktlim@umich.edu 2022683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2032683Sktlim@umich.edu 2042683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2052683Sktlim@umich.edu /// cycles to wait before beginning execution. 2062683Sktlim@umich.edu void activate(int delay = 1); 2072683Sktlim@umich.edu 2082683Sktlim@umich.edu /// Set the status to Suspended. 2092683Sktlim@umich.edu void suspend(); 2102683Sktlim@umich.edu 2112683Sktlim@umich.edu /// Set the status to Unallocated. 2122683Sktlim@umich.edu void deallocate(); 2132683Sktlim@umich.edu 2142683Sktlim@umich.edu /// Set the status to Halted. 2152683Sktlim@umich.edu void halt(); 2162683Sktlim@umich.edu 2172SN/A virtual bool misspeculating(); 2182SN/A 2192532SN/A Fault instRead(RequestPtr &req) 220716SN/A { 2212378SN/A panic("instRead not implemented"); 2222378SN/A // return funcPhysMem->read(req, inst); 2232423SN/A return NoFault; 224716SN/A } 225716SN/A 2262683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2272190SN/A 2282683Sktlim@umich.edu void clearArchRegs() { regs.clear(); } 2292190SN/A 2302SN/A // 2312SN/A // New accessors for new decoder. 2322SN/A // 2332SN/A uint64_t readIntReg(int reg_idx) 2342SN/A { 2355082Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); 2365082Sgblack@eecs.umich.edu return regs.readIntReg(flatIndex); 2372SN/A } 2382SN/A 2392455SN/A FloatReg readFloatReg(int reg_idx, int width) 2402SN/A { 2415088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2425082Sgblack@eecs.umich.edu return regs.readFloatReg(flatIndex, width); 2432SN/A } 2442SN/A 2452455SN/A FloatReg readFloatReg(int reg_idx) 2462SN/A { 2475088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2485082Sgblack@eecs.umich.edu return regs.readFloatReg(flatIndex); 2492SN/A } 2502SN/A 2512455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width) 2522SN/A { 2535088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2545082Sgblack@eecs.umich.edu return regs.readFloatRegBits(flatIndex, width); 2552455SN/A } 2562455SN/A 2572455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2582455SN/A { 2595088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2605082Sgblack@eecs.umich.edu return regs.readFloatRegBits(flatIndex); 2612SN/A } 2622SN/A 2632SN/A void setIntReg(int reg_idx, uint64_t val) 2642SN/A { 2655082Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); 2665082Sgblack@eecs.umich.edu regs.setIntReg(flatIndex, val); 2672SN/A } 2682SN/A 2692455SN/A void setFloatReg(int reg_idx, FloatReg val, int width) 2702SN/A { 2715088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2725082Sgblack@eecs.umich.edu regs.setFloatReg(flatIndex, val, width); 2732SN/A } 2742SN/A 2752455SN/A void setFloatReg(int reg_idx, FloatReg val) 2762SN/A { 2775088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2785082Sgblack@eecs.umich.edu regs.setFloatReg(flatIndex, val); 2792SN/A } 2802SN/A 2812455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 2822SN/A { 2835088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2845082Sgblack@eecs.umich.edu regs.setFloatRegBits(flatIndex, val, width); 2852455SN/A } 2862455SN/A 2872455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2882455SN/A { 2895088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2905082Sgblack@eecs.umich.edu regs.setFloatRegBits(flatIndex, val); 2912SN/A } 2922SN/A 2932SN/A uint64_t readPC() 2942SN/A { 2952525SN/A return regs.readPC(); 2962SN/A } 2972SN/A 2982190SN/A void setPC(uint64_t val) 2992190SN/A { 3002525SN/A regs.setPC(val); 3012190SN/A } 3022190SN/A 3033276Sgblack@eecs.umich.edu uint64_t readMicroPC() 3043276Sgblack@eecs.umich.edu { 3053276Sgblack@eecs.umich.edu return microPC; 3063276Sgblack@eecs.umich.edu } 3073276Sgblack@eecs.umich.edu 3083276Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) 3093276Sgblack@eecs.umich.edu { 3103276Sgblack@eecs.umich.edu microPC = val; 3113276Sgblack@eecs.umich.edu } 3123276Sgblack@eecs.umich.edu 3132190SN/A uint64_t readNextPC() 3142190SN/A { 3152525SN/A return regs.readNextPC(); 3162190SN/A } 3172190SN/A 3182SN/A void setNextPC(uint64_t val) 3192SN/A { 3202525SN/A regs.setNextPC(val); 3212SN/A } 3222SN/A 3233276Sgblack@eecs.umich.edu uint64_t readNextMicroPC() 3243276Sgblack@eecs.umich.edu { 3253276Sgblack@eecs.umich.edu return nextMicroPC; 3263276Sgblack@eecs.umich.edu } 3273276Sgblack@eecs.umich.edu 3283276Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) 3293276Sgblack@eecs.umich.edu { 3303276Sgblack@eecs.umich.edu nextMicroPC = val; 3313276Sgblack@eecs.umich.edu } 3323276Sgblack@eecs.umich.edu 3332252SN/A uint64_t readNextNPC() 3342252SN/A { 3352525SN/A return regs.readNextNPC(); 3362252SN/A } 3372252SN/A 3382251SN/A void setNextNPC(uint64_t val) 3392251SN/A { 3402525SN/A regs.setNextNPC(val); 3412251SN/A } 3422251SN/A 3434661Sksewell@umich.edu MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0) 3444172Ssaidi@eecs.umich.edu { 3454172Ssaidi@eecs.umich.edu return regs.readMiscRegNoEffect(misc_reg); 3464172Ssaidi@eecs.umich.edu } 3474172Ssaidi@eecs.umich.edu 3484661Sksewell@umich.edu MiscReg readMiscReg(int misc_reg, unsigned tid = 0) 3492SN/A { 3504172Ssaidi@eecs.umich.edu return regs.readMiscReg(misc_reg, tc); 3512SN/A } 3522SN/A 3534661Sksewell@umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0) 3542SN/A { 3554172Ssaidi@eecs.umich.edu return regs.setMiscRegNoEffect(misc_reg, val); 3562SN/A } 3572SN/A 3584661Sksewell@umich.edu void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0) 3592SN/A { 3604172Ssaidi@eecs.umich.edu return regs.setMiscReg(misc_reg, val, tc); 3612SN/A } 3622SN/A 3632190SN/A unsigned readStCondFailures() { return storeCondFailures; } 3642190SN/A 3652190SN/A void setStCondFailures(unsigned sc_failures) 3662190SN/A { storeCondFailures = sc_failures; } 3672190SN/A 3681858SN/A#if !FULL_SYSTEM 3692561SN/A void syscall(int64_t callnum) 3702SN/A { 3712680SN/A process->syscall(callnum, tc); 3722SN/A } 3732SN/A#endif 3742SN/A}; 3752SN/A 3762SN/A 3772SN/A// for non-speculative execution context, spec_mode is always false 3782SN/Ainline bool 3792683Sktlim@umich.eduSimpleThread::misspeculating() 3802SN/A{ 3812SN/A return false; 3822SN/A} 3832SN/A 3842190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 385