simple_thread.hh revision 5891
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302SN/A */ 312SN/A 322683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 332683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 342SN/A 352190SN/A#include "arch/isa_traits.hh" 363776Sgblack@eecs.umich.edu#include "arch/regfile.hh" 373776Sgblack@eecs.umich.edu#include "arch/syscallreturn.hh" 384997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 391858SN/A#include "config/full_system.hh" 402680SN/A#include "cpu/thread_context.hh" 412683Sktlim@umich.edu#include "cpu/thread_state.hh" 422395SN/A#include "mem/request.hh" 432190SN/A#include "sim/byteswap.hh" 442188SN/A#include "sim/eventq.hh" 4556SN/A#include "sim/host.hh" 46217SN/A#include "sim/serialize.hh" 472SN/A 482SN/Aclass BaseCPU; 492SN/A 501858SN/A#if FULL_SYSTEM 512SN/A 521070SN/A#include "sim/system.hh" 531070SN/A 541917SN/Aclass FunctionProfile; 551917SN/Aclass ProfileNode; 562521SN/Aclass FunctionalPort; 572521SN/Aclass PhysicalPort; 582521SN/A 593548Sgblack@eecs.umich.edunamespace TheISA { 603548Sgblack@eecs.umich.edu namespace Kernel { 613548Sgblack@eecs.umich.edu class Statistics; 623548Sgblack@eecs.umich.edu }; 632330SN/A}; 642330SN/A 652SN/A#else // !FULL_SYSTEM 662SN/A 67360SN/A#include "sim/process.hh" 682462SN/A#include "mem/page_table.hh" 692420SN/Aclass TranslatingPort; 702SN/A 712SN/A#endif // FULL_SYSTEM 722SN/A 732683Sktlim@umich.edu/** 742683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 752683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 762683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 772683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 782683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 792683Sktlim@umich.edu * the objects needed for simple functional execution, including a 802683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 812683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 822683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 832683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 842683Sktlim@umich.edu * all the necessary state for full architecture-level functional 852683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 862683Sktlim@umich.edu * examples. 872683Sktlim@umich.edu */ 882SN/A 892683Sktlim@umich.educlass SimpleThread : public ThreadState 902SN/A{ 912107SN/A protected: 922107SN/A typedef TheISA::RegFile RegFile; 932107SN/A typedef TheISA::MachInst MachInst; 942107SN/A typedef TheISA::MiscRegFile MiscRegFile; 952159SN/A typedef TheISA::MiscReg MiscReg; 962455SN/A typedef TheISA::FloatReg FloatReg; 972455SN/A typedef TheISA::FloatRegBits FloatRegBits; 982SN/A public: 992680SN/A typedef ThreadContext::Status Status; 1002SN/A 1012190SN/A protected: 1025543Ssaidi@eecs.umich.edu RegFile regs; // correct-path register context 1032SN/A 1042190SN/A public: 1052683Sktlim@umich.edu // pointer to CPU associated with this SimpleThread 1062SN/A BaseCPU *cpu; 1072SN/A 1082683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1092188SN/A 1102378SN/A System *system; 1112400SN/A 1123453Sgblack@eecs.umich.edu TheISA::ITB *itb; 1133453Sgblack@eecs.umich.edu TheISA::DTB *dtb; 1142SN/A 1152683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1161858SN/A#if FULL_SYSTEM 1172683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1183453Sgblack@eecs.umich.edu TheISA::ITB *_itb, TheISA::DTB *_dtb, 1192683Sktlim@umich.edu bool use_kernel_stats = true); 1202SN/A#else 1214997Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 1224997Sgblack@eecs.umich.edu TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid); 1232SN/A#endif 1242862Sktlim@umich.edu 1252864Sktlim@umich.edu SimpleThread(); 1262862Sktlim@umich.edu 1272683Sktlim@umich.edu virtual ~SimpleThread(); 1282SN/A 1292680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 130180SN/A 1312SN/A void regStats(const std::string &name); 1322SN/A 1332864Sktlim@umich.edu void copyTC(ThreadContext *context); 1342864Sktlim@umich.edu 1352862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1362862Sktlim@umich.edu 137217SN/A void serialize(std::ostream &os); 138237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 139217SN/A 1402683Sktlim@umich.edu /*************************************************************** 1412683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1425891Sgblack@eecs.umich.edu * state. 1432683Sktlim@umich.edu **************************************************************/ 1442190SN/A 1452683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1462683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1472683Sktlim@umich.edu * CPU. 1482683Sktlim@umich.edu */ 1492680SN/A ThreadContext *getTC() { return tc; } 1502190SN/A 1515358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1525358Sgblack@eecs.umich.edu { 1535358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1545358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1555358Sgblack@eecs.umich.edu } 1565358Sgblack@eecs.umich.edu 1575358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1585358Sgblack@eecs.umich.edu { 1595358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1605358Sgblack@eecs.umich.edu } 1615358Sgblack@eecs.umich.edu 1625358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1635358Sgblack@eecs.umich.edu { 1645358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1655358Sgblack@eecs.umich.edu } 1665358Sgblack@eecs.umich.edu 1674997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1684997Sgblack@eecs.umich.edu int getInstAsid() { return regs.instAsid(); } 1694997Sgblack@eecs.umich.edu int getDataAsid() { return regs.dataAsid(); } 1704997Sgblack@eecs.umich.edu 1712683Sktlim@umich.edu void dumpFuncProfile(); 1722521SN/A 1735702Ssaidi@eecs.umich.edu Fault hwrei(); 1745702Ssaidi@eecs.umich.edu 1755702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1765702Ssaidi@eecs.umich.edu 1772683Sktlim@umich.edu#endif 1782SN/A 1792683Sktlim@umich.edu /******************************************* 1802683Sktlim@umich.edu * ThreadContext interface functions. 1812683Sktlim@umich.edu ******************************************/ 1822683Sktlim@umich.edu 1832683Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 1842683Sktlim@umich.edu 1853453Sgblack@eecs.umich.edu TheISA::ITB *getITBPtr() { return itb; } 1862683Sktlim@umich.edu 1873453Sgblack@eecs.umich.edu TheISA::DTB *getDTBPtr() { return dtb; } 1882683Sktlim@umich.edu 1894997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 1904997Sgblack@eecs.umich.edu 1915803Snate@binkert.org#if FULL_SYSTEM 1922683Sktlim@umich.edu FunctionalPort *getPhysPort() { return physPort; } 1932683Sktlim@umich.edu 1945499Ssaidi@eecs.umich.edu /** Return a virtual port. This port cannot be cached locally in an object. 1955499Ssaidi@eecs.umich.edu * After a CPU switch it may point to the wrong memory object which could 1965499Ssaidi@eecs.umich.edu * mean stale data. 1975499Ssaidi@eecs.umich.edu */ 1985499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return virtPort; } 1992SN/A#endif 2002SN/A 2012683Sktlim@umich.edu Status status() const { return _status; } 2022683Sktlim@umich.edu 2032683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2042683Sktlim@umich.edu 2052683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2062683Sktlim@umich.edu /// cycles to wait before beginning execution. 2072683Sktlim@umich.edu void activate(int delay = 1); 2082683Sktlim@umich.edu 2092683Sktlim@umich.edu /// Set the status to Suspended. 2102683Sktlim@umich.edu void suspend(); 2112683Sktlim@umich.edu 2122683Sktlim@umich.edu /// Set the status to Unallocated. 2132683Sktlim@umich.edu void deallocate(); 2142683Sktlim@umich.edu 2152683Sktlim@umich.edu /// Set the status to Halted. 2162683Sktlim@umich.edu void halt(); 2172683Sktlim@umich.edu 2182SN/A virtual bool misspeculating(); 2192SN/A 2202532SN/A Fault instRead(RequestPtr &req) 221716SN/A { 2222378SN/A panic("instRead not implemented"); 2232378SN/A // return funcPhysMem->read(req, inst); 2242423SN/A return NoFault; 225716SN/A } 226716SN/A 2272683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2282190SN/A 2292683Sktlim@umich.edu void clearArchRegs() { regs.clear(); } 2302190SN/A 2312SN/A // 2322SN/A // New accessors for new decoder. 2332SN/A // 2342SN/A uint64_t readIntReg(int reg_idx) 2352SN/A { 2365082Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); 2375082Sgblack@eecs.umich.edu return regs.readIntReg(flatIndex); 2382SN/A } 2392SN/A 2402455SN/A FloatReg readFloatReg(int reg_idx, int width) 2412SN/A { 2425088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2435082Sgblack@eecs.umich.edu return regs.readFloatReg(flatIndex, width); 2442SN/A } 2452SN/A 2462455SN/A FloatReg readFloatReg(int reg_idx) 2472SN/A { 2485088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2495082Sgblack@eecs.umich.edu return regs.readFloatReg(flatIndex); 2502SN/A } 2512SN/A 2522455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width) 2532SN/A { 2545088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2555082Sgblack@eecs.umich.edu return regs.readFloatRegBits(flatIndex, width); 2562455SN/A } 2572455SN/A 2582455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2592455SN/A { 2605088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2615082Sgblack@eecs.umich.edu return regs.readFloatRegBits(flatIndex); 2622SN/A } 2632SN/A 2642SN/A void setIntReg(int reg_idx, uint64_t val) 2652SN/A { 2665082Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); 2675082Sgblack@eecs.umich.edu regs.setIntReg(flatIndex, val); 2682SN/A } 2692SN/A 2702455SN/A void setFloatReg(int reg_idx, FloatReg val, int width) 2712SN/A { 2725088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2735082Sgblack@eecs.umich.edu regs.setFloatReg(flatIndex, val, width); 2742SN/A } 2752SN/A 2762455SN/A void setFloatReg(int reg_idx, FloatReg val) 2772SN/A { 2785088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2795082Sgblack@eecs.umich.edu regs.setFloatReg(flatIndex, val); 2802SN/A } 2812SN/A 2822455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 2832SN/A { 2845088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2855082Sgblack@eecs.umich.edu regs.setFloatRegBits(flatIndex, val, width); 2862455SN/A } 2872455SN/A 2882455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2892455SN/A { 2905088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2915082Sgblack@eecs.umich.edu regs.setFloatRegBits(flatIndex, val); 2922SN/A } 2932SN/A 2942SN/A uint64_t readPC() 2952SN/A { 2962525SN/A return regs.readPC(); 2972SN/A } 2982SN/A 2992190SN/A void setPC(uint64_t val) 3002190SN/A { 3012525SN/A regs.setPC(val); 3022190SN/A } 3032190SN/A 3043276Sgblack@eecs.umich.edu uint64_t readMicroPC() 3053276Sgblack@eecs.umich.edu { 3063276Sgblack@eecs.umich.edu return microPC; 3073276Sgblack@eecs.umich.edu } 3083276Sgblack@eecs.umich.edu 3093276Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) 3103276Sgblack@eecs.umich.edu { 3113276Sgblack@eecs.umich.edu microPC = val; 3123276Sgblack@eecs.umich.edu } 3133276Sgblack@eecs.umich.edu 3142190SN/A uint64_t readNextPC() 3152190SN/A { 3162525SN/A return regs.readNextPC(); 3172190SN/A } 3182190SN/A 3192SN/A void setNextPC(uint64_t val) 3202SN/A { 3212525SN/A regs.setNextPC(val); 3222SN/A } 3232SN/A 3243276Sgblack@eecs.umich.edu uint64_t readNextMicroPC() 3253276Sgblack@eecs.umich.edu { 3263276Sgblack@eecs.umich.edu return nextMicroPC; 3273276Sgblack@eecs.umich.edu } 3283276Sgblack@eecs.umich.edu 3293276Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) 3303276Sgblack@eecs.umich.edu { 3313276Sgblack@eecs.umich.edu nextMicroPC = val; 3323276Sgblack@eecs.umich.edu } 3333276Sgblack@eecs.umich.edu 3342252SN/A uint64_t readNextNPC() 3352252SN/A { 3362525SN/A return regs.readNextNPC(); 3372252SN/A } 3382252SN/A 3392251SN/A void setNextNPC(uint64_t val) 3402251SN/A { 3412525SN/A regs.setNextNPC(val); 3422251SN/A } 3432251SN/A 3444661Sksewell@umich.edu MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0) 3454172Ssaidi@eecs.umich.edu { 3464172Ssaidi@eecs.umich.edu return regs.readMiscRegNoEffect(misc_reg); 3474172Ssaidi@eecs.umich.edu } 3484172Ssaidi@eecs.umich.edu 3494661Sksewell@umich.edu MiscReg readMiscReg(int misc_reg, unsigned tid = 0) 3502SN/A { 3514172Ssaidi@eecs.umich.edu return regs.readMiscReg(misc_reg, tc); 3522SN/A } 3532SN/A 3544661Sksewell@umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0) 3552SN/A { 3564172Ssaidi@eecs.umich.edu return regs.setMiscRegNoEffect(misc_reg, val); 3572SN/A } 3582SN/A 3594661Sksewell@umich.edu void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0) 3602SN/A { 3614172Ssaidi@eecs.umich.edu return regs.setMiscReg(misc_reg, val, tc); 3622SN/A } 3632SN/A 3642190SN/A unsigned readStCondFailures() { return storeCondFailures; } 3652190SN/A 3662190SN/A void setStCondFailures(unsigned sc_failures) 3672190SN/A { storeCondFailures = sc_failures; } 3682190SN/A 3691858SN/A#if !FULL_SYSTEM 3702107SN/A TheISA::IntReg getSyscallArg(int i) 371360SN/A { 3724772Sgblack@eecs.umich.edu assert(i < TheISA::NumArgumentRegs); 3735779Sgblack@eecs.umich.edu TheISA::IntReg val = regs.readIntReg( 3745779Sgblack@eecs.umich.edu TheISA::flattenIntIndex(getTC(), TheISA::ArgumentReg[i])); 3755779Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 3765779Sgblack@eecs.umich.edu if (bits(this->readMiscRegNoEffect( 3775779Sgblack@eecs.umich.edu SparcISA::MISCREG_PSTATE), 3, 3)) { 3785779Sgblack@eecs.umich.edu val = bits(val, 31, 0); 3795779Sgblack@eecs.umich.edu } 3805779Sgblack@eecs.umich.edu#endif 3815779Sgblack@eecs.umich.edu return val; 382360SN/A } 383360SN/A 384360SN/A // used to shift args for indirect syscall 3852107SN/A void setSyscallArg(int i, TheISA::IntReg val) 386360SN/A { 3874772Sgblack@eecs.umich.edu assert(i < TheISA::NumArgumentRegs); 3883776Sgblack@eecs.umich.edu regs.setIntReg(TheISA::flattenIntIndex(getTC(), 3894772Sgblack@eecs.umich.edu TheISA::ArgumentReg[i]), val); 390360SN/A } 391360SN/A 3921450SN/A void setSyscallReturn(SyscallReturn return_value) 393360SN/A { 3943776Sgblack@eecs.umich.edu TheISA::setSyscallReturn(return_value, getTC()); 395360SN/A } 396360SN/A 3972561SN/A void syscall(int64_t callnum) 3982SN/A { 3992680SN/A process->syscall(callnum, tc); 4002SN/A } 4012SN/A#endif 4022SN/A}; 4032SN/A 4042SN/A 4052SN/A// for non-speculative execution context, spec_mode is always false 4062SN/Ainline bool 4072683Sktlim@umich.eduSimpleThread::misspeculating() 4082SN/A{ 4092SN/A return false; 4102SN/A} 4112SN/A 4122190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 413