simple_thread.hh revision 5779
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302SN/A */ 312SN/A 322683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 332683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 342SN/A 352190SN/A#include "arch/isa_traits.hh" 363776Sgblack@eecs.umich.edu#include "arch/regfile.hh" 373776Sgblack@eecs.umich.edu#include "arch/syscallreturn.hh" 384997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 391858SN/A#include "config/full_system.hh" 402680SN/A#include "cpu/thread_context.hh" 412683Sktlim@umich.edu#include "cpu/thread_state.hh" 422395SN/A#include "mem/request.hh" 432190SN/A#include "sim/byteswap.hh" 442188SN/A#include "sim/eventq.hh" 4556SN/A#include "sim/host.hh" 46217SN/A#include "sim/serialize.hh" 472SN/A 482SN/Aclass BaseCPU; 492SN/A 501858SN/A#if FULL_SYSTEM 512SN/A 521070SN/A#include "sim/system.hh" 531070SN/A 541917SN/Aclass FunctionProfile; 551917SN/Aclass ProfileNode; 562521SN/Aclass FunctionalPort; 572521SN/Aclass PhysicalPort; 582521SN/A 593548Sgblack@eecs.umich.edunamespace TheISA { 603548Sgblack@eecs.umich.edu namespace Kernel { 613548Sgblack@eecs.umich.edu class Statistics; 623548Sgblack@eecs.umich.edu }; 632330SN/A}; 642330SN/A 652SN/A#else // !FULL_SYSTEM 662SN/A 67360SN/A#include "sim/process.hh" 682462SN/A#include "mem/page_table.hh" 692420SN/Aclass TranslatingPort; 702SN/A 712SN/A#endif // FULL_SYSTEM 722SN/A 732683Sktlim@umich.edu/** 742683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 752683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 762683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 772683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 782683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 792683Sktlim@umich.edu * the objects needed for simple functional execution, including a 802683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 812683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 822683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 832683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 842683Sktlim@umich.edu * all the necessary state for full architecture-level functional 852683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 862683Sktlim@umich.edu * examples. 872683Sktlim@umich.edu */ 882SN/A 892683Sktlim@umich.educlass SimpleThread : public ThreadState 902SN/A{ 912107SN/A protected: 922107SN/A typedef TheISA::RegFile RegFile; 932107SN/A typedef TheISA::MachInst MachInst; 942107SN/A typedef TheISA::MiscRegFile MiscRegFile; 952159SN/A typedef TheISA::MiscReg MiscReg; 962455SN/A typedef TheISA::FloatReg FloatReg; 972455SN/A typedef TheISA::FloatRegBits FloatRegBits; 982SN/A public: 992680SN/A typedef ThreadContext::Status Status; 1002SN/A 1012190SN/A protected: 1025543Ssaidi@eecs.umich.edu RegFile regs; // correct-path register context 1032SN/A 1042190SN/A public: 1052683Sktlim@umich.edu // pointer to CPU associated with this SimpleThread 1062SN/A BaseCPU *cpu; 1072SN/A 1082683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1092188SN/A 1102378SN/A System *system; 1112400SN/A 1123453Sgblack@eecs.umich.edu TheISA::ITB *itb; 1133453Sgblack@eecs.umich.edu TheISA::DTB *dtb; 1142SN/A 1152683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1161858SN/A#if FULL_SYSTEM 1172683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1183453Sgblack@eecs.umich.edu TheISA::ITB *_itb, TheISA::DTB *_dtb, 1192683Sktlim@umich.edu bool use_kernel_stats = true); 1202SN/A#else 1214997Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 1224997Sgblack@eecs.umich.edu TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid); 1232SN/A#endif 1242862Sktlim@umich.edu 1252864Sktlim@umich.edu SimpleThread(); 1262862Sktlim@umich.edu 1272683Sktlim@umich.edu virtual ~SimpleThread(); 1282SN/A 1292680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 130180SN/A 1312SN/A void regStats(const std::string &name); 1322SN/A 1332864Sktlim@umich.edu void copyTC(ThreadContext *context); 1342864Sktlim@umich.edu 1352862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1362862Sktlim@umich.edu 137217SN/A void serialize(std::ostream &os); 138237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 139217SN/A 1402683Sktlim@umich.edu /*************************************************************** 1412683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1422683Sktlim@umich.edu * state, and to provide address translation methods. 1432683Sktlim@umich.edu **************************************************************/ 1442190SN/A 1452683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1462683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1472683Sktlim@umich.edu * CPU. 1482683Sktlim@umich.edu */ 1492680SN/A ThreadContext *getTC() { return tc; } 1502190SN/A 1512532SN/A Fault translateInstReq(RequestPtr &req) 1522SN/A { 1532680SN/A return itb->translate(req, tc); 1542SN/A } 1552SN/A 1562532SN/A Fault translateDataReadReq(RequestPtr &req) 1572SN/A { 1582680SN/A return dtb->translate(req, tc, false); 1592SN/A } 1602SN/A 1612532SN/A Fault translateDataWriteReq(RequestPtr &req) 1622SN/A { 1632680SN/A return dtb->translate(req, tc, true); 1642SN/A } 1652SN/A 1665358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1675358Sgblack@eecs.umich.edu { 1685358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1695358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1705358Sgblack@eecs.umich.edu } 1715358Sgblack@eecs.umich.edu 1725358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1735358Sgblack@eecs.umich.edu { 1745358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1755358Sgblack@eecs.umich.edu } 1765358Sgblack@eecs.umich.edu 1775358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1785358Sgblack@eecs.umich.edu { 1795358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1805358Sgblack@eecs.umich.edu } 1815358Sgblack@eecs.umich.edu 1824997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1834997Sgblack@eecs.umich.edu int getInstAsid() { return regs.instAsid(); } 1844997Sgblack@eecs.umich.edu int getDataAsid() { return regs.dataAsid(); } 1854997Sgblack@eecs.umich.edu 1862683Sktlim@umich.edu void dumpFuncProfile(); 1872521SN/A 1885702Ssaidi@eecs.umich.edu Fault hwrei(); 1895702Ssaidi@eecs.umich.edu 1905702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1915702Ssaidi@eecs.umich.edu 1922683Sktlim@umich.edu#endif 1932SN/A 1942683Sktlim@umich.edu /******************************************* 1952683Sktlim@umich.edu * ThreadContext interface functions. 1962683Sktlim@umich.edu ******************************************/ 1972683Sktlim@umich.edu 1982683Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 1992683Sktlim@umich.edu 2003453Sgblack@eecs.umich.edu TheISA::ITB *getITBPtr() { return itb; } 2012683Sktlim@umich.edu 2023453Sgblack@eecs.umich.edu TheISA::DTB *getDTBPtr() { return dtb; } 2032683Sktlim@umich.edu 2044997Sgblack@eecs.umich.edu#if FULL_SYSTEM 2054997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2064997Sgblack@eecs.umich.edu 2072683Sktlim@umich.edu FunctionalPort *getPhysPort() { return physPort; } 2082683Sktlim@umich.edu 2095499Ssaidi@eecs.umich.edu /** Return a virtual port. This port cannot be cached locally in an object. 2105499Ssaidi@eecs.umich.edu * After a CPU switch it may point to the wrong memory object which could 2115499Ssaidi@eecs.umich.edu * mean stale data. 2125499Ssaidi@eecs.umich.edu */ 2135499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return virtPort; } 2142SN/A#endif 2152SN/A 2162683Sktlim@umich.edu Status status() const { return _status; } 2172683Sktlim@umich.edu 2182683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2192683Sktlim@umich.edu 2202683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2212683Sktlim@umich.edu /// cycles to wait before beginning execution. 2222683Sktlim@umich.edu void activate(int delay = 1); 2232683Sktlim@umich.edu 2242683Sktlim@umich.edu /// Set the status to Suspended. 2252683Sktlim@umich.edu void suspend(); 2262683Sktlim@umich.edu 2272683Sktlim@umich.edu /// Set the status to Unallocated. 2282683Sktlim@umich.edu void deallocate(); 2292683Sktlim@umich.edu 2302683Sktlim@umich.edu /// Set the status to Halted. 2312683Sktlim@umich.edu void halt(); 2322683Sktlim@umich.edu 2332SN/A virtual bool misspeculating(); 2342SN/A 2352532SN/A Fault instRead(RequestPtr &req) 236716SN/A { 2372378SN/A panic("instRead not implemented"); 2382378SN/A // return funcPhysMem->read(req, inst); 2392423SN/A return NoFault; 240716SN/A } 241716SN/A 2422683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2432190SN/A 2442683Sktlim@umich.edu void clearArchRegs() { regs.clear(); } 2452190SN/A 2462SN/A // 2472SN/A // New accessors for new decoder. 2482SN/A // 2492SN/A uint64_t readIntReg(int reg_idx) 2502SN/A { 2515082Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); 2525082Sgblack@eecs.umich.edu return regs.readIntReg(flatIndex); 2532SN/A } 2542SN/A 2552455SN/A FloatReg readFloatReg(int reg_idx, int width) 2562SN/A { 2575088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2585082Sgblack@eecs.umich.edu return regs.readFloatReg(flatIndex, width); 2592SN/A } 2602SN/A 2612455SN/A FloatReg readFloatReg(int reg_idx) 2622SN/A { 2635088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2645082Sgblack@eecs.umich.edu return regs.readFloatReg(flatIndex); 2652SN/A } 2662SN/A 2672455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width) 2682SN/A { 2695088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2705082Sgblack@eecs.umich.edu return regs.readFloatRegBits(flatIndex, width); 2712455SN/A } 2722455SN/A 2732455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2742455SN/A { 2755088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2765082Sgblack@eecs.umich.edu return regs.readFloatRegBits(flatIndex); 2772SN/A } 2782SN/A 2792SN/A void setIntReg(int reg_idx, uint64_t val) 2802SN/A { 2815082Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); 2825082Sgblack@eecs.umich.edu regs.setIntReg(flatIndex, val); 2832SN/A } 2842SN/A 2852455SN/A void setFloatReg(int reg_idx, FloatReg val, int width) 2862SN/A { 2875088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2885082Sgblack@eecs.umich.edu regs.setFloatReg(flatIndex, val, width); 2892SN/A } 2902SN/A 2912455SN/A void setFloatReg(int reg_idx, FloatReg val) 2922SN/A { 2935088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 2945082Sgblack@eecs.umich.edu regs.setFloatReg(flatIndex, val); 2952SN/A } 2962SN/A 2972455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 2982SN/A { 2995088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 3005082Sgblack@eecs.umich.edu regs.setFloatRegBits(flatIndex, val, width); 3012455SN/A } 3022455SN/A 3032455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3042455SN/A { 3055088Sgblack@eecs.umich.edu int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); 3065082Sgblack@eecs.umich.edu regs.setFloatRegBits(flatIndex, val); 3072SN/A } 3082SN/A 3092SN/A uint64_t readPC() 3102SN/A { 3112525SN/A return regs.readPC(); 3122SN/A } 3132SN/A 3142190SN/A void setPC(uint64_t val) 3152190SN/A { 3162525SN/A regs.setPC(val); 3172190SN/A } 3182190SN/A 3193276Sgblack@eecs.umich.edu uint64_t readMicroPC() 3203276Sgblack@eecs.umich.edu { 3213276Sgblack@eecs.umich.edu return microPC; 3223276Sgblack@eecs.umich.edu } 3233276Sgblack@eecs.umich.edu 3243276Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) 3253276Sgblack@eecs.umich.edu { 3263276Sgblack@eecs.umich.edu microPC = val; 3273276Sgblack@eecs.umich.edu } 3283276Sgblack@eecs.umich.edu 3292190SN/A uint64_t readNextPC() 3302190SN/A { 3312525SN/A return regs.readNextPC(); 3322190SN/A } 3332190SN/A 3342SN/A void setNextPC(uint64_t val) 3352SN/A { 3362525SN/A regs.setNextPC(val); 3372SN/A } 3382SN/A 3393276Sgblack@eecs.umich.edu uint64_t readNextMicroPC() 3403276Sgblack@eecs.umich.edu { 3413276Sgblack@eecs.umich.edu return nextMicroPC; 3423276Sgblack@eecs.umich.edu } 3433276Sgblack@eecs.umich.edu 3443276Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) 3453276Sgblack@eecs.umich.edu { 3463276Sgblack@eecs.umich.edu nextMicroPC = val; 3473276Sgblack@eecs.umich.edu } 3483276Sgblack@eecs.umich.edu 3492252SN/A uint64_t readNextNPC() 3502252SN/A { 3512525SN/A return regs.readNextNPC(); 3522252SN/A } 3532252SN/A 3542251SN/A void setNextNPC(uint64_t val) 3552251SN/A { 3562525SN/A regs.setNextNPC(val); 3572251SN/A } 3582251SN/A 3594661Sksewell@umich.edu MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0) 3604172Ssaidi@eecs.umich.edu { 3614172Ssaidi@eecs.umich.edu return regs.readMiscRegNoEffect(misc_reg); 3624172Ssaidi@eecs.umich.edu } 3634172Ssaidi@eecs.umich.edu 3644661Sksewell@umich.edu MiscReg readMiscReg(int misc_reg, unsigned tid = 0) 3652SN/A { 3664172Ssaidi@eecs.umich.edu return regs.readMiscReg(misc_reg, tc); 3672SN/A } 3682SN/A 3694661Sksewell@umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0) 3702SN/A { 3714172Ssaidi@eecs.umich.edu return regs.setMiscRegNoEffect(misc_reg, val); 3722SN/A } 3732SN/A 3744661Sksewell@umich.edu void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0) 3752SN/A { 3764172Ssaidi@eecs.umich.edu return regs.setMiscReg(misc_reg, val, tc); 3772SN/A } 3782SN/A 3792190SN/A unsigned readStCondFailures() { return storeCondFailures; } 3802190SN/A 3812190SN/A void setStCondFailures(unsigned sc_failures) 3822190SN/A { storeCondFailures = sc_failures; } 3832190SN/A 3841858SN/A#if !FULL_SYSTEM 3852107SN/A TheISA::IntReg getSyscallArg(int i) 386360SN/A { 3874772Sgblack@eecs.umich.edu assert(i < TheISA::NumArgumentRegs); 3885779Sgblack@eecs.umich.edu TheISA::IntReg val = regs.readIntReg( 3895779Sgblack@eecs.umich.edu TheISA::flattenIntIndex(getTC(), TheISA::ArgumentReg[i])); 3905779Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 3915779Sgblack@eecs.umich.edu if (bits(this->readMiscRegNoEffect( 3925779Sgblack@eecs.umich.edu SparcISA::MISCREG_PSTATE), 3, 3)) { 3935779Sgblack@eecs.umich.edu val = bits(val, 31, 0); 3945779Sgblack@eecs.umich.edu } 3955779Sgblack@eecs.umich.edu#endif 3965779Sgblack@eecs.umich.edu return val; 397360SN/A } 398360SN/A 399360SN/A // used to shift args for indirect syscall 4002107SN/A void setSyscallArg(int i, TheISA::IntReg val) 401360SN/A { 4024772Sgblack@eecs.umich.edu assert(i < TheISA::NumArgumentRegs); 4033776Sgblack@eecs.umich.edu regs.setIntReg(TheISA::flattenIntIndex(getTC(), 4044772Sgblack@eecs.umich.edu TheISA::ArgumentReg[i]), val); 405360SN/A } 406360SN/A 4071450SN/A void setSyscallReturn(SyscallReturn return_value) 408360SN/A { 4093776Sgblack@eecs.umich.edu TheISA::setSyscallReturn(return_value, getTC()); 410360SN/A } 411360SN/A 4122561SN/A void syscall(int64_t callnum) 4132SN/A { 4142680SN/A process->syscall(callnum, tc); 4152SN/A } 4162SN/A#endif 4172SN/A}; 4182SN/A 4192SN/A 4202SN/A// for non-speculative execution context, spec_mode is always false 4212SN/Ainline bool 4222683Sktlim@umich.eduSimpleThread::misspeculating() 4232SN/A{ 4242SN/A return false; 4252SN/A} 4262SN/A 4272190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 428