simple_thread.hh revision 4997
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302SN/A */ 312SN/A 322683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 332683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 342SN/A 352190SN/A#include "arch/isa_traits.hh" 363776Sgblack@eecs.umich.edu#include "arch/regfile.hh" 373776Sgblack@eecs.umich.edu#include "arch/syscallreturn.hh" 384997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 391858SN/A#include "config/full_system.hh" 402680SN/A#include "cpu/thread_context.hh" 412683Sktlim@umich.edu#include "cpu/thread_state.hh" 422395SN/A#include "mem/request.hh" 432190SN/A#include "sim/byteswap.hh" 442188SN/A#include "sim/eventq.hh" 4556SN/A#include "sim/host.hh" 46217SN/A#include "sim/serialize.hh" 472SN/A 482SN/Aclass BaseCPU; 492SN/A 501858SN/A#if FULL_SYSTEM 512SN/A 521070SN/A#include "sim/system.hh" 531070SN/A 541917SN/Aclass FunctionProfile; 551917SN/Aclass ProfileNode; 562521SN/Aclass FunctionalPort; 572521SN/Aclass PhysicalPort; 582521SN/A 593548Sgblack@eecs.umich.edunamespace TheISA { 603548Sgblack@eecs.umich.edu namespace Kernel { 613548Sgblack@eecs.umich.edu class Statistics; 623548Sgblack@eecs.umich.edu }; 632330SN/A}; 642330SN/A 652SN/A#else // !FULL_SYSTEM 662SN/A 67360SN/A#include "sim/process.hh" 682462SN/A#include "mem/page_table.hh" 692420SN/Aclass TranslatingPort; 702SN/A 712SN/A#endif // FULL_SYSTEM 722SN/A 732683Sktlim@umich.edu/** 742683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 752683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 762683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 772683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 782683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 792683Sktlim@umich.edu * the objects needed for simple functional execution, including a 802683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 812683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 822683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 832683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 842683Sktlim@umich.edu * all the necessary state for full architecture-level functional 852683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 862683Sktlim@umich.edu * examples. 872683Sktlim@umich.edu */ 882SN/A 892683Sktlim@umich.educlass SimpleThread : public ThreadState 902SN/A{ 912107SN/A protected: 922107SN/A typedef TheISA::RegFile RegFile; 932107SN/A typedef TheISA::MachInst MachInst; 942107SN/A typedef TheISA::MiscRegFile MiscRegFile; 952159SN/A typedef TheISA::MiscReg MiscReg; 962455SN/A typedef TheISA::FloatReg FloatReg; 972455SN/A typedef TheISA::FloatRegBits FloatRegBits; 982SN/A public: 992680SN/A typedef ThreadContext::Status Status; 1002SN/A 1012190SN/A protected: 1022SN/A RegFile regs; // correct-path register context 1032SN/A 1042190SN/A public: 1052683Sktlim@umich.edu // pointer to CPU associated with this SimpleThread 1062SN/A BaseCPU *cpu; 1072SN/A 1082683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1092188SN/A 1102378SN/A System *system; 1112400SN/A 1123453Sgblack@eecs.umich.edu TheISA::ITB *itb; 1133453Sgblack@eecs.umich.edu TheISA::DTB *dtb; 1142SN/A 1152683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1161858SN/A#if FULL_SYSTEM 1172683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1183453Sgblack@eecs.umich.edu TheISA::ITB *_itb, TheISA::DTB *_dtb, 1192683Sktlim@umich.edu bool use_kernel_stats = true); 1202SN/A#else 1214997Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 1224997Sgblack@eecs.umich.edu TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid); 1232SN/A#endif 1242862Sktlim@umich.edu 1252864Sktlim@umich.edu SimpleThread(); 1262862Sktlim@umich.edu 1272683Sktlim@umich.edu virtual ~SimpleThread(); 1282SN/A 1292680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 130180SN/A 1312SN/A void regStats(const std::string &name); 1322SN/A 1332864Sktlim@umich.edu void copyTC(ThreadContext *context); 1342864Sktlim@umich.edu 1352862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1362862Sktlim@umich.edu 137217SN/A void serialize(std::ostream &os); 138237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 139217SN/A 1402683Sktlim@umich.edu /*************************************************************** 1412683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1422683Sktlim@umich.edu * state, and to provide address translation methods. 1432683Sktlim@umich.edu **************************************************************/ 1442190SN/A 1452683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1462683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1472683Sktlim@umich.edu * CPU. 1482683Sktlim@umich.edu */ 1492680SN/A ThreadContext *getTC() { return tc; } 1502190SN/A 1512532SN/A Fault translateInstReq(RequestPtr &req) 1522SN/A { 1532680SN/A return itb->translate(req, tc); 1542SN/A } 1552SN/A 1562532SN/A Fault translateDataReadReq(RequestPtr &req) 1572SN/A { 1582680SN/A return dtb->translate(req, tc, false); 1592SN/A } 1602SN/A 1612532SN/A Fault translateDataWriteReq(RequestPtr &req) 1622SN/A { 1632680SN/A return dtb->translate(req, tc, true); 1642SN/A } 1652SN/A 1664997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1674997Sgblack@eecs.umich.edu int getInstAsid() { return regs.instAsid(); } 1684997Sgblack@eecs.umich.edu int getDataAsid() { return regs.dataAsid(); } 1694997Sgblack@eecs.umich.edu 1702683Sktlim@umich.edu void dumpFuncProfile(); 1712521SN/A 1722683Sktlim@umich.edu Fault hwrei(); 1732521SN/A 1742683Sktlim@umich.edu bool simPalCheck(int palFunc); 1753402Sktlim@umich.edu 1762683Sktlim@umich.edu#endif 1772SN/A 1782683Sktlim@umich.edu /******************************************* 1792683Sktlim@umich.edu * ThreadContext interface functions. 1802683Sktlim@umich.edu ******************************************/ 1812683Sktlim@umich.edu 1822683Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 1832683Sktlim@umich.edu 1842683Sktlim@umich.edu int getThreadNum() { return tid; } 1852683Sktlim@umich.edu 1863453Sgblack@eecs.umich.edu TheISA::ITB *getITBPtr() { return itb; } 1872683Sktlim@umich.edu 1883453Sgblack@eecs.umich.edu TheISA::DTB *getDTBPtr() { return dtb; } 1892683Sktlim@umich.edu 1904997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1914997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 1924997Sgblack@eecs.umich.edu 1932683Sktlim@umich.edu FunctionalPort *getPhysPort() { return physPort; } 1942683Sktlim@umich.edu 1952683Sktlim@umich.edu /** Return a virtual port. If no thread context is specified then a static 1962683Sktlim@umich.edu * port is returned. Otherwise a port is created and returned. It must be 1972683Sktlim@umich.edu * deleted by deleteVirtPort(). */ 1982683Sktlim@umich.edu VirtualPort *getVirtPort(ThreadContext *tc); 1992683Sktlim@umich.edu 2002683Sktlim@umich.edu void delVirtPort(VirtualPort *vp); 2012SN/A#endif 2022SN/A 2032683Sktlim@umich.edu Status status() const { return _status; } 2042683Sktlim@umich.edu 2052683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2062683Sktlim@umich.edu 2072683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2082683Sktlim@umich.edu /// cycles to wait before beginning execution. 2092683Sktlim@umich.edu void activate(int delay = 1); 2102683Sktlim@umich.edu 2112683Sktlim@umich.edu /// Set the status to Suspended. 2122683Sktlim@umich.edu void suspend(); 2132683Sktlim@umich.edu 2142683Sktlim@umich.edu /// Set the status to Unallocated. 2152683Sktlim@umich.edu void deallocate(); 2162683Sktlim@umich.edu 2172683Sktlim@umich.edu /// Set the status to Halted. 2182683Sktlim@umich.edu void halt(); 2192683Sktlim@umich.edu 2202SN/A virtual bool misspeculating(); 2212SN/A 2222532SN/A Fault instRead(RequestPtr &req) 223716SN/A { 2242378SN/A panic("instRead not implemented"); 2252378SN/A // return funcPhysMem->read(req, inst); 2262423SN/A return NoFault; 227716SN/A } 228716SN/A 2292683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2302190SN/A 2312683Sktlim@umich.edu void clearArchRegs() { regs.clear(); } 2322190SN/A 2332SN/A // 2342SN/A // New accessors for new decoder. 2352SN/A // 2362SN/A uint64_t readIntReg(int reg_idx) 2372SN/A { 2383776Sgblack@eecs.umich.edu return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx)); 2392SN/A } 2402SN/A 2412455SN/A FloatReg readFloatReg(int reg_idx, int width) 2422SN/A { 2432525SN/A return regs.readFloatReg(reg_idx, width); 2442SN/A } 2452SN/A 2462455SN/A FloatReg readFloatReg(int reg_idx) 2472SN/A { 2482525SN/A return regs.readFloatReg(reg_idx); 2492SN/A } 2502SN/A 2512455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width) 2522SN/A { 2532525SN/A return regs.readFloatRegBits(reg_idx, width); 2542455SN/A } 2552455SN/A 2562455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2572455SN/A { 2582525SN/A return regs.readFloatRegBits(reg_idx); 2592SN/A } 2602SN/A 2612SN/A void setIntReg(int reg_idx, uint64_t val) 2622SN/A { 2633776Sgblack@eecs.umich.edu regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val); 2642SN/A } 2652SN/A 2662455SN/A void setFloatReg(int reg_idx, FloatReg val, int width) 2672SN/A { 2682525SN/A regs.setFloatReg(reg_idx, val, width); 2692SN/A } 2702SN/A 2712455SN/A void setFloatReg(int reg_idx, FloatReg val) 2722SN/A { 2732525SN/A regs.setFloatReg(reg_idx, val); 2742SN/A } 2752SN/A 2762455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 2772SN/A { 2782525SN/A regs.setFloatRegBits(reg_idx, val, width); 2792455SN/A } 2802455SN/A 2812455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2822455SN/A { 2832525SN/A regs.setFloatRegBits(reg_idx, val); 2842SN/A } 2852SN/A 2862SN/A uint64_t readPC() 2872SN/A { 2882525SN/A return regs.readPC(); 2892SN/A } 2902SN/A 2912190SN/A void setPC(uint64_t val) 2922190SN/A { 2932525SN/A regs.setPC(val); 2942190SN/A } 2952190SN/A 2963276Sgblack@eecs.umich.edu uint64_t readMicroPC() 2973276Sgblack@eecs.umich.edu { 2983276Sgblack@eecs.umich.edu return microPC; 2993276Sgblack@eecs.umich.edu } 3003276Sgblack@eecs.umich.edu 3013276Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) 3023276Sgblack@eecs.umich.edu { 3033276Sgblack@eecs.umich.edu microPC = val; 3043276Sgblack@eecs.umich.edu } 3053276Sgblack@eecs.umich.edu 3062190SN/A uint64_t readNextPC() 3072190SN/A { 3082525SN/A return regs.readNextPC(); 3092190SN/A } 3102190SN/A 3112SN/A void setNextPC(uint64_t val) 3122SN/A { 3132525SN/A regs.setNextPC(val); 3142SN/A } 3152SN/A 3163276Sgblack@eecs.umich.edu uint64_t readNextMicroPC() 3173276Sgblack@eecs.umich.edu { 3183276Sgblack@eecs.umich.edu return nextMicroPC; 3193276Sgblack@eecs.umich.edu } 3203276Sgblack@eecs.umich.edu 3213276Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) 3223276Sgblack@eecs.umich.edu { 3233276Sgblack@eecs.umich.edu nextMicroPC = val; 3243276Sgblack@eecs.umich.edu } 3253276Sgblack@eecs.umich.edu 3262252SN/A uint64_t readNextNPC() 3272252SN/A { 3282525SN/A return regs.readNextNPC(); 3292252SN/A } 3302252SN/A 3312251SN/A void setNextNPC(uint64_t val) 3322251SN/A { 3332525SN/A regs.setNextNPC(val); 3342251SN/A } 3352251SN/A 3364661Sksewell@umich.edu MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0) 3374172Ssaidi@eecs.umich.edu { 3384172Ssaidi@eecs.umich.edu return regs.readMiscRegNoEffect(misc_reg); 3394172Ssaidi@eecs.umich.edu } 3404172Ssaidi@eecs.umich.edu 3414661Sksewell@umich.edu MiscReg readMiscReg(int misc_reg, unsigned tid = 0) 3422SN/A { 3434172Ssaidi@eecs.umich.edu return regs.readMiscReg(misc_reg, tc); 3442SN/A } 3452SN/A 3464661Sksewell@umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0) 3472SN/A { 3484172Ssaidi@eecs.umich.edu return regs.setMiscRegNoEffect(misc_reg, val); 3492SN/A } 3502SN/A 3514661Sksewell@umich.edu void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0) 3522SN/A { 3534172Ssaidi@eecs.umich.edu return regs.setMiscReg(misc_reg, val, tc); 3542SN/A } 3552SN/A 3562190SN/A unsigned readStCondFailures() { return storeCondFailures; } 3572190SN/A 3582190SN/A void setStCondFailures(unsigned sc_failures) 3592190SN/A { storeCondFailures = sc_failures; } 3602190SN/A 3611858SN/A#if !FULL_SYSTEM 3622107SN/A TheISA::IntReg getSyscallArg(int i) 363360SN/A { 3644772Sgblack@eecs.umich.edu assert(i < TheISA::NumArgumentRegs); 3653776Sgblack@eecs.umich.edu return regs.readIntReg(TheISA::flattenIntIndex(getTC(), 3664772Sgblack@eecs.umich.edu TheISA::ArgumentReg[i])); 367360SN/A } 368360SN/A 369360SN/A // used to shift args for indirect syscall 3702107SN/A void setSyscallArg(int i, TheISA::IntReg val) 371360SN/A { 3724772Sgblack@eecs.umich.edu assert(i < TheISA::NumArgumentRegs); 3733776Sgblack@eecs.umich.edu regs.setIntReg(TheISA::flattenIntIndex(getTC(), 3744772Sgblack@eecs.umich.edu TheISA::ArgumentReg[i]), val); 375360SN/A } 376360SN/A 3771450SN/A void setSyscallReturn(SyscallReturn return_value) 378360SN/A { 3793776Sgblack@eecs.umich.edu TheISA::setSyscallReturn(return_value, getTC()); 380360SN/A } 381360SN/A 3822561SN/A void syscall(int64_t callnum) 3832SN/A { 3842680SN/A process->syscall(callnum, tc); 3852SN/A } 3862SN/A#endif 3872525SN/A 3882972Sgblack@eecs.umich.edu void changeRegFileContext(TheISA::RegContextParam param, 3892972Sgblack@eecs.umich.edu TheISA::RegContextVal val) 3902525SN/A { 3912525SN/A regs.changeContext(param, val); 3922525SN/A } 3932SN/A}; 3942SN/A 3952SN/A 3962SN/A// for non-speculative execution context, spec_mode is always false 3972SN/Ainline bool 3982683Sktlim@umich.eduSimpleThread::misspeculating() 3992SN/A{ 4002SN/A return false; 4012SN/A} 4022SN/A 4032190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 404