simple_thread.hh revision 4772
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302SN/A */ 312SN/A 322683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 332683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 342SN/A 352190SN/A#include "arch/isa_traits.hh" 363776Sgblack@eecs.umich.edu#include "arch/regfile.hh" 373776Sgblack@eecs.umich.edu#include "arch/syscallreturn.hh" 381858SN/A#include "config/full_system.hh" 392680SN/A#include "cpu/thread_context.hh" 402683Sktlim@umich.edu#include "cpu/thread_state.hh" 412395SN/A#include "mem/request.hh" 422190SN/A#include "sim/byteswap.hh" 432188SN/A#include "sim/eventq.hh" 4456SN/A#include "sim/host.hh" 45217SN/A#include "sim/serialize.hh" 462SN/A 472SN/Aclass BaseCPU; 482SN/A 491858SN/A#if FULL_SYSTEM 502SN/A 511070SN/A#include "sim/system.hh" 522171SN/A#include "arch/tlb.hh" 531070SN/A 541917SN/Aclass FunctionProfile; 551917SN/Aclass ProfileNode; 562521SN/Aclass FunctionalPort; 572521SN/Aclass PhysicalPort; 582521SN/A 593548Sgblack@eecs.umich.edunamespace TheISA { 603548Sgblack@eecs.umich.edu namespace Kernel { 613548Sgblack@eecs.umich.edu class Statistics; 623548Sgblack@eecs.umich.edu }; 632330SN/A}; 642330SN/A 652SN/A#else // !FULL_SYSTEM 662SN/A 67360SN/A#include "sim/process.hh" 682462SN/A#include "mem/page_table.hh" 692420SN/Aclass TranslatingPort; 702SN/A 712SN/A#endif // FULL_SYSTEM 722SN/A 732683Sktlim@umich.edu/** 742683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 752683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 762683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 772683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 782683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 792683Sktlim@umich.edu * the objects needed for simple functional execution, including a 802683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 812683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 822683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 832683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 842683Sktlim@umich.edu * all the necessary state for full architecture-level functional 852683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 862683Sktlim@umich.edu * examples. 872683Sktlim@umich.edu */ 882SN/A 892683Sktlim@umich.educlass SimpleThread : public ThreadState 902SN/A{ 912107SN/A protected: 922107SN/A typedef TheISA::RegFile RegFile; 932107SN/A typedef TheISA::MachInst MachInst; 942107SN/A typedef TheISA::MiscRegFile MiscRegFile; 952159SN/A typedef TheISA::MiscReg MiscReg; 962455SN/A typedef TheISA::FloatReg FloatReg; 972455SN/A typedef TheISA::FloatRegBits FloatRegBits; 982SN/A public: 992680SN/A typedef ThreadContext::Status Status; 1002SN/A 1012190SN/A protected: 1022SN/A RegFile regs; // correct-path register context 1032SN/A 1042190SN/A public: 1052683Sktlim@umich.edu // pointer to CPU associated with this SimpleThread 1062SN/A BaseCPU *cpu; 1072SN/A 1082683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1092188SN/A 1102378SN/A System *system; 1112400SN/A 1121858SN/A#if FULL_SYSTEM 1133453Sgblack@eecs.umich.edu TheISA::ITB *itb; 1143453Sgblack@eecs.umich.edu TheISA::DTB *dtb; 1152SN/A#endif 1162SN/A 1172683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1181858SN/A#if FULL_SYSTEM 1192683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1203453Sgblack@eecs.umich.edu TheISA::ITB *_itb, TheISA::DTB *_dtb, 1212683Sktlim@umich.edu bool use_kernel_stats = true); 1222SN/A#else 1233402Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); 1242SN/A#endif 1252862Sktlim@umich.edu 1262864Sktlim@umich.edu SimpleThread(); 1272862Sktlim@umich.edu 1282683Sktlim@umich.edu virtual ~SimpleThread(); 1292SN/A 1302680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 131180SN/A 1322SN/A void regStats(const std::string &name); 1332SN/A 1342864Sktlim@umich.edu void copyTC(ThreadContext *context); 1352864Sktlim@umich.edu 1362862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1372862Sktlim@umich.edu 138217SN/A void serialize(std::ostream &os); 139237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 140217SN/A 1412683Sktlim@umich.edu /*************************************************************** 1422683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1432683Sktlim@umich.edu * state, and to provide address translation methods. 1442683Sktlim@umich.edu **************************************************************/ 1452190SN/A 1462683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1472683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1482683Sktlim@umich.edu * CPU. 1492683Sktlim@umich.edu */ 1502680SN/A ThreadContext *getTC() { return tc; } 1512190SN/A 1521858SN/A#if FULL_SYSTEM 1531147SN/A int getInstAsid() { return regs.instAsid(); } 1541147SN/A int getDataAsid() { return regs.dataAsid(); } 1552SN/A 1562532SN/A Fault translateInstReq(RequestPtr &req) 1572SN/A { 1582680SN/A return itb->translate(req, tc); 1592SN/A } 1602SN/A 1612532SN/A Fault translateDataReadReq(RequestPtr &req) 1622SN/A { 1632680SN/A return dtb->translate(req, tc, false); 1642SN/A } 1652SN/A 1662532SN/A Fault translateDataWriteReq(RequestPtr &req) 1672SN/A { 1682680SN/A return dtb->translate(req, tc, true); 1692SN/A } 1702SN/A 1712683Sktlim@umich.edu void dumpFuncProfile(); 1722521SN/A 1732683Sktlim@umich.edu Fault hwrei(); 1742521SN/A 1752683Sktlim@umich.edu bool simPalCheck(int palFunc); 1762SN/A#else 1773402Sktlim@umich.edu 1782532SN/A Fault translateInstReq(RequestPtr &req) 1792SN/A { 1802378SN/A return process->pTable->translate(req); 1811917SN/A } 1822SN/A 1832532SN/A Fault translateDataReadReq(RequestPtr &req) 1841917SN/A { 1852378SN/A return process->pTable->translate(req); 1862SN/A } 1872378SN/A 1882532SN/A Fault translateDataWriteReq(RequestPtr &req) 1892SN/A { 1902378SN/A return process->pTable->translate(req); 1912SN/A } 1922683Sktlim@umich.edu#endif 1932SN/A 1942683Sktlim@umich.edu /******************************************* 1952683Sktlim@umich.edu * ThreadContext interface functions. 1962683Sktlim@umich.edu ******************************************/ 1972683Sktlim@umich.edu 1982683Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 1992683Sktlim@umich.edu 2002683Sktlim@umich.edu int getThreadNum() { return tid; } 2012683Sktlim@umich.edu 2022683Sktlim@umich.edu#if FULL_SYSTEM 2032683Sktlim@umich.edu System *getSystemPtr() { return system; } 2042683Sktlim@umich.edu 2053453Sgblack@eecs.umich.edu TheISA::ITB *getITBPtr() { return itb; } 2062683Sktlim@umich.edu 2073453Sgblack@eecs.umich.edu TheISA::DTB *getDTBPtr() { return dtb; } 2082683Sktlim@umich.edu 2092683Sktlim@umich.edu FunctionalPort *getPhysPort() { return physPort; } 2102683Sktlim@umich.edu 2112683Sktlim@umich.edu /** Return a virtual port. If no thread context is specified then a static 2122683Sktlim@umich.edu * port is returned. Otherwise a port is created and returned. It must be 2132683Sktlim@umich.edu * deleted by deleteVirtPort(). */ 2142683Sktlim@umich.edu VirtualPort *getVirtPort(ThreadContext *tc); 2152683Sktlim@umich.edu 2162683Sktlim@umich.edu void delVirtPort(VirtualPort *vp); 2172SN/A#endif 2182SN/A 2192683Sktlim@umich.edu Status status() const { return _status; } 2202683Sktlim@umich.edu 2212683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2222683Sktlim@umich.edu 2232683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2242683Sktlim@umich.edu /// cycles to wait before beginning execution. 2252683Sktlim@umich.edu void activate(int delay = 1); 2262683Sktlim@umich.edu 2272683Sktlim@umich.edu /// Set the status to Suspended. 2282683Sktlim@umich.edu void suspend(); 2292683Sktlim@umich.edu 2302683Sktlim@umich.edu /// Set the status to Unallocated. 2312683Sktlim@umich.edu void deallocate(); 2322683Sktlim@umich.edu 2332683Sktlim@umich.edu /// Set the status to Halted. 2342683Sktlim@umich.edu void halt(); 2352683Sktlim@umich.edu 2362SN/A virtual bool misspeculating(); 2372SN/A 2382532SN/A Fault instRead(RequestPtr &req) 239716SN/A { 2402378SN/A panic("instRead not implemented"); 2412378SN/A // return funcPhysMem->read(req, inst); 2422423SN/A return NoFault; 243716SN/A } 244716SN/A 2452683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2462190SN/A 2472683Sktlim@umich.edu void clearArchRegs() { regs.clear(); } 2482190SN/A 2492SN/A // 2502SN/A // New accessors for new decoder. 2512SN/A // 2522SN/A uint64_t readIntReg(int reg_idx) 2532SN/A { 2543776Sgblack@eecs.umich.edu return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx)); 2552SN/A } 2562SN/A 2572455SN/A FloatReg readFloatReg(int reg_idx, int width) 2582SN/A { 2592525SN/A return regs.readFloatReg(reg_idx, width); 2602SN/A } 2612SN/A 2622455SN/A FloatReg readFloatReg(int reg_idx) 2632SN/A { 2642525SN/A return regs.readFloatReg(reg_idx); 2652SN/A } 2662SN/A 2672455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width) 2682SN/A { 2692525SN/A return regs.readFloatRegBits(reg_idx, width); 2702455SN/A } 2712455SN/A 2722455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2732455SN/A { 2742525SN/A return regs.readFloatRegBits(reg_idx); 2752SN/A } 2762SN/A 2772SN/A void setIntReg(int reg_idx, uint64_t val) 2782SN/A { 2793776Sgblack@eecs.umich.edu regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val); 2802SN/A } 2812SN/A 2822455SN/A void setFloatReg(int reg_idx, FloatReg val, int width) 2832SN/A { 2842525SN/A regs.setFloatReg(reg_idx, val, width); 2852SN/A } 2862SN/A 2872455SN/A void setFloatReg(int reg_idx, FloatReg val) 2882SN/A { 2892525SN/A regs.setFloatReg(reg_idx, val); 2902SN/A } 2912SN/A 2922455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 2932SN/A { 2942525SN/A regs.setFloatRegBits(reg_idx, val, width); 2952455SN/A } 2962455SN/A 2972455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2982455SN/A { 2992525SN/A regs.setFloatRegBits(reg_idx, val); 3002SN/A } 3012SN/A 3022SN/A uint64_t readPC() 3032SN/A { 3042525SN/A return regs.readPC(); 3052SN/A } 3062SN/A 3072190SN/A void setPC(uint64_t val) 3082190SN/A { 3092525SN/A regs.setPC(val); 3102190SN/A } 3112190SN/A 3123276Sgblack@eecs.umich.edu uint64_t readMicroPC() 3133276Sgblack@eecs.umich.edu { 3143276Sgblack@eecs.umich.edu return microPC; 3153276Sgblack@eecs.umich.edu } 3163276Sgblack@eecs.umich.edu 3173276Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) 3183276Sgblack@eecs.umich.edu { 3193276Sgblack@eecs.umich.edu microPC = val; 3203276Sgblack@eecs.umich.edu } 3213276Sgblack@eecs.umich.edu 3222190SN/A uint64_t readNextPC() 3232190SN/A { 3242525SN/A return regs.readNextPC(); 3252190SN/A } 3262190SN/A 3272SN/A void setNextPC(uint64_t val) 3282SN/A { 3292525SN/A regs.setNextPC(val); 3302SN/A } 3312SN/A 3323276Sgblack@eecs.umich.edu uint64_t readNextMicroPC() 3333276Sgblack@eecs.umich.edu { 3343276Sgblack@eecs.umich.edu return nextMicroPC; 3353276Sgblack@eecs.umich.edu } 3363276Sgblack@eecs.umich.edu 3373276Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) 3383276Sgblack@eecs.umich.edu { 3393276Sgblack@eecs.umich.edu nextMicroPC = val; 3403276Sgblack@eecs.umich.edu } 3413276Sgblack@eecs.umich.edu 3422252SN/A uint64_t readNextNPC() 3432252SN/A { 3442525SN/A return regs.readNextNPC(); 3452252SN/A } 3462252SN/A 3472251SN/A void setNextNPC(uint64_t val) 3482251SN/A { 3492525SN/A regs.setNextNPC(val); 3502251SN/A } 3512251SN/A 3524661Sksewell@umich.edu MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0) 3534172Ssaidi@eecs.umich.edu { 3544172Ssaidi@eecs.umich.edu return regs.readMiscRegNoEffect(misc_reg); 3554172Ssaidi@eecs.umich.edu } 3564172Ssaidi@eecs.umich.edu 3574661Sksewell@umich.edu MiscReg readMiscReg(int misc_reg, unsigned tid = 0) 3582SN/A { 3594172Ssaidi@eecs.umich.edu return regs.readMiscReg(misc_reg, tc); 3602SN/A } 3612SN/A 3624661Sksewell@umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0) 3632SN/A { 3644172Ssaidi@eecs.umich.edu return regs.setMiscRegNoEffect(misc_reg, val); 3652SN/A } 3662SN/A 3674661Sksewell@umich.edu void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0) 3682SN/A { 3694172Ssaidi@eecs.umich.edu return regs.setMiscReg(misc_reg, val, tc); 3702SN/A } 3712SN/A 3722190SN/A unsigned readStCondFailures() { return storeCondFailures; } 3732190SN/A 3742190SN/A void setStCondFailures(unsigned sc_failures) 3752190SN/A { storeCondFailures = sc_failures; } 3762190SN/A 3771858SN/A#if !FULL_SYSTEM 3782107SN/A TheISA::IntReg getSyscallArg(int i) 379360SN/A { 3804772Sgblack@eecs.umich.edu assert(i < TheISA::NumArgumentRegs); 3813776Sgblack@eecs.umich.edu return regs.readIntReg(TheISA::flattenIntIndex(getTC(), 3824772Sgblack@eecs.umich.edu TheISA::ArgumentReg[i])); 383360SN/A } 384360SN/A 385360SN/A // used to shift args for indirect syscall 3862107SN/A void setSyscallArg(int i, TheISA::IntReg val) 387360SN/A { 3884772Sgblack@eecs.umich.edu assert(i < TheISA::NumArgumentRegs); 3893776Sgblack@eecs.umich.edu regs.setIntReg(TheISA::flattenIntIndex(getTC(), 3904772Sgblack@eecs.umich.edu TheISA::ArgumentReg[i]), val); 391360SN/A } 392360SN/A 3931450SN/A void setSyscallReturn(SyscallReturn return_value) 394360SN/A { 3953776Sgblack@eecs.umich.edu TheISA::setSyscallReturn(return_value, getTC()); 396360SN/A } 397360SN/A 3982561SN/A void syscall(int64_t callnum) 3992SN/A { 4002680SN/A process->syscall(callnum, tc); 4012SN/A } 4022SN/A#endif 4032525SN/A 4042972Sgblack@eecs.umich.edu void changeRegFileContext(TheISA::RegContextParam param, 4052972Sgblack@eecs.umich.edu TheISA::RegContextVal val) 4062525SN/A { 4072525SN/A regs.changeContext(param, val); 4082525SN/A } 4092SN/A}; 4102SN/A 4112SN/A 4122SN/A// for non-speculative execution context, spec_mode is always false 4132SN/Ainline bool 4142683Sktlim@umich.eduSimpleThread::misspeculating() 4152SN/A{ 4162SN/A return false; 4172SN/A} 4182SN/A 4192190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 420