simple_thread.hh revision 4172
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302SN/A */ 312SN/A 322683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 332683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 342SN/A 352190SN/A#include "arch/isa_traits.hh" 363776Sgblack@eecs.umich.edu#include "arch/regfile.hh" 373776Sgblack@eecs.umich.edu#include "arch/syscallreturn.hh" 381858SN/A#include "config/full_system.hh" 392680SN/A#include "cpu/thread_context.hh" 402683Sktlim@umich.edu#include "cpu/thread_state.hh" 412395SN/A#include "mem/physical.hh" 422395SN/A#include "mem/request.hh" 432190SN/A#include "sim/byteswap.hh" 442188SN/A#include "sim/eventq.hh" 4556SN/A#include "sim/host.hh" 46217SN/A#include "sim/serialize.hh" 472SN/A 482SN/Aclass BaseCPU; 492SN/A 501858SN/A#if FULL_SYSTEM 512SN/A 521070SN/A#include "sim/system.hh" 532171SN/A#include "arch/tlb.hh" 541070SN/A 551917SN/Aclass FunctionProfile; 561917SN/Aclass ProfileNode; 572521SN/Aclass FunctionalPort; 582521SN/Aclass PhysicalPort; 592521SN/A 603548Sgblack@eecs.umich.edunamespace TheISA { 613548Sgblack@eecs.umich.edu namespace Kernel { 623548Sgblack@eecs.umich.edu class Statistics; 633548Sgblack@eecs.umich.edu }; 642330SN/A}; 652330SN/A 662SN/A#else // !FULL_SYSTEM 672SN/A 68360SN/A#include "sim/process.hh" 692462SN/A#include "mem/page_table.hh" 702420SN/Aclass TranslatingPort; 712SN/A 722SN/A#endif // FULL_SYSTEM 732SN/A 742683Sktlim@umich.edu/** 752683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 762683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 772683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 782683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 792683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 802683Sktlim@umich.edu * the objects needed for simple functional execution, including a 812683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 822683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 832683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 842683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 852683Sktlim@umich.edu * all the necessary state for full architecture-level functional 862683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 872683Sktlim@umich.edu * examples. 882683Sktlim@umich.edu */ 892SN/A 902683Sktlim@umich.educlass SimpleThread : public ThreadState 912SN/A{ 922107SN/A protected: 932107SN/A typedef TheISA::RegFile RegFile; 942107SN/A typedef TheISA::MachInst MachInst; 952107SN/A typedef TheISA::MiscRegFile MiscRegFile; 962159SN/A typedef TheISA::MiscReg MiscReg; 972455SN/A typedef TheISA::FloatReg FloatReg; 982455SN/A typedef TheISA::FloatRegBits FloatRegBits; 992SN/A public: 1002680SN/A typedef ThreadContext::Status Status; 1012SN/A 1022190SN/A protected: 1032SN/A RegFile regs; // correct-path register context 1042SN/A 1052190SN/A public: 1062683Sktlim@umich.edu // pointer to CPU associated with this SimpleThread 1072SN/A BaseCPU *cpu; 1082SN/A 1092683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1102188SN/A 1112378SN/A System *system; 1122400SN/A 1131858SN/A#if FULL_SYSTEM 1143453Sgblack@eecs.umich.edu TheISA::ITB *itb; 1153453Sgblack@eecs.umich.edu TheISA::DTB *dtb; 1162SN/A#endif 1172SN/A 1182683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1191858SN/A#if FULL_SYSTEM 1202683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1213453Sgblack@eecs.umich.edu TheISA::ITB *_itb, TheISA::DTB *_dtb, 1222683Sktlim@umich.edu bool use_kernel_stats = true); 1232SN/A#else 1243402Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); 1252SN/A#endif 1262862Sktlim@umich.edu 1272864Sktlim@umich.edu SimpleThread(); 1282862Sktlim@umich.edu 1292683Sktlim@umich.edu virtual ~SimpleThread(); 1302SN/A 1312680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 132180SN/A 1332SN/A void regStats(const std::string &name); 1342SN/A 1352864Sktlim@umich.edu void copyTC(ThreadContext *context); 1362864Sktlim@umich.edu 1372862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1382862Sktlim@umich.edu 139217SN/A void serialize(std::ostream &os); 140237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 141217SN/A 1422683Sktlim@umich.edu /*************************************************************** 1432683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1442683Sktlim@umich.edu * state, and to provide address translation methods. 1452683Sktlim@umich.edu **************************************************************/ 1462190SN/A 1472683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1482683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1492683Sktlim@umich.edu * CPU. 1502683Sktlim@umich.edu */ 1512680SN/A ThreadContext *getTC() { return tc; } 1522190SN/A 1531858SN/A#if FULL_SYSTEM 1541147SN/A int getInstAsid() { return regs.instAsid(); } 1551147SN/A int getDataAsid() { return regs.dataAsid(); } 1562SN/A 1572532SN/A Fault translateInstReq(RequestPtr &req) 1582SN/A { 1592680SN/A return itb->translate(req, tc); 1602SN/A } 1612SN/A 1622532SN/A Fault translateDataReadReq(RequestPtr &req) 1632SN/A { 1642680SN/A return dtb->translate(req, tc, false); 1652SN/A } 1662SN/A 1672532SN/A Fault translateDataWriteReq(RequestPtr &req) 1682SN/A { 1692680SN/A return dtb->translate(req, tc, true); 1702SN/A } 1712SN/A 1722683Sktlim@umich.edu void dumpFuncProfile(); 1732521SN/A 1742683Sktlim@umich.edu Fault hwrei(); 1752521SN/A 1762683Sktlim@umich.edu bool simPalCheck(int palFunc); 1772SN/A#else 1783402Sktlim@umich.edu 1792532SN/A Fault translateInstReq(RequestPtr &req) 1802SN/A { 1812378SN/A return process->pTable->translate(req); 1821917SN/A } 1832SN/A 1842532SN/A Fault translateDataReadReq(RequestPtr &req) 1851917SN/A { 1862378SN/A return process->pTable->translate(req); 1872SN/A } 1882378SN/A 1892532SN/A Fault translateDataWriteReq(RequestPtr &req) 1902SN/A { 1912378SN/A return process->pTable->translate(req); 1922SN/A } 1932683Sktlim@umich.edu#endif 1942SN/A 1952683Sktlim@umich.edu /******************************************* 1962683Sktlim@umich.edu * ThreadContext interface functions. 1972683Sktlim@umich.edu ******************************************/ 1982683Sktlim@umich.edu 1992683Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 2002683Sktlim@umich.edu 2012683Sktlim@umich.edu int getThreadNum() { return tid; } 2022683Sktlim@umich.edu 2032683Sktlim@umich.edu#if FULL_SYSTEM 2042683Sktlim@umich.edu System *getSystemPtr() { return system; } 2052683Sktlim@umich.edu 2063453Sgblack@eecs.umich.edu TheISA::ITB *getITBPtr() { return itb; } 2072683Sktlim@umich.edu 2083453Sgblack@eecs.umich.edu TheISA::DTB *getDTBPtr() { return dtb; } 2092683Sktlim@umich.edu 2102683Sktlim@umich.edu FunctionalPort *getPhysPort() { return physPort; } 2112683Sktlim@umich.edu 2122683Sktlim@umich.edu /** Return a virtual port. If no thread context is specified then a static 2132683Sktlim@umich.edu * port is returned. Otherwise a port is created and returned. It must be 2142683Sktlim@umich.edu * deleted by deleteVirtPort(). */ 2152683Sktlim@umich.edu VirtualPort *getVirtPort(ThreadContext *tc); 2162683Sktlim@umich.edu 2172683Sktlim@umich.edu void delVirtPort(VirtualPort *vp); 2182SN/A#endif 2192SN/A 2202683Sktlim@umich.edu Status status() const { return _status; } 2212683Sktlim@umich.edu 2222683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2232683Sktlim@umich.edu 2242683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2252683Sktlim@umich.edu /// cycles to wait before beginning execution. 2262683Sktlim@umich.edu void activate(int delay = 1); 2272683Sktlim@umich.edu 2282683Sktlim@umich.edu /// Set the status to Suspended. 2292683Sktlim@umich.edu void suspend(); 2302683Sktlim@umich.edu 2312683Sktlim@umich.edu /// Set the status to Unallocated. 2322683Sktlim@umich.edu void deallocate(); 2332683Sktlim@umich.edu 2342683Sktlim@umich.edu /// Set the status to Halted. 2352683Sktlim@umich.edu void halt(); 2362683Sktlim@umich.edu 2372SN/A virtual bool misspeculating(); 2382SN/A 2392532SN/A Fault instRead(RequestPtr &req) 240716SN/A { 2412378SN/A panic("instRead not implemented"); 2422378SN/A // return funcPhysMem->read(req, inst); 2432423SN/A return NoFault; 244716SN/A } 245716SN/A 2462683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2472190SN/A 2482683Sktlim@umich.edu void clearArchRegs() { regs.clear(); } 2492190SN/A 2502SN/A // 2512SN/A // New accessors for new decoder. 2522SN/A // 2532SN/A uint64_t readIntReg(int reg_idx) 2542SN/A { 2553776Sgblack@eecs.umich.edu return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx)); 2562SN/A } 2572SN/A 2582455SN/A FloatReg readFloatReg(int reg_idx, int width) 2592SN/A { 2602525SN/A return regs.readFloatReg(reg_idx, width); 2612SN/A } 2622SN/A 2632455SN/A FloatReg readFloatReg(int reg_idx) 2642SN/A { 2652525SN/A return regs.readFloatReg(reg_idx); 2662SN/A } 2672SN/A 2682455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width) 2692SN/A { 2702525SN/A return regs.readFloatRegBits(reg_idx, width); 2712455SN/A } 2722455SN/A 2732455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2742455SN/A { 2752525SN/A return regs.readFloatRegBits(reg_idx); 2762SN/A } 2772SN/A 2782SN/A void setIntReg(int reg_idx, uint64_t val) 2792SN/A { 2803776Sgblack@eecs.umich.edu regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val); 2812SN/A } 2822SN/A 2832455SN/A void setFloatReg(int reg_idx, FloatReg val, int width) 2842SN/A { 2852525SN/A regs.setFloatReg(reg_idx, val, width); 2862SN/A } 2872SN/A 2882455SN/A void setFloatReg(int reg_idx, FloatReg val) 2892SN/A { 2902525SN/A regs.setFloatReg(reg_idx, val); 2912SN/A } 2922SN/A 2932455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 2942SN/A { 2952525SN/A regs.setFloatRegBits(reg_idx, val, width); 2962455SN/A } 2972455SN/A 2982455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2992455SN/A { 3002525SN/A regs.setFloatRegBits(reg_idx, val); 3012SN/A } 3022SN/A 3032SN/A uint64_t readPC() 3042SN/A { 3052525SN/A return regs.readPC(); 3062SN/A } 3072SN/A 3082190SN/A void setPC(uint64_t val) 3092190SN/A { 3102525SN/A regs.setPC(val); 3112190SN/A } 3122190SN/A 3133276Sgblack@eecs.umich.edu uint64_t readMicroPC() 3143276Sgblack@eecs.umich.edu { 3153276Sgblack@eecs.umich.edu return microPC; 3163276Sgblack@eecs.umich.edu } 3173276Sgblack@eecs.umich.edu 3183276Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) 3193276Sgblack@eecs.umich.edu { 3203276Sgblack@eecs.umich.edu microPC = val; 3213276Sgblack@eecs.umich.edu } 3223276Sgblack@eecs.umich.edu 3232190SN/A uint64_t readNextPC() 3242190SN/A { 3252525SN/A return regs.readNextPC(); 3262190SN/A } 3272190SN/A 3282SN/A void setNextPC(uint64_t val) 3292SN/A { 3302525SN/A regs.setNextPC(val); 3312SN/A } 3322SN/A 3333276Sgblack@eecs.umich.edu uint64_t readNextMicroPC() 3343276Sgblack@eecs.umich.edu { 3353276Sgblack@eecs.umich.edu return nextMicroPC; 3363276Sgblack@eecs.umich.edu } 3373276Sgblack@eecs.umich.edu 3383276Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) 3393276Sgblack@eecs.umich.edu { 3403276Sgblack@eecs.umich.edu nextMicroPC = val; 3413276Sgblack@eecs.umich.edu } 3423276Sgblack@eecs.umich.edu 3432252SN/A uint64_t readNextNPC() 3442252SN/A { 3452525SN/A return regs.readNextNPC(); 3462252SN/A } 3472252SN/A 3482251SN/A void setNextNPC(uint64_t val) 3492251SN/A { 3502525SN/A regs.setNextNPC(val); 3512251SN/A } 3522251SN/A 3534172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 3544172Ssaidi@eecs.umich.edu { 3554172Ssaidi@eecs.umich.edu return regs.readMiscRegNoEffect(misc_reg); 3564172Ssaidi@eecs.umich.edu } 3574172Ssaidi@eecs.umich.edu 3582159SN/A MiscReg readMiscReg(int misc_reg) 3592SN/A { 3604172Ssaidi@eecs.umich.edu return regs.readMiscReg(misc_reg, tc); 3612SN/A } 3622SN/A 3634172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3642SN/A { 3654172Ssaidi@eecs.umich.edu return regs.setMiscRegNoEffect(misc_reg, val); 3662SN/A } 3672SN/A 3683468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3692SN/A { 3704172Ssaidi@eecs.umich.edu return regs.setMiscReg(misc_reg, val, tc); 3712SN/A } 3722SN/A 3732190SN/A unsigned readStCondFailures() { return storeCondFailures; } 3742190SN/A 3752190SN/A void setStCondFailures(unsigned sc_failures) 3762190SN/A { storeCondFailures = sc_failures; } 3772190SN/A 3781858SN/A#if !FULL_SYSTEM 3792107SN/A TheISA::IntReg getSyscallArg(int i) 380360SN/A { 3813776Sgblack@eecs.umich.edu return regs.readIntReg(TheISA::flattenIntIndex(getTC(), 3823776Sgblack@eecs.umich.edu TheISA::ArgumentReg0 + i)); 383360SN/A } 384360SN/A 385360SN/A // used to shift args for indirect syscall 3862107SN/A void setSyscallArg(int i, TheISA::IntReg val) 387360SN/A { 3883776Sgblack@eecs.umich.edu regs.setIntReg(TheISA::flattenIntIndex(getTC(), 3893776Sgblack@eecs.umich.edu TheISA::ArgumentReg0 + i), val); 390360SN/A } 391360SN/A 3921450SN/A void setSyscallReturn(SyscallReturn return_value) 393360SN/A { 3943776Sgblack@eecs.umich.edu TheISA::setSyscallReturn(return_value, getTC()); 395360SN/A } 396360SN/A 3972561SN/A void syscall(int64_t callnum) 3982SN/A { 3992680SN/A process->syscall(callnum, tc); 4002SN/A } 4012SN/A#endif 4022525SN/A 4032972Sgblack@eecs.umich.edu void changeRegFileContext(TheISA::RegContextParam param, 4042972Sgblack@eecs.umich.edu TheISA::RegContextVal val) 4052525SN/A { 4062525SN/A regs.changeContext(param, val); 4072525SN/A } 4082SN/A}; 4092SN/A 4102SN/A 4112SN/A// for non-speculative execution context, spec_mode is always false 4122SN/Ainline bool 4132683Sktlim@umich.eduSimpleThread::misspeculating() 4142SN/A{ 4152SN/A return false; 4162SN/A} 4172SN/A 4182190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 419