simple_thread.hh revision 13693
12SN/A/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2011-2012, 2016-2018 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 412665SN/A * Authors: Steve Reinhardt 422665SN/A * Nathan Binkert 432SN/A */ 442SN/A 452683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 462683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 472SN/A 489020Sgblack@eecs.umich.edu#include "arch/decoder.hh" 4912406Sgabeblack@google.com#include "arch/generic/tlb.hh" 506313Sgblack@eecs.umich.edu#include "arch/isa.hh" 512190SN/A#include "arch/isa_traits.hh" 526329Sgblack@eecs.umich.edu#include "arch/registers.hh" 536316Sgblack@eecs.umich.edu#include "arch/types.hh" 546216Snate@binkert.org#include "base/types.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 562680SN/A#include "cpu/thread_context.hh" 572683Sktlim@umich.edu#include "cpu/thread_state.hh" 589920Syasuko.eckert@amd.com#include "debug/CCRegs.hh" 598232Snate@binkert.org#include "debug/FloatRegs.hh" 608232Snate@binkert.org#include "debug/IntRegs.hh" 6113610Sgiacomo.gabrielli@arm.com#include "debug/VecPredRegs.hh" 6212109SRekai.GonzalezAlberquilla@arm.com#include "debug/VecRegs.hh" 638777Sgblack@eecs.umich.edu#include "mem/page_table.hh" 642395SN/A#include "mem/request.hh" 652190SN/A#include "sim/byteswap.hh" 662188SN/A#include "sim/eventq.hh" 678777Sgblack@eecs.umich.edu#include "sim/process.hh" 68217SN/A#include "sim/serialize.hh" 698777Sgblack@eecs.umich.edu#include "sim/system.hh" 702SN/A 712SN/Aclass BaseCPU; 728887Sgeoffrey.blake@arm.comclass CheckerCPU; 731070SN/A 741917SN/Aclass FunctionProfile; 751917SN/Aclass ProfileNode; 762521SN/A 773548Sgblack@eecs.umich.edunamespace TheISA { 783548Sgblack@eecs.umich.edu namespace Kernel { 793548Sgblack@eecs.umich.edu class Statistics; 808902Sandreas.hansson@arm.com } 818902Sandreas.hansson@arm.com} 822330SN/A 832683Sktlim@umich.edu/** 842683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 852683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 862683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 872683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 882683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 892683Sktlim@umich.edu * the objects needed for simple functional execution, including a 902683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 912683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 922683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 932683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 942683Sktlim@umich.edu * all the necessary state for full architecture-level functional 952683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 962683Sktlim@umich.edu * examples. 972683Sktlim@umich.edu */ 982SN/A 992683Sktlim@umich.educlass SimpleThread : public ThreadState 1002SN/A{ 1012107SN/A protected: 1022107SN/A typedef TheISA::MachInst MachInst; 10312109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 10412109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 10513610Sgiacomo.gabrielli@arm.com using VecPredRegContainer = TheISA::VecPredRegContainer; 1062SN/A public: 1072680SN/A typedef ThreadContext::Status Status; 1082SN/A 1092190SN/A protected: 11013557Sgabeblack@google.com RegVal floatRegs[TheISA::NumFloatRegs]; 11113557Sgabeblack@google.com RegVal intRegs[TheISA::NumIntRegs]; 11212109SRekai.GonzalezAlberquilla@arm.com VecRegContainer vecRegs[TheISA::NumVecRegs]; 11313610Sgiacomo.gabrielli@arm.com VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs]; 1149920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 11513622Sgabeblack@google.com RegVal ccRegs[TheISA::NumCCRegs]; 1169920Syasuko.eckert@amd.com#endif 1179384SAndreas.Sandberg@arm.com TheISA::ISA *const isa; // one "instance" of the current ISA. 1182SN/A 1197720Sgblack@eecs.umich.edu TheISA::PCState _pcState; 1206324Sgblack@eecs.umich.edu 1217597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1227597Sminkyu.jeong@arm.com bool predicate; 1237597Sminkyu.jeong@arm.com 1242190SN/A public: 1258357Sksewell@umich.edu std::string name() const 1268357Sksewell@umich.edu { 1278735Sandreas.hanson@arm.com return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 1288357Sksewell@umich.edu } 1298357Sksewell@umich.edu 1302683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1312188SN/A 1322378SN/A System *system; 1332400SN/A 13412406Sgabeblack@google.com BaseTLB *itb; 13512406Sgabeblack@google.com BaseTLB *dtb; 1362SN/A 1379020Sgblack@eecs.umich.edu TheISA::Decoder decoder; 1388541Sgblack@eecs.umich.edu 1392683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1408793Sgblack@eecs.umich.edu // FS 1412683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 14212406Sgabeblack@google.com BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa, 1432683Sktlim@umich.edu bool use_kernel_stats = true); 1448793Sgblack@eecs.umich.edu // SE 1458820Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 14612406Sgabeblack@google.com Process *_process, BaseTLB *_itb, BaseTLB *_dtb, 1479384SAndreas.Sandberg@arm.com TheISA::ISA *_isa); 1482862Sktlim@umich.edu 1492683Sktlim@umich.edu virtual ~SimpleThread(); 1502SN/A 1512680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 152180SN/A 1532SN/A void regStats(const std::string &name); 1542SN/A 1552862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1562862Sktlim@umich.edu 15711168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 15811168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1599461Snilay@cs.wisc.edu void startup(); 160217SN/A 1612683Sktlim@umich.edu /*************************************************************** 1622683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1635891Sgblack@eecs.umich.edu * state. 1642683Sktlim@umich.edu **************************************************************/ 1652190SN/A 1662683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1672683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1682683Sktlim@umich.edu * CPU. 1692683Sktlim@umich.edu */ 1702680SN/A ThreadContext *getTC() { return tc; } 1712190SN/A 1725358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1735358Sgblack@eecs.umich.edu { 1745358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1755358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1765358Sgblack@eecs.umich.edu } 1775358Sgblack@eecs.umich.edu 1785358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1795358Sgblack@eecs.umich.edu { 1805358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1815358Sgblack@eecs.umich.edu } 1825358Sgblack@eecs.umich.edu 1835358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1845358Sgblack@eecs.umich.edu { 1855358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1865358Sgblack@eecs.umich.edu } 1875358Sgblack@eecs.umich.edu 1882683Sktlim@umich.edu void dumpFuncProfile(); 1892521SN/A 1905702Ssaidi@eecs.umich.edu Fault hwrei(); 1915702Ssaidi@eecs.umich.edu 1925702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1935702Ssaidi@eecs.umich.edu 1942683Sktlim@umich.edu /******************************************* 1952683Sktlim@umich.edu * ThreadContext interface functions. 1962683Sktlim@umich.edu ******************************************/ 1972683Sktlim@umich.edu 1988735Sandreas.hanson@arm.com BaseCPU *getCpuPtr() { return baseCpu; } 1992683Sktlim@umich.edu 20012406Sgabeblack@google.com BaseTLB *getITBPtr() { return itb; } 2012683Sktlim@umich.edu 20212406Sgabeblack@google.com BaseTLB *getDTBPtr() { return dtb; } 2032683Sktlim@umich.edu 2048887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return NULL; } 2058733Sgeoffrey.blake@arm.com 20613693Sgiacomo.gabrielli@arm.com TheISA::ISA *getIsaPtr() { return isa; } 20713693Sgiacomo.gabrielli@arm.com 2089020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return &decoder; } 2098541Sgblack@eecs.umich.edu 2104997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2114997Sgblack@eecs.umich.edu 2122683Sktlim@umich.edu Status status() const { return _status; } 2132683Sktlim@umich.edu 2142683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2152683Sktlim@umich.edu 21610407Smitch.hayenga@arm.com /// Set the status to Active. 21710407Smitch.hayenga@arm.com void activate(); 2182683Sktlim@umich.edu 2192683Sktlim@umich.edu /// Set the status to Suspended. 2202683Sktlim@umich.edu void suspend(); 2212683Sktlim@umich.edu 2222683Sktlim@umich.edu /// Set the status to Halted. 2232683Sktlim@umich.edu void halt(); 2242683Sktlim@umich.edu 2252683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2262190SN/A 2276315Sgblack@eecs.umich.edu void clearArchRegs() 2286315Sgblack@eecs.umich.edu { 2297720Sgblack@eecs.umich.edu _pcState = 0; 2306316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 23113501Sgabeblack@google.com memset(floatRegs, 0, sizeof(floatRegs)); 23212109SRekai.GonzalezAlberquilla@arm.com for (int i = 0; i < TheISA::NumVecRegs; i++) { 23312109SRekai.GonzalezAlberquilla@arm.com vecRegs[i].zero(); 23412109SRekai.GonzalezAlberquilla@arm.com } 23513610Sgiacomo.gabrielli@arm.com for (int i = 0; i < TheISA::NumVecPredRegs; i++) { 23613610Sgiacomo.gabrielli@arm.com vecPredRegs[i].reset(); 23713610Sgiacomo.gabrielli@arm.com } 2389920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 2399920Syasuko.eckert@amd.com memset(ccRegs, 0, sizeof(ccRegs)); 2409920Syasuko.eckert@amd.com#endif 2419384SAndreas.Sandberg@arm.com isa->clear(); 2426315Sgblack@eecs.umich.edu } 2432190SN/A 2442SN/A // 2452SN/A // New accessors for new decoder. 2462SN/A // 24713557Sgabeblack@google.com RegVal 24813557Sgabeblack@google.com readIntReg(int reg_idx) 2492SN/A { 2509384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 2516323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2529426SAndreas.Sandberg@ARM.com uint64_t regVal(readIntRegFlat(flatIndex)); 2537601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2547601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 2556418Sgblack@eecs.umich.edu return regVal; 2562SN/A } 2572SN/A 25813557Sgabeblack@google.com RegVal 25913611Sgabeblack@google.com readFloatReg(int reg_idx) 2602455SN/A { 2619384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 2626323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 26313611Sgabeblack@google.com RegVal regVal(readFloatRegFlat(flatIndex)); 26413501Sgabeblack@google.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", 26513501Sgabeblack@google.com reg_idx, flatIndex, regVal); 2667341Sgblack@eecs.umich.edu return regVal; 2672SN/A } 2682SN/A 26912109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& 27012109SRekai.GonzalezAlberquilla@arm.com readVecReg(const RegId& reg) const 27112109SRekai.GonzalezAlberquilla@arm.com { 27212109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 27312109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 27412109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& regVal = readVecRegFlat(flatIndex); 27512109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n", 27613610Sgiacomo.gabrielli@arm.com reg.index(), flatIndex, regVal.print()); 27712109SRekai.GonzalezAlberquilla@arm.com return regVal; 27812109SRekai.GonzalezAlberquilla@arm.com } 27912109SRekai.GonzalezAlberquilla@arm.com 28012109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& 28112109SRekai.GonzalezAlberquilla@arm.com getWritableVecReg(const RegId& reg) 28212109SRekai.GonzalezAlberquilla@arm.com { 28312109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 28412109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 28512109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& regVal = getWritableVecRegFlat(flatIndex); 28612109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n", 28713610Sgiacomo.gabrielli@arm.com reg.index(), flatIndex, regVal.print()); 28812109SRekai.GonzalezAlberquilla@arm.com return regVal; 28912109SRekai.GonzalezAlberquilla@arm.com } 29012109SRekai.GonzalezAlberquilla@arm.com 29112109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 29212109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 29312109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector <T> operand. */ 29412109SRekai.GonzalezAlberquilla@arm.com template <typename T> 29512109SRekai.GonzalezAlberquilla@arm.com VecLaneT<T, true> 29612109SRekai.GonzalezAlberquilla@arm.com readVecLane(const RegId& reg) const 29712109SRekai.GonzalezAlberquilla@arm.com { 29812109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 29912109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 30012109SRekai.GonzalezAlberquilla@arm.com auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex()); 30112109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n", 30212109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, reg.elemIndex(), regVal); 30312109SRekai.GonzalezAlberquilla@arm.com return regVal; 30412109SRekai.GonzalezAlberquilla@arm.com } 30512109SRekai.GonzalezAlberquilla@arm.com 30612109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 30712109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 30812109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneReg(const RegId& reg) const 30912109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint8_t>(reg); } 31012109SRekai.GonzalezAlberquilla@arm.com 31112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 31212109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 31312109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneReg(const RegId& reg) const 31412109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint16_t>(reg); } 31512109SRekai.GonzalezAlberquilla@arm.com 31612109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 31712109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 31812109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneReg(const RegId& reg) const 31912109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint32_t>(reg); } 32012109SRekai.GonzalezAlberquilla@arm.com 32112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 32212109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 32312109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneReg(const RegId& reg) const 32412109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint64_t>(reg); } 32512109SRekai.GonzalezAlberquilla@arm.com 32612109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 32712109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 32812109SRekai.GonzalezAlberquilla@arm.com void setVecLaneT(const RegId& reg, const LD& val) 32912109SRekai.GonzalezAlberquilla@arm.com { 33012109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 33112109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 33212109SRekai.GonzalezAlberquilla@arm.com setVecLaneFlat(flatIndex, reg.elemIndex(), val); 33312109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n", 33412109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, reg.elemIndex(), val); 33512109SRekai.GonzalezAlberquilla@arm.com } 33612109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 33712109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) 33812109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 33912109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 34012109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) 34112109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 34212109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 34312109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) 34412109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 34512109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 34612109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) 34712109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 34812109SRekai.GonzalezAlberquilla@arm.com /** @} */ 34912109SRekai.GonzalezAlberquilla@arm.com 35012109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElem(const RegId& reg) const 35112109SRekai.GonzalezAlberquilla@arm.com { 35212109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecElemIndex(reg.index()); 35312109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 35412109SRekai.GonzalezAlberquilla@arm.com const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex()); 35512109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as" 35612109SRekai.GonzalezAlberquilla@arm.com " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal); 35712109SRekai.GonzalezAlberquilla@arm.com return regVal; 35812109SRekai.GonzalezAlberquilla@arm.com } 35912109SRekai.GonzalezAlberquilla@arm.com 36013610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& 36113610Sgiacomo.gabrielli@arm.com readVecPredReg(const RegId& reg) const 36213610Sgiacomo.gabrielli@arm.com { 36313610Sgiacomo.gabrielli@arm.com int flatIndex = isa->flattenVecPredIndex(reg.index()); 36413610Sgiacomo.gabrielli@arm.com assert(flatIndex < TheISA::NumVecPredRegs); 36513610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& regVal = readVecPredRegFlat(flatIndex); 36613610Sgiacomo.gabrielli@arm.com DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n", 36713610Sgiacomo.gabrielli@arm.com reg.index(), flatIndex, regVal.print()); 36813610Sgiacomo.gabrielli@arm.com return regVal; 36913610Sgiacomo.gabrielli@arm.com } 37013610Sgiacomo.gabrielli@arm.com 37113610Sgiacomo.gabrielli@arm.com VecPredRegContainer& 37213610Sgiacomo.gabrielli@arm.com getWritableVecPredReg(const RegId& reg) 37313610Sgiacomo.gabrielli@arm.com { 37413610Sgiacomo.gabrielli@arm.com int flatIndex = isa->flattenVecPredIndex(reg.index()); 37513610Sgiacomo.gabrielli@arm.com assert(flatIndex < TheISA::NumVecPredRegs); 37613610Sgiacomo.gabrielli@arm.com VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex); 37713610Sgiacomo.gabrielli@arm.com DPRINTF(VecPredRegs, 37813610Sgiacomo.gabrielli@arm.com "Reading predicate reg %d (%d) as %s for modify.\n", 37913610Sgiacomo.gabrielli@arm.com reg.index(), flatIndex, regVal.print()); 38013610Sgiacomo.gabrielli@arm.com return regVal; 38113610Sgiacomo.gabrielli@arm.com } 38212109SRekai.GonzalezAlberquilla@arm.com 38313622Sgabeblack@google.com RegVal 38413622Sgabeblack@google.com readCCReg(int reg_idx) 3859920Syasuko.eckert@amd.com { 3869920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 3879920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 38810338SCurtis.Dunham@arm.com assert(0 <= flatIndex); 3899920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 3909920Syasuko.eckert@amd.com uint64_t regVal(readCCRegFlat(flatIndex)); 3919920Syasuko.eckert@amd.com DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 3929920Syasuko.eckert@amd.com reg_idx, flatIndex, regVal); 3939920Syasuko.eckert@amd.com return regVal; 3949920Syasuko.eckert@amd.com#else 3959920Syasuko.eckert@amd.com panic("Tried to read a CC register."); 3969920Syasuko.eckert@amd.com return 0; 3979920Syasuko.eckert@amd.com#endif 3989920Syasuko.eckert@amd.com } 3999920Syasuko.eckert@amd.com 40013557Sgabeblack@google.com void 40113557Sgabeblack@google.com setIntReg(int reg_idx, RegVal val) 4022SN/A { 4039384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 4046323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 4057601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 4067601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 4079426SAndreas.Sandberg@ARM.com setIntRegFlat(flatIndex, val); 4082SN/A } 4092SN/A 41013557Sgabeblack@google.com void 41113611Sgabeblack@google.com setFloatReg(int reg_idx, RegVal val) 4122455SN/A { 4139384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 4146323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 4158733Sgeoffrey.blake@arm.com // XXX: Fix array out of bounds compiler error for gem5.fast 4168733Sgeoffrey.blake@arm.com // when checkercpu enabled 4178733Sgeoffrey.blake@arm.com if (flatIndex < TheISA::NumFloatRegs) 41813611Sgabeblack@google.com setFloatRegFlat(flatIndex, val); 41913501Sgabeblack@google.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", 42013501Sgabeblack@google.com reg_idx, flatIndex, val); 4212SN/A } 4222SN/A 42313557Sgabeblack@google.com void 42413557Sgabeblack@google.com setVecReg(const RegId& reg, const VecRegContainer& val) 42512109SRekai.GonzalezAlberquilla@arm.com { 42612109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 42712109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 42812109SRekai.GonzalezAlberquilla@arm.com setVecRegFlat(flatIndex, val); 42912109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n", 43012109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, val.print()); 43112109SRekai.GonzalezAlberquilla@arm.com } 43212109SRekai.GonzalezAlberquilla@arm.com 43313557Sgabeblack@google.com void 43413557Sgabeblack@google.com setVecElem(const RegId& reg, const VecElem& val) 43512109SRekai.GonzalezAlberquilla@arm.com { 43612109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecElemIndex(reg.index()); 43712109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 43812109SRekai.GonzalezAlberquilla@arm.com setVecElemFlat(flatIndex, reg.elemIndex(), val); 43912109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 44012109SRekai.GonzalezAlberquilla@arm.com " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 44112109SRekai.GonzalezAlberquilla@arm.com } 44212109SRekai.GonzalezAlberquilla@arm.com 44313557Sgabeblack@google.com void 44413610Sgiacomo.gabrielli@arm.com setVecPredReg(const RegId& reg, const VecPredRegContainer& val) 44513610Sgiacomo.gabrielli@arm.com { 44613610Sgiacomo.gabrielli@arm.com int flatIndex = isa->flattenVecPredIndex(reg.index()); 44713610Sgiacomo.gabrielli@arm.com assert(flatIndex < TheISA::NumVecPredRegs); 44813610Sgiacomo.gabrielli@arm.com setVecPredRegFlat(flatIndex, val); 44913610Sgiacomo.gabrielli@arm.com DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n", 45013610Sgiacomo.gabrielli@arm.com reg.index(), flatIndex, val.print()); 45113610Sgiacomo.gabrielli@arm.com } 45213610Sgiacomo.gabrielli@arm.com 45313610Sgiacomo.gabrielli@arm.com void 45413622Sgabeblack@google.com setCCReg(int reg_idx, RegVal val) 4559920Syasuko.eckert@amd.com { 4569920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 4579920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 4589920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 4599920Syasuko.eckert@amd.com DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 4609920Syasuko.eckert@amd.com reg_idx, flatIndex, val); 4619920Syasuko.eckert@amd.com setCCRegFlat(flatIndex, val); 4629920Syasuko.eckert@amd.com#else 4639920Syasuko.eckert@amd.com panic("Tried to set a CC register."); 4649920Syasuko.eckert@amd.com#endif 4659920Syasuko.eckert@amd.com } 4669920Syasuko.eckert@amd.com 4677720Sgblack@eecs.umich.edu TheISA::PCState 4687720Sgblack@eecs.umich.edu pcState() 4692SN/A { 4707720Sgblack@eecs.umich.edu return _pcState; 4712SN/A } 4722SN/A 4737720Sgblack@eecs.umich.edu void 4747720Sgblack@eecs.umich.edu pcState(const TheISA::PCState &val) 4752190SN/A { 4767720Sgblack@eecs.umich.edu _pcState = val; 4772190SN/A } 4782190SN/A 4798733Sgeoffrey.blake@arm.com void 4808733Sgeoffrey.blake@arm.com pcStateNoRecord(const TheISA::PCState &val) 4818733Sgeoffrey.blake@arm.com { 4828733Sgeoffrey.blake@arm.com _pcState = val; 4838733Sgeoffrey.blake@arm.com } 4848733Sgeoffrey.blake@arm.com 4857720Sgblack@eecs.umich.edu Addr 4867720Sgblack@eecs.umich.edu instAddr() 4873276Sgblack@eecs.umich.edu { 4887720Sgblack@eecs.umich.edu return _pcState.instAddr(); 4893276Sgblack@eecs.umich.edu } 4903276Sgblack@eecs.umich.edu 4917720Sgblack@eecs.umich.edu Addr 4927720Sgblack@eecs.umich.edu nextInstAddr() 4933276Sgblack@eecs.umich.edu { 4947720Sgblack@eecs.umich.edu return _pcState.nextInstAddr(); 4953276Sgblack@eecs.umich.edu } 4963276Sgblack@eecs.umich.edu 49711886Sbrandon.potter@amd.com void 49811886Sbrandon.potter@amd.com setNPC(Addr val) 49911886Sbrandon.potter@amd.com { 50011886Sbrandon.potter@amd.com _pcState.setNPC(val); 50111886Sbrandon.potter@amd.com } 50211886Sbrandon.potter@amd.com 5037720Sgblack@eecs.umich.edu MicroPC 5047720Sgblack@eecs.umich.edu microPC() 5052190SN/A { 5067720Sgblack@eecs.umich.edu return _pcState.microPC(); 5072251SN/A } 5082251SN/A 5097597Sminkyu.jeong@arm.com bool readPredicate() 5107597Sminkyu.jeong@arm.com { 5117597Sminkyu.jeong@arm.com return predicate; 5127597Sminkyu.jeong@arm.com } 5137597Sminkyu.jeong@arm.com 5147597Sminkyu.jeong@arm.com void setPredicate(bool val) 5157597Sminkyu.jeong@arm.com { 5167597Sminkyu.jeong@arm.com predicate = val; 5177597Sminkyu.jeong@arm.com } 5187597Sminkyu.jeong@arm.com 51913557Sgabeblack@google.com RegVal 52013557Sgabeblack@google.com readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const 5214172Ssaidi@eecs.umich.edu { 5229384SAndreas.Sandberg@arm.com return isa->readMiscRegNoEffect(misc_reg); 5234172Ssaidi@eecs.umich.edu } 5244172Ssaidi@eecs.umich.edu 52513557Sgabeblack@google.com RegVal 52613557Sgabeblack@google.com readMiscReg(int misc_reg, ThreadID tid=0) 5272SN/A { 5289384SAndreas.Sandberg@arm.com return isa->readMiscReg(misc_reg, tc); 5292SN/A } 5302SN/A 5316221Snate@binkert.org void 53213582Sgabeblack@google.com setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid = 0) 5332SN/A { 5349384SAndreas.Sandberg@arm.com return isa->setMiscRegNoEffect(misc_reg, val); 5352SN/A } 5362SN/A 5376221Snate@binkert.org void 53813582Sgabeblack@google.com setMiscReg(int misc_reg, RegVal val, ThreadID tid = 0) 5392SN/A { 5409384SAndreas.Sandberg@arm.com return isa->setMiscReg(misc_reg, val, tc); 5416313Sgblack@eecs.umich.edu } 5426313Sgblack@eecs.umich.edu 54312106SRekai.GonzalezAlberquilla@arm.com RegId 54412106SRekai.GonzalezAlberquilla@arm.com flattenRegId(const RegId& regId) const 5456313Sgblack@eecs.umich.edu { 54612106SRekai.GonzalezAlberquilla@arm.com return isa->flattenRegId(regId); 54710033SAli.Saidi@ARM.com } 54810033SAli.Saidi@ARM.com 5492190SN/A unsigned readStCondFailures() { return storeCondFailures; } 5502190SN/A 5512190SN/A void setStCondFailures(unsigned sc_failures) 5522190SN/A { storeCondFailures = sc_failures; } 5532190SN/A 55413557Sgabeblack@google.com void 55513557Sgabeblack@google.com syscall(int64_t callnum, Fault *fault) 5562SN/A { 55711877Sbrandon.potter@amd.com process->syscall(callnum, tc, fault); 5582SN/A } 5599426SAndreas.Sandberg@ARM.com 56013557Sgabeblack@google.com RegVal readIntRegFlat(int idx) { return intRegs[idx]; } 56113557Sgabeblack@google.com void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; } 5629426SAndreas.Sandberg@ARM.com 56313611Sgabeblack@google.com RegVal readFloatRegFlat(int idx) { return floatRegs[idx]; } 56413611Sgabeblack@google.com void setFloatRegFlat(int idx, RegVal val) { floatRegs[idx] = val; } 5659426SAndreas.Sandberg@ARM.com 56613557Sgabeblack@google.com const VecRegContainer & 56713557Sgabeblack@google.com readVecRegFlat(const RegIndex& reg) const 56812109SRekai.GonzalezAlberquilla@arm.com { 56912109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg]; 57012109SRekai.GonzalezAlberquilla@arm.com } 57112109SRekai.GonzalezAlberquilla@arm.com 57213557Sgabeblack@google.com VecRegContainer & 57313557Sgabeblack@google.com getWritableVecRegFlat(const RegIndex& reg) 57412109SRekai.GonzalezAlberquilla@arm.com { 57512109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg]; 57612109SRekai.GonzalezAlberquilla@arm.com } 57712109SRekai.GonzalezAlberquilla@arm.com 57813557Sgabeblack@google.com void 57913557Sgabeblack@google.com setVecRegFlat(const RegIndex& reg, const VecRegContainer& val) 58012109SRekai.GonzalezAlberquilla@arm.com { 58112109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg] = val; 58212109SRekai.GonzalezAlberquilla@arm.com } 58312109SRekai.GonzalezAlberquilla@arm.com 58412109SRekai.GonzalezAlberquilla@arm.com template <typename T> 58513557Sgabeblack@google.com VecLaneT<T, true> 58613557Sgabeblack@google.com readVecLaneFlat(const RegIndex& reg, int lId) const 58712109SRekai.GonzalezAlberquilla@arm.com { 58812109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg].laneView<T>(lId); 58912109SRekai.GonzalezAlberquilla@arm.com } 59012109SRekai.GonzalezAlberquilla@arm.com 59112109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 59213557Sgabeblack@google.com void 59313557Sgabeblack@google.com setVecLaneFlat(const RegIndex& reg, int lId, const LD& val) 59412109SRekai.GonzalezAlberquilla@arm.com { 59512109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; 59612109SRekai.GonzalezAlberquilla@arm.com } 59712109SRekai.GonzalezAlberquilla@arm.com 59813557Sgabeblack@google.com const VecElem & 59913557Sgabeblack@google.com readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const 60012109SRekai.GonzalezAlberquilla@arm.com { 60112109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; 60212109SRekai.GonzalezAlberquilla@arm.com } 60312109SRekai.GonzalezAlberquilla@arm.com 60413557Sgabeblack@google.com void 60513557Sgabeblack@google.com setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex, 60613557Sgabeblack@google.com const VecElem val) 60712109SRekai.GonzalezAlberquilla@arm.com { 60812109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 60912109SRekai.GonzalezAlberquilla@arm.com } 61012109SRekai.GonzalezAlberquilla@arm.com 61113610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& readVecPredRegFlat(const RegIndex& reg) const 61213610Sgiacomo.gabrielli@arm.com { 61313610Sgiacomo.gabrielli@arm.com return vecPredRegs[reg]; 61413610Sgiacomo.gabrielli@arm.com } 61513610Sgiacomo.gabrielli@arm.com 61613610Sgiacomo.gabrielli@arm.com VecPredRegContainer& getWritableVecPredRegFlat(const RegIndex& reg) 61713610Sgiacomo.gabrielli@arm.com { 61813610Sgiacomo.gabrielli@arm.com return vecPredRegs[reg]; 61913610Sgiacomo.gabrielli@arm.com } 62013610Sgiacomo.gabrielli@arm.com 62113610Sgiacomo.gabrielli@arm.com void setVecPredRegFlat(const RegIndex& reg, const VecPredRegContainer& val) 62213610Sgiacomo.gabrielli@arm.com { 62313610Sgiacomo.gabrielli@arm.com vecPredRegs[reg] = val; 62413610Sgiacomo.gabrielli@arm.com } 62513610Sgiacomo.gabrielli@arm.com 6269920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 62713622Sgabeblack@google.com RegVal readCCRegFlat(int idx) { return ccRegs[idx]; } 62813622Sgabeblack@google.com void setCCRegFlat(int idx, RegVal val) { ccRegs[idx] = val; } 6299920Syasuko.eckert@amd.com#else 63013622Sgabeblack@google.com RegVal readCCRegFlat(int idx) 6319920Syasuko.eckert@amd.com { panic("readCCRegFlat w/no CC regs!\n"); } 6329920Syasuko.eckert@amd.com 63313622Sgabeblack@google.com void setCCRegFlat(int idx, RegVal val) 6349920Syasuko.eckert@amd.com { panic("setCCRegFlat w/no CC regs!\n"); } 6359920Syasuko.eckert@amd.com#endif 6362SN/A}; 6372SN/A 6382SN/A 6392190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 640