simple_thread.hh revision 13582
12SN/A/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2011-2012, 2016 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 412665SN/A * Authors: Steve Reinhardt 422665SN/A * Nathan Binkert 432SN/A */ 442SN/A 452683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 462683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 472SN/A 489020Sgblack@eecs.umich.edu#include "arch/decoder.hh" 4912406Sgabeblack@google.com#include "arch/generic/tlb.hh" 506313Sgblack@eecs.umich.edu#include "arch/isa.hh" 512190SN/A#include "arch/isa_traits.hh" 526329Sgblack@eecs.umich.edu#include "arch/registers.hh" 536316Sgblack@eecs.umich.edu#include "arch/types.hh" 546216Snate@binkert.org#include "base/types.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 562680SN/A#include "cpu/thread_context.hh" 572683Sktlim@umich.edu#include "cpu/thread_state.hh" 589920Syasuko.eckert@amd.com#include "debug/CCRegs.hh" 598232Snate@binkert.org#include "debug/FloatRegs.hh" 608232Snate@binkert.org#include "debug/IntRegs.hh" 6112109SRekai.GonzalezAlberquilla@arm.com#include "debug/VecRegs.hh" 628777Sgblack@eecs.umich.edu#include "mem/page_table.hh" 632395SN/A#include "mem/request.hh" 642190SN/A#include "sim/byteswap.hh" 652188SN/A#include "sim/eventq.hh" 668777Sgblack@eecs.umich.edu#include "sim/process.hh" 67217SN/A#include "sim/serialize.hh" 688777Sgblack@eecs.umich.edu#include "sim/system.hh" 692SN/A 702SN/Aclass BaseCPU; 718887Sgeoffrey.blake@arm.comclass CheckerCPU; 721070SN/A 731917SN/Aclass FunctionProfile; 741917SN/Aclass ProfileNode; 752521SN/A 763548Sgblack@eecs.umich.edunamespace TheISA { 773548Sgblack@eecs.umich.edu namespace Kernel { 783548Sgblack@eecs.umich.edu class Statistics; 798902Sandreas.hansson@arm.com } 808902Sandreas.hansson@arm.com} 812330SN/A 822683Sktlim@umich.edu/** 832683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 842683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 852683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 862683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 872683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 882683Sktlim@umich.edu * the objects needed for simple functional execution, including a 892683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 902683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 912683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 922683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 932683Sktlim@umich.edu * all the necessary state for full architecture-level functional 942683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 952683Sktlim@umich.edu * examples. 962683Sktlim@umich.edu */ 972SN/A 982683Sktlim@umich.educlass SimpleThread : public ThreadState 992SN/A{ 1002107SN/A protected: 1012107SN/A typedef TheISA::MachInst MachInst; 1029920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 10312109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 10412109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 1052SN/A public: 1062680SN/A typedef ThreadContext::Status Status; 1072SN/A 1082190SN/A protected: 10913557Sgabeblack@google.com RegVal floatRegs[TheISA::NumFloatRegs]; 11013557Sgabeblack@google.com RegVal intRegs[TheISA::NumIntRegs]; 11112109SRekai.GonzalezAlberquilla@arm.com VecRegContainer vecRegs[TheISA::NumVecRegs]; 1129920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 1139920Syasuko.eckert@amd.com TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 1149920Syasuko.eckert@amd.com#endif 1159384SAndreas.Sandberg@arm.com TheISA::ISA *const isa; // one "instance" of the current ISA. 1162SN/A 1177720Sgblack@eecs.umich.edu TheISA::PCState _pcState; 1186324Sgblack@eecs.umich.edu 1197597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1207597Sminkyu.jeong@arm.com bool predicate; 1217597Sminkyu.jeong@arm.com 1222190SN/A public: 1238357Sksewell@umich.edu std::string name() const 1248357Sksewell@umich.edu { 1258735Sandreas.hanson@arm.com return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 1268357Sksewell@umich.edu } 1278357Sksewell@umich.edu 1282683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1292188SN/A 1302378SN/A System *system; 1312400SN/A 13212406Sgabeblack@google.com BaseTLB *itb; 13312406Sgabeblack@google.com BaseTLB *dtb; 1342SN/A 1359020Sgblack@eecs.umich.edu TheISA::Decoder decoder; 1368541Sgblack@eecs.umich.edu 1372683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1388793Sgblack@eecs.umich.edu // FS 1392683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 14012406Sgabeblack@google.com BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa, 1412683Sktlim@umich.edu bool use_kernel_stats = true); 1428793Sgblack@eecs.umich.edu // SE 1438820Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 14412406Sgabeblack@google.com Process *_process, BaseTLB *_itb, BaseTLB *_dtb, 1459384SAndreas.Sandberg@arm.com TheISA::ISA *_isa); 1462862Sktlim@umich.edu 1472683Sktlim@umich.edu virtual ~SimpleThread(); 1482SN/A 1492680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 150180SN/A 1512SN/A void regStats(const std::string &name); 1522SN/A 1532862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1542862Sktlim@umich.edu 15511168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 15611168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1579461Snilay@cs.wisc.edu void startup(); 158217SN/A 1592683Sktlim@umich.edu /*************************************************************** 1602683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1615891Sgblack@eecs.umich.edu * state. 1622683Sktlim@umich.edu **************************************************************/ 1632190SN/A 1642683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1652683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1662683Sktlim@umich.edu * CPU. 1672683Sktlim@umich.edu */ 1682680SN/A ThreadContext *getTC() { return tc; } 1692190SN/A 1705358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1715358Sgblack@eecs.umich.edu { 1725358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1735358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1745358Sgblack@eecs.umich.edu } 1755358Sgblack@eecs.umich.edu 1765358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1775358Sgblack@eecs.umich.edu { 1785358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1795358Sgblack@eecs.umich.edu } 1805358Sgblack@eecs.umich.edu 1815358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1825358Sgblack@eecs.umich.edu { 1835358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1845358Sgblack@eecs.umich.edu } 1855358Sgblack@eecs.umich.edu 1862683Sktlim@umich.edu void dumpFuncProfile(); 1872521SN/A 1885702Ssaidi@eecs.umich.edu Fault hwrei(); 1895702Ssaidi@eecs.umich.edu 1905702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1915702Ssaidi@eecs.umich.edu 1922683Sktlim@umich.edu /******************************************* 1932683Sktlim@umich.edu * ThreadContext interface functions. 1942683Sktlim@umich.edu ******************************************/ 1952683Sktlim@umich.edu 1968735Sandreas.hanson@arm.com BaseCPU *getCpuPtr() { return baseCpu; } 1972683Sktlim@umich.edu 19812406Sgabeblack@google.com BaseTLB *getITBPtr() { return itb; } 1992683Sktlim@umich.edu 20012406Sgabeblack@google.com BaseTLB *getDTBPtr() { return dtb; } 2012683Sktlim@umich.edu 2028887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return NULL; } 2038733Sgeoffrey.blake@arm.com 2049020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return &decoder; } 2058541Sgblack@eecs.umich.edu 2064997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2074997Sgblack@eecs.umich.edu 2082683Sktlim@umich.edu Status status() const { return _status; } 2092683Sktlim@umich.edu 2102683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2112683Sktlim@umich.edu 21210407Smitch.hayenga@arm.com /// Set the status to Active. 21310407Smitch.hayenga@arm.com void activate(); 2142683Sktlim@umich.edu 2152683Sktlim@umich.edu /// Set the status to Suspended. 2162683Sktlim@umich.edu void suspend(); 2172683Sktlim@umich.edu 2182683Sktlim@umich.edu /// Set the status to Halted. 2192683Sktlim@umich.edu void halt(); 2202683Sktlim@umich.edu 2212683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2222190SN/A 2236315Sgblack@eecs.umich.edu void clearArchRegs() 2246315Sgblack@eecs.umich.edu { 2257720Sgblack@eecs.umich.edu _pcState = 0; 2266316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 22713501Sgabeblack@google.com memset(floatRegs, 0, sizeof(floatRegs)); 22812109SRekai.GonzalezAlberquilla@arm.com for (int i = 0; i < TheISA::NumVecRegs; i++) { 22912109SRekai.GonzalezAlberquilla@arm.com vecRegs[i].zero(); 23012109SRekai.GonzalezAlberquilla@arm.com } 2319920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 2329920Syasuko.eckert@amd.com memset(ccRegs, 0, sizeof(ccRegs)); 2339920Syasuko.eckert@amd.com#endif 2349384SAndreas.Sandberg@arm.com isa->clear(); 2356315Sgblack@eecs.umich.edu } 2362190SN/A 2372SN/A // 2382SN/A // New accessors for new decoder. 2392SN/A // 24013557Sgabeblack@google.com RegVal 24113557Sgabeblack@google.com readIntReg(int reg_idx) 2422SN/A { 2439384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 2446323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2459426SAndreas.Sandberg@ARM.com uint64_t regVal(readIntRegFlat(flatIndex)); 2467601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2477601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 2486418Sgblack@eecs.umich.edu return regVal; 2492SN/A } 2502SN/A 25113557Sgabeblack@google.com RegVal 25213557Sgabeblack@google.com readFloatRegBits(int reg_idx) 2532455SN/A { 2549384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 2556323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 25613557Sgabeblack@google.com RegVal regVal(readFloatRegBitsFlat(flatIndex)); 25713501Sgabeblack@google.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", 25813501Sgabeblack@google.com reg_idx, flatIndex, regVal); 2597341Sgblack@eecs.umich.edu return regVal; 2602SN/A } 2612SN/A 26212109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& 26312109SRekai.GonzalezAlberquilla@arm.com readVecReg(const RegId& reg) const 26412109SRekai.GonzalezAlberquilla@arm.com { 26512109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 26612109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 26712109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& regVal = readVecRegFlat(flatIndex); 26812109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n", 26912109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print()); 27012109SRekai.GonzalezAlberquilla@arm.com return regVal; 27112109SRekai.GonzalezAlberquilla@arm.com } 27212109SRekai.GonzalezAlberquilla@arm.com 27312109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& 27412109SRekai.GonzalezAlberquilla@arm.com getWritableVecReg(const RegId& reg) 27512109SRekai.GonzalezAlberquilla@arm.com { 27612109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 27712109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 27812109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& regVal = getWritableVecRegFlat(flatIndex); 27912109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n", 28012109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print()); 28112109SRekai.GonzalezAlberquilla@arm.com return regVal; 28212109SRekai.GonzalezAlberquilla@arm.com } 28312109SRekai.GonzalezAlberquilla@arm.com 28412109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 28512109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 28612109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector <T> operand. */ 28712109SRekai.GonzalezAlberquilla@arm.com template <typename T> 28812109SRekai.GonzalezAlberquilla@arm.com VecLaneT<T, true> 28912109SRekai.GonzalezAlberquilla@arm.com readVecLane(const RegId& reg) const 29012109SRekai.GonzalezAlberquilla@arm.com { 29112109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 29212109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 29312109SRekai.GonzalezAlberquilla@arm.com auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex()); 29412109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n", 29512109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, reg.elemIndex(), regVal); 29612109SRekai.GonzalezAlberquilla@arm.com return regVal; 29712109SRekai.GonzalezAlberquilla@arm.com } 29812109SRekai.GonzalezAlberquilla@arm.com 29912109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 30012109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 30112109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneReg(const RegId& reg) const 30212109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint8_t>(reg); } 30312109SRekai.GonzalezAlberquilla@arm.com 30412109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 30512109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 30612109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneReg(const RegId& reg) const 30712109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint16_t>(reg); } 30812109SRekai.GonzalezAlberquilla@arm.com 30912109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 31012109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 31112109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneReg(const RegId& reg) const 31212109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint32_t>(reg); } 31312109SRekai.GonzalezAlberquilla@arm.com 31412109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 31512109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 31612109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneReg(const RegId& reg) const 31712109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint64_t>(reg); } 31812109SRekai.GonzalezAlberquilla@arm.com 31912109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 32012109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 32112109SRekai.GonzalezAlberquilla@arm.com void setVecLaneT(const RegId& reg, const LD& val) 32212109SRekai.GonzalezAlberquilla@arm.com { 32312109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 32412109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 32512109SRekai.GonzalezAlberquilla@arm.com setVecLaneFlat(flatIndex, reg.elemIndex(), val); 32612109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n", 32712109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, reg.elemIndex(), val); 32812109SRekai.GonzalezAlberquilla@arm.com } 32912109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 33012109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) 33112109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 33212109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 33312109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) 33412109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 33512109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 33612109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) 33712109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 33812109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 33912109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) 34012109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 34112109SRekai.GonzalezAlberquilla@arm.com /** @} */ 34212109SRekai.GonzalezAlberquilla@arm.com 34312109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElem(const RegId& reg) const 34412109SRekai.GonzalezAlberquilla@arm.com { 34512109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecElemIndex(reg.index()); 34612109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 34712109SRekai.GonzalezAlberquilla@arm.com const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex()); 34812109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as" 34912109SRekai.GonzalezAlberquilla@arm.com " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal); 35012109SRekai.GonzalezAlberquilla@arm.com return regVal; 35112109SRekai.GonzalezAlberquilla@arm.com } 35212109SRekai.GonzalezAlberquilla@arm.com 35312109SRekai.GonzalezAlberquilla@arm.com 3549920Syasuko.eckert@amd.com CCReg readCCReg(int reg_idx) 3559920Syasuko.eckert@amd.com { 3569920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 3579920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 35810338SCurtis.Dunham@arm.com assert(0 <= flatIndex); 3599920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 3609920Syasuko.eckert@amd.com uint64_t regVal(readCCRegFlat(flatIndex)); 3619920Syasuko.eckert@amd.com DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 3629920Syasuko.eckert@amd.com reg_idx, flatIndex, regVal); 3639920Syasuko.eckert@amd.com return regVal; 3649920Syasuko.eckert@amd.com#else 3659920Syasuko.eckert@amd.com panic("Tried to read a CC register."); 3669920Syasuko.eckert@amd.com return 0; 3679920Syasuko.eckert@amd.com#endif 3689920Syasuko.eckert@amd.com } 3699920Syasuko.eckert@amd.com 37013557Sgabeblack@google.com void 37113557Sgabeblack@google.com setIntReg(int reg_idx, RegVal val) 3722SN/A { 3739384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 3746323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 3757601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 3767601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 3779426SAndreas.Sandberg@ARM.com setIntRegFlat(flatIndex, val); 3782SN/A } 3792SN/A 38013557Sgabeblack@google.com void 38113557Sgabeblack@google.com setFloatRegBits(int reg_idx, RegVal val) 3822455SN/A { 3839384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 3846323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 3858733Sgeoffrey.blake@arm.com // XXX: Fix array out of bounds compiler error for gem5.fast 3868733Sgeoffrey.blake@arm.com // when checkercpu enabled 3878733Sgeoffrey.blake@arm.com if (flatIndex < TheISA::NumFloatRegs) 3889426SAndreas.Sandberg@ARM.com setFloatRegBitsFlat(flatIndex, val); 38913501Sgabeblack@google.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", 39013501Sgabeblack@google.com reg_idx, flatIndex, val); 3912SN/A } 3922SN/A 39313557Sgabeblack@google.com void 39413557Sgabeblack@google.com setVecReg(const RegId& reg, const VecRegContainer& val) 39512109SRekai.GonzalezAlberquilla@arm.com { 39612109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 39712109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 39812109SRekai.GonzalezAlberquilla@arm.com setVecRegFlat(flatIndex, val); 39912109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n", 40012109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, val.print()); 40112109SRekai.GonzalezAlberquilla@arm.com } 40212109SRekai.GonzalezAlberquilla@arm.com 40313557Sgabeblack@google.com void 40413557Sgabeblack@google.com setVecElem(const RegId& reg, const VecElem& val) 40512109SRekai.GonzalezAlberquilla@arm.com { 40612109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecElemIndex(reg.index()); 40712109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 40812109SRekai.GonzalezAlberquilla@arm.com setVecElemFlat(flatIndex, reg.elemIndex(), val); 40912109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 41012109SRekai.GonzalezAlberquilla@arm.com " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 41112109SRekai.GonzalezAlberquilla@arm.com } 41212109SRekai.GonzalezAlberquilla@arm.com 41313557Sgabeblack@google.com void 41413557Sgabeblack@google.com setCCReg(int reg_idx, CCReg val) 4159920Syasuko.eckert@amd.com { 4169920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 4179920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 4189920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 4199920Syasuko.eckert@amd.com DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 4209920Syasuko.eckert@amd.com reg_idx, flatIndex, val); 4219920Syasuko.eckert@amd.com setCCRegFlat(flatIndex, val); 4229920Syasuko.eckert@amd.com#else 4239920Syasuko.eckert@amd.com panic("Tried to set a CC register."); 4249920Syasuko.eckert@amd.com#endif 4259920Syasuko.eckert@amd.com } 4269920Syasuko.eckert@amd.com 4277720Sgblack@eecs.umich.edu TheISA::PCState 4287720Sgblack@eecs.umich.edu pcState() 4292SN/A { 4307720Sgblack@eecs.umich.edu return _pcState; 4312SN/A } 4322SN/A 4337720Sgblack@eecs.umich.edu void 4347720Sgblack@eecs.umich.edu pcState(const TheISA::PCState &val) 4352190SN/A { 4367720Sgblack@eecs.umich.edu _pcState = val; 4372190SN/A } 4382190SN/A 4398733Sgeoffrey.blake@arm.com void 4408733Sgeoffrey.blake@arm.com pcStateNoRecord(const TheISA::PCState &val) 4418733Sgeoffrey.blake@arm.com { 4428733Sgeoffrey.blake@arm.com _pcState = val; 4438733Sgeoffrey.blake@arm.com } 4448733Sgeoffrey.blake@arm.com 4457720Sgblack@eecs.umich.edu Addr 4467720Sgblack@eecs.umich.edu instAddr() 4473276Sgblack@eecs.umich.edu { 4487720Sgblack@eecs.umich.edu return _pcState.instAddr(); 4493276Sgblack@eecs.umich.edu } 4503276Sgblack@eecs.umich.edu 4517720Sgblack@eecs.umich.edu Addr 4527720Sgblack@eecs.umich.edu nextInstAddr() 4533276Sgblack@eecs.umich.edu { 4547720Sgblack@eecs.umich.edu return _pcState.nextInstAddr(); 4553276Sgblack@eecs.umich.edu } 4563276Sgblack@eecs.umich.edu 45711886Sbrandon.potter@amd.com void 45811886Sbrandon.potter@amd.com setNPC(Addr val) 45911886Sbrandon.potter@amd.com { 46011886Sbrandon.potter@amd.com _pcState.setNPC(val); 46111886Sbrandon.potter@amd.com } 46211886Sbrandon.potter@amd.com 4637720Sgblack@eecs.umich.edu MicroPC 4647720Sgblack@eecs.umich.edu microPC() 4652190SN/A { 4667720Sgblack@eecs.umich.edu return _pcState.microPC(); 4672251SN/A } 4682251SN/A 4697597Sminkyu.jeong@arm.com bool readPredicate() 4707597Sminkyu.jeong@arm.com { 4717597Sminkyu.jeong@arm.com return predicate; 4727597Sminkyu.jeong@arm.com } 4737597Sminkyu.jeong@arm.com 4747597Sminkyu.jeong@arm.com void setPredicate(bool val) 4757597Sminkyu.jeong@arm.com { 4767597Sminkyu.jeong@arm.com predicate = val; 4777597Sminkyu.jeong@arm.com } 4787597Sminkyu.jeong@arm.com 47913557Sgabeblack@google.com RegVal 48013557Sgabeblack@google.com readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const 4814172Ssaidi@eecs.umich.edu { 4829384SAndreas.Sandberg@arm.com return isa->readMiscRegNoEffect(misc_reg); 4834172Ssaidi@eecs.umich.edu } 4844172Ssaidi@eecs.umich.edu 48513557Sgabeblack@google.com RegVal 48613557Sgabeblack@google.com readMiscReg(int misc_reg, ThreadID tid=0) 4872SN/A { 4889384SAndreas.Sandberg@arm.com return isa->readMiscReg(misc_reg, tc); 4892SN/A } 4902SN/A 4916221Snate@binkert.org void 49213582Sgabeblack@google.com setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid = 0) 4932SN/A { 4949384SAndreas.Sandberg@arm.com return isa->setMiscRegNoEffect(misc_reg, val); 4952SN/A } 4962SN/A 4976221Snate@binkert.org void 49813582Sgabeblack@google.com setMiscReg(int misc_reg, RegVal val, ThreadID tid = 0) 4992SN/A { 5009384SAndreas.Sandberg@arm.com return isa->setMiscReg(misc_reg, val, tc); 5016313Sgblack@eecs.umich.edu } 5026313Sgblack@eecs.umich.edu 50312106SRekai.GonzalezAlberquilla@arm.com RegId 50412106SRekai.GonzalezAlberquilla@arm.com flattenRegId(const RegId& regId) const 5056313Sgblack@eecs.umich.edu { 50612106SRekai.GonzalezAlberquilla@arm.com return isa->flattenRegId(regId); 50710033SAli.Saidi@ARM.com } 50810033SAli.Saidi@ARM.com 5092190SN/A unsigned readStCondFailures() { return storeCondFailures; } 5102190SN/A 5112190SN/A void setStCondFailures(unsigned sc_failures) 5122190SN/A { storeCondFailures = sc_failures; } 5132190SN/A 51413557Sgabeblack@google.com void 51513557Sgabeblack@google.com syscall(int64_t callnum, Fault *fault) 5162SN/A { 51711877Sbrandon.potter@amd.com process->syscall(callnum, tc, fault); 5182SN/A } 5199426SAndreas.Sandberg@ARM.com 52013557Sgabeblack@google.com RegVal readIntRegFlat(int idx) { return intRegs[idx]; } 52113557Sgabeblack@google.com void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; } 5229426SAndreas.Sandberg@ARM.com 52313557Sgabeblack@google.com RegVal readFloatRegBitsFlat(int idx) { return floatRegs[idx]; } 52413557Sgabeblack@google.com void setFloatRegBitsFlat(int idx, RegVal val) { floatRegs[idx] = val; } 5259426SAndreas.Sandberg@ARM.com 52613557Sgabeblack@google.com const VecRegContainer & 52713557Sgabeblack@google.com readVecRegFlat(const RegIndex& reg) const 52812109SRekai.GonzalezAlberquilla@arm.com { 52912109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg]; 53012109SRekai.GonzalezAlberquilla@arm.com } 53112109SRekai.GonzalezAlberquilla@arm.com 53213557Sgabeblack@google.com VecRegContainer & 53313557Sgabeblack@google.com getWritableVecRegFlat(const RegIndex& reg) 53412109SRekai.GonzalezAlberquilla@arm.com { 53512109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg]; 53612109SRekai.GonzalezAlberquilla@arm.com } 53712109SRekai.GonzalezAlberquilla@arm.com 53813557Sgabeblack@google.com void 53913557Sgabeblack@google.com setVecRegFlat(const RegIndex& reg, const VecRegContainer& val) 54012109SRekai.GonzalezAlberquilla@arm.com { 54112109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg] = val; 54212109SRekai.GonzalezAlberquilla@arm.com } 54312109SRekai.GonzalezAlberquilla@arm.com 54412109SRekai.GonzalezAlberquilla@arm.com template <typename T> 54513557Sgabeblack@google.com VecLaneT<T, true> 54613557Sgabeblack@google.com readVecLaneFlat(const RegIndex& reg, int lId) const 54712109SRekai.GonzalezAlberquilla@arm.com { 54812109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg].laneView<T>(lId); 54912109SRekai.GonzalezAlberquilla@arm.com } 55012109SRekai.GonzalezAlberquilla@arm.com 55112109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 55213557Sgabeblack@google.com void 55313557Sgabeblack@google.com setVecLaneFlat(const RegIndex& reg, int lId, const LD& val) 55412109SRekai.GonzalezAlberquilla@arm.com { 55512109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; 55612109SRekai.GonzalezAlberquilla@arm.com } 55712109SRekai.GonzalezAlberquilla@arm.com 55813557Sgabeblack@google.com const VecElem & 55913557Sgabeblack@google.com readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const 56012109SRekai.GonzalezAlberquilla@arm.com { 56112109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; 56212109SRekai.GonzalezAlberquilla@arm.com } 56312109SRekai.GonzalezAlberquilla@arm.com 56413557Sgabeblack@google.com void 56513557Sgabeblack@google.com setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex, 56613557Sgabeblack@google.com const VecElem val) 56712109SRekai.GonzalezAlberquilla@arm.com { 56812109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 56912109SRekai.GonzalezAlberquilla@arm.com } 57012109SRekai.GonzalezAlberquilla@arm.com 5719920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 5729920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 5739920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 5749920Syasuko.eckert@amd.com#else 5759920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) 5769920Syasuko.eckert@amd.com { panic("readCCRegFlat w/no CC regs!\n"); } 5779920Syasuko.eckert@amd.com 5789920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) 5799920Syasuko.eckert@amd.com { panic("setCCRegFlat w/no CC regs!\n"); } 5809920Syasuko.eckert@amd.com#endif 5812SN/A}; 5822SN/A 5832SN/A 5842190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 585