simple_thread.hh revision 12406
12SN/A/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2011-2012, 2016 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 412665SN/A * Authors: Steve Reinhardt 422665SN/A * Nathan Binkert 432SN/A */ 442SN/A 452683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 462683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 472SN/A 489020Sgblack@eecs.umich.edu#include "arch/decoder.hh" 4912406Sgabeblack@google.com#include "arch/generic/tlb.hh" 506313Sgblack@eecs.umich.edu#include "arch/isa.hh" 512190SN/A#include "arch/isa_traits.hh" 526329Sgblack@eecs.umich.edu#include "arch/registers.hh" 536316Sgblack@eecs.umich.edu#include "arch/types.hh" 546216Snate@binkert.org#include "base/types.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 562680SN/A#include "cpu/thread_context.hh" 572683Sktlim@umich.edu#include "cpu/thread_state.hh" 589920Syasuko.eckert@amd.com#include "debug/CCRegs.hh" 598232Snate@binkert.org#include "debug/FloatRegs.hh" 608232Snate@binkert.org#include "debug/IntRegs.hh" 6112109SRekai.GonzalezAlberquilla@arm.com#include "debug/VecRegs.hh" 628777Sgblack@eecs.umich.edu#include "mem/page_table.hh" 632395SN/A#include "mem/request.hh" 642190SN/A#include "sim/byteswap.hh" 652188SN/A#include "sim/eventq.hh" 668777Sgblack@eecs.umich.edu#include "sim/process.hh" 67217SN/A#include "sim/serialize.hh" 688777Sgblack@eecs.umich.edu#include "sim/system.hh" 692SN/A 702SN/Aclass BaseCPU; 718887Sgeoffrey.blake@arm.comclass CheckerCPU; 721070SN/A 731917SN/Aclass FunctionProfile; 741917SN/Aclass ProfileNode; 752521SN/A 763548Sgblack@eecs.umich.edunamespace TheISA { 773548Sgblack@eecs.umich.edu namespace Kernel { 783548Sgblack@eecs.umich.edu class Statistics; 798902Sandreas.hansson@arm.com } 808902Sandreas.hansson@arm.com} 812330SN/A 822683Sktlim@umich.edu/** 832683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 842683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 852683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 862683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 872683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 882683Sktlim@umich.edu * the objects needed for simple functional execution, including a 892683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 902683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 912683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 922683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 932683Sktlim@umich.edu * all the necessary state for full architecture-level functional 942683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 952683Sktlim@umich.edu * examples. 962683Sktlim@umich.edu */ 972SN/A 982683Sktlim@umich.educlass SimpleThread : public ThreadState 992SN/A{ 1002107SN/A protected: 1012107SN/A typedef TheISA::MachInst MachInst; 1022159SN/A typedef TheISA::MiscReg MiscReg; 1032455SN/A typedef TheISA::FloatReg FloatReg; 1042455SN/A typedef TheISA::FloatRegBits FloatRegBits; 1059920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 10612109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 10712109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 1082SN/A public: 1092680SN/A typedef ThreadContext::Status Status; 1102SN/A 1112190SN/A protected: 1126315Sgblack@eecs.umich.edu union { 1136315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1146315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1156315Sgblack@eecs.umich.edu } floatRegs; 1166316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 11712109SRekai.GonzalezAlberquilla@arm.com VecRegContainer vecRegs[TheISA::NumVecRegs]; 1189920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 1199920Syasuko.eckert@amd.com TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 1209920Syasuko.eckert@amd.com#endif 1219384SAndreas.Sandberg@arm.com TheISA::ISA *const isa; // one "instance" of the current ISA. 1222SN/A 1237720Sgblack@eecs.umich.edu TheISA::PCState _pcState; 1246324Sgblack@eecs.umich.edu 1257597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1267597Sminkyu.jeong@arm.com bool predicate; 1277597Sminkyu.jeong@arm.com 1282190SN/A public: 1298357Sksewell@umich.edu std::string name() const 1308357Sksewell@umich.edu { 1318735Sandreas.hanson@arm.com return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 1328357Sksewell@umich.edu } 1338357Sksewell@umich.edu 1342683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1352188SN/A 1362378SN/A System *system; 1372400SN/A 13812406Sgabeblack@google.com BaseTLB *itb; 13912406Sgabeblack@google.com BaseTLB *dtb; 1402SN/A 1419020Sgblack@eecs.umich.edu TheISA::Decoder decoder; 1428541Sgblack@eecs.umich.edu 1432683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1448793Sgblack@eecs.umich.edu // FS 1452683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 14612406Sgabeblack@google.com BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa, 1472683Sktlim@umich.edu bool use_kernel_stats = true); 1488793Sgblack@eecs.umich.edu // SE 1498820Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 15012406Sgabeblack@google.com Process *_process, BaseTLB *_itb, BaseTLB *_dtb, 1519384SAndreas.Sandberg@arm.com TheISA::ISA *_isa); 1522862Sktlim@umich.edu 1532683Sktlim@umich.edu virtual ~SimpleThread(); 1542SN/A 1552680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 156180SN/A 1572SN/A void regStats(const std::string &name); 1582SN/A 1592862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1602862Sktlim@umich.edu 16111168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 16211168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1639461Snilay@cs.wisc.edu void startup(); 164217SN/A 1652683Sktlim@umich.edu /*************************************************************** 1662683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1675891Sgblack@eecs.umich.edu * state. 1682683Sktlim@umich.edu **************************************************************/ 1692190SN/A 1702683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1712683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1722683Sktlim@umich.edu * CPU. 1732683Sktlim@umich.edu */ 1742680SN/A ThreadContext *getTC() { return tc; } 1752190SN/A 1765358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1775358Sgblack@eecs.umich.edu { 1785358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1795358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1805358Sgblack@eecs.umich.edu } 1815358Sgblack@eecs.umich.edu 1825358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1835358Sgblack@eecs.umich.edu { 1845358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1855358Sgblack@eecs.umich.edu } 1865358Sgblack@eecs.umich.edu 1875358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1885358Sgblack@eecs.umich.edu { 1895358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1905358Sgblack@eecs.umich.edu } 1915358Sgblack@eecs.umich.edu 1922683Sktlim@umich.edu void dumpFuncProfile(); 1932521SN/A 1945702Ssaidi@eecs.umich.edu Fault hwrei(); 1955702Ssaidi@eecs.umich.edu 1965702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1975702Ssaidi@eecs.umich.edu 1982683Sktlim@umich.edu /******************************************* 1992683Sktlim@umich.edu * ThreadContext interface functions. 2002683Sktlim@umich.edu ******************************************/ 2012683Sktlim@umich.edu 2028735Sandreas.hanson@arm.com BaseCPU *getCpuPtr() { return baseCpu; } 2032683Sktlim@umich.edu 20412406Sgabeblack@google.com BaseTLB *getITBPtr() { return itb; } 2052683Sktlim@umich.edu 20612406Sgabeblack@google.com BaseTLB *getDTBPtr() { return dtb; } 2072683Sktlim@umich.edu 2088887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return NULL; } 2098733Sgeoffrey.blake@arm.com 2109020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return &decoder; } 2118541Sgblack@eecs.umich.edu 2124997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2134997Sgblack@eecs.umich.edu 2142683Sktlim@umich.edu Status status() const { return _status; } 2152683Sktlim@umich.edu 2162683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2172683Sktlim@umich.edu 21810407Smitch.hayenga@arm.com /// Set the status to Active. 21910407Smitch.hayenga@arm.com void activate(); 2202683Sktlim@umich.edu 2212683Sktlim@umich.edu /// Set the status to Suspended. 2222683Sktlim@umich.edu void suspend(); 2232683Sktlim@umich.edu 2242683Sktlim@umich.edu /// Set the status to Halted. 2252683Sktlim@umich.edu void halt(); 2262683Sktlim@umich.edu 2272683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2282190SN/A 2296315Sgblack@eecs.umich.edu void clearArchRegs() 2306315Sgblack@eecs.umich.edu { 2317720Sgblack@eecs.umich.edu _pcState = 0; 2326316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 2336315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 23412109SRekai.GonzalezAlberquilla@arm.com for (int i = 0; i < TheISA::NumVecRegs; i++) { 23512109SRekai.GonzalezAlberquilla@arm.com vecRegs[i].zero(); 23612109SRekai.GonzalezAlberquilla@arm.com } 2379920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 2389920Syasuko.eckert@amd.com memset(ccRegs, 0, sizeof(ccRegs)); 2399920Syasuko.eckert@amd.com#endif 2409384SAndreas.Sandberg@arm.com isa->clear(); 2416315Sgblack@eecs.umich.edu } 2422190SN/A 2432SN/A // 2442SN/A // New accessors for new decoder. 2452SN/A // 2462SN/A uint64_t readIntReg(int reg_idx) 2472SN/A { 2489384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 2496323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2509426SAndreas.Sandberg@ARM.com uint64_t regVal(readIntRegFlat(flatIndex)); 2517601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2527601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 2536418Sgblack@eecs.umich.edu return regVal; 2542SN/A } 2552SN/A 2562455SN/A FloatReg readFloatReg(int reg_idx) 2572SN/A { 2589384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 2596323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2609426SAndreas.Sandberg@ARM.com FloatReg regVal(readFloatRegFlat(flatIndex)); 2617601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 2627601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 2637341Sgblack@eecs.umich.edu return regVal; 2642SN/A } 2652SN/A 2662455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2672455SN/A { 2689384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 2696323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2709426SAndreas.Sandberg@ARM.com FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); 2717601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 2727601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 2737341Sgblack@eecs.umich.edu return regVal; 2742SN/A } 2752SN/A 27612109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& 27712109SRekai.GonzalezAlberquilla@arm.com readVecReg(const RegId& reg) const 27812109SRekai.GonzalezAlberquilla@arm.com { 27912109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 28012109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 28112109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& regVal = readVecRegFlat(flatIndex); 28212109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n", 28312109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print()); 28412109SRekai.GonzalezAlberquilla@arm.com return regVal; 28512109SRekai.GonzalezAlberquilla@arm.com } 28612109SRekai.GonzalezAlberquilla@arm.com 28712109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& 28812109SRekai.GonzalezAlberquilla@arm.com getWritableVecReg(const RegId& reg) 28912109SRekai.GonzalezAlberquilla@arm.com { 29012109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 29112109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 29212109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& regVal = getWritableVecRegFlat(flatIndex); 29312109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n", 29412109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print()); 29512109SRekai.GonzalezAlberquilla@arm.com return regVal; 29612109SRekai.GonzalezAlberquilla@arm.com } 29712109SRekai.GonzalezAlberquilla@arm.com 29812109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 29912109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 30012109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector <T> operand. */ 30112109SRekai.GonzalezAlberquilla@arm.com template <typename T> 30212109SRekai.GonzalezAlberquilla@arm.com VecLaneT<T, true> 30312109SRekai.GonzalezAlberquilla@arm.com readVecLane(const RegId& reg) const 30412109SRekai.GonzalezAlberquilla@arm.com { 30512109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 30612109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 30712109SRekai.GonzalezAlberquilla@arm.com auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex()); 30812109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n", 30912109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, reg.elemIndex(), regVal); 31012109SRekai.GonzalezAlberquilla@arm.com return regVal; 31112109SRekai.GonzalezAlberquilla@arm.com } 31212109SRekai.GonzalezAlberquilla@arm.com 31312109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 31412109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 31512109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneReg(const RegId& reg) const 31612109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint8_t>(reg); } 31712109SRekai.GonzalezAlberquilla@arm.com 31812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 31912109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 32012109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneReg(const RegId& reg) const 32112109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint16_t>(reg); } 32212109SRekai.GonzalezAlberquilla@arm.com 32312109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 32412109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 32512109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneReg(const RegId& reg) const 32612109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint32_t>(reg); } 32712109SRekai.GonzalezAlberquilla@arm.com 32812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 32912109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 33012109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneReg(const RegId& reg) const 33112109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint64_t>(reg); } 33212109SRekai.GonzalezAlberquilla@arm.com 33312109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 33412109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 33512109SRekai.GonzalezAlberquilla@arm.com void setVecLaneT(const RegId& reg, const LD& val) 33612109SRekai.GonzalezAlberquilla@arm.com { 33712109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 33812109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 33912109SRekai.GonzalezAlberquilla@arm.com setVecLaneFlat(flatIndex, reg.elemIndex(), val); 34012109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n", 34112109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, reg.elemIndex(), val); 34212109SRekai.GonzalezAlberquilla@arm.com } 34312109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 34412109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) 34512109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 34612109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 34712109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) 34812109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 34912109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 35012109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) 35112109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 35212109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 35312109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) 35412109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 35512109SRekai.GonzalezAlberquilla@arm.com /** @} */ 35612109SRekai.GonzalezAlberquilla@arm.com 35712109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElem(const RegId& reg) const 35812109SRekai.GonzalezAlberquilla@arm.com { 35912109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecElemIndex(reg.index()); 36012109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 36112109SRekai.GonzalezAlberquilla@arm.com const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex()); 36212109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as" 36312109SRekai.GonzalezAlberquilla@arm.com " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal); 36412109SRekai.GonzalezAlberquilla@arm.com return regVal; 36512109SRekai.GonzalezAlberquilla@arm.com } 36612109SRekai.GonzalezAlberquilla@arm.com 36712109SRekai.GonzalezAlberquilla@arm.com 3689920Syasuko.eckert@amd.com CCReg readCCReg(int reg_idx) 3699920Syasuko.eckert@amd.com { 3709920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 3719920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 37210338SCurtis.Dunham@arm.com assert(0 <= flatIndex); 3739920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 3749920Syasuko.eckert@amd.com uint64_t regVal(readCCRegFlat(flatIndex)); 3759920Syasuko.eckert@amd.com DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 3769920Syasuko.eckert@amd.com reg_idx, flatIndex, regVal); 3779920Syasuko.eckert@amd.com return regVal; 3789920Syasuko.eckert@amd.com#else 3799920Syasuko.eckert@amd.com panic("Tried to read a CC register."); 3809920Syasuko.eckert@amd.com return 0; 3819920Syasuko.eckert@amd.com#endif 3829920Syasuko.eckert@amd.com } 3839920Syasuko.eckert@amd.com 3842SN/A void setIntReg(int reg_idx, uint64_t val) 3852SN/A { 3869384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 3876323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 3887601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 3897601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 3909426SAndreas.Sandberg@ARM.com setIntRegFlat(flatIndex, val); 3912SN/A } 3922SN/A 3932455SN/A void setFloatReg(int reg_idx, FloatReg val) 3942SN/A { 3959384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 3966323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 3979426SAndreas.Sandberg@ARM.com setFloatRegFlat(flatIndex, val); 3987601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 3997601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 4002SN/A } 4012SN/A 4022455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 4032455SN/A { 4049384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 4056323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 4068733Sgeoffrey.blake@arm.com // XXX: Fix array out of bounds compiler error for gem5.fast 4078733Sgeoffrey.blake@arm.com // when checkercpu enabled 4088733Sgeoffrey.blake@arm.com if (flatIndex < TheISA::NumFloatRegs) 4099426SAndreas.Sandberg@ARM.com setFloatRegBitsFlat(flatIndex, val); 4107601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 4117601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 4122SN/A } 4132SN/A 41412109SRekai.GonzalezAlberquilla@arm.com void setVecReg(const RegId& reg, const VecRegContainer& val) 41512109SRekai.GonzalezAlberquilla@arm.com { 41612109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 41712109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 41812109SRekai.GonzalezAlberquilla@arm.com setVecRegFlat(flatIndex, val); 41912109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n", 42012109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, val.print()); 42112109SRekai.GonzalezAlberquilla@arm.com } 42212109SRekai.GonzalezAlberquilla@arm.com 42312109SRekai.GonzalezAlberquilla@arm.com void setVecElem(const RegId& reg, const VecElem& val) 42412109SRekai.GonzalezAlberquilla@arm.com { 42512109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecElemIndex(reg.index()); 42612109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 42712109SRekai.GonzalezAlberquilla@arm.com setVecElemFlat(flatIndex, reg.elemIndex(), val); 42812109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 42912109SRekai.GonzalezAlberquilla@arm.com " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 43012109SRekai.GonzalezAlberquilla@arm.com } 43112109SRekai.GonzalezAlberquilla@arm.com 4329920Syasuko.eckert@amd.com void setCCReg(int reg_idx, CCReg val) 4339920Syasuko.eckert@amd.com { 4349920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 4359920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 4369920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 4379920Syasuko.eckert@amd.com DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 4389920Syasuko.eckert@amd.com reg_idx, flatIndex, val); 4399920Syasuko.eckert@amd.com setCCRegFlat(flatIndex, val); 4409920Syasuko.eckert@amd.com#else 4419920Syasuko.eckert@amd.com panic("Tried to set a CC register."); 4429920Syasuko.eckert@amd.com#endif 4439920Syasuko.eckert@amd.com } 4449920Syasuko.eckert@amd.com 4457720Sgblack@eecs.umich.edu TheISA::PCState 4467720Sgblack@eecs.umich.edu pcState() 4472SN/A { 4487720Sgblack@eecs.umich.edu return _pcState; 4492SN/A } 4502SN/A 4517720Sgblack@eecs.umich.edu void 4527720Sgblack@eecs.umich.edu pcState(const TheISA::PCState &val) 4532190SN/A { 4547720Sgblack@eecs.umich.edu _pcState = val; 4552190SN/A } 4562190SN/A 4578733Sgeoffrey.blake@arm.com void 4588733Sgeoffrey.blake@arm.com pcStateNoRecord(const TheISA::PCState &val) 4598733Sgeoffrey.blake@arm.com { 4608733Sgeoffrey.blake@arm.com _pcState = val; 4618733Sgeoffrey.blake@arm.com } 4628733Sgeoffrey.blake@arm.com 4637720Sgblack@eecs.umich.edu Addr 4647720Sgblack@eecs.umich.edu instAddr() 4653276Sgblack@eecs.umich.edu { 4667720Sgblack@eecs.umich.edu return _pcState.instAddr(); 4673276Sgblack@eecs.umich.edu } 4683276Sgblack@eecs.umich.edu 4697720Sgblack@eecs.umich.edu Addr 4707720Sgblack@eecs.umich.edu nextInstAddr() 4713276Sgblack@eecs.umich.edu { 4727720Sgblack@eecs.umich.edu return _pcState.nextInstAddr(); 4733276Sgblack@eecs.umich.edu } 4743276Sgblack@eecs.umich.edu 47511886Sbrandon.potter@amd.com void 47611886Sbrandon.potter@amd.com setNPC(Addr val) 47711886Sbrandon.potter@amd.com { 47811886Sbrandon.potter@amd.com _pcState.setNPC(val); 47911886Sbrandon.potter@amd.com } 48011886Sbrandon.potter@amd.com 4817720Sgblack@eecs.umich.edu MicroPC 4827720Sgblack@eecs.umich.edu microPC() 4832190SN/A { 4847720Sgblack@eecs.umich.edu return _pcState.microPC(); 4852251SN/A } 4862251SN/A 4877597Sminkyu.jeong@arm.com bool readPredicate() 4887597Sminkyu.jeong@arm.com { 4897597Sminkyu.jeong@arm.com return predicate; 4907597Sminkyu.jeong@arm.com } 4917597Sminkyu.jeong@arm.com 4927597Sminkyu.jeong@arm.com void setPredicate(bool val) 4937597Sminkyu.jeong@arm.com { 4947597Sminkyu.jeong@arm.com predicate = val; 4957597Sminkyu.jeong@arm.com } 4967597Sminkyu.jeong@arm.com 4976221Snate@binkert.org MiscReg 49810698Sandreas.hansson@arm.com readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const 4994172Ssaidi@eecs.umich.edu { 5009384SAndreas.Sandberg@arm.com return isa->readMiscRegNoEffect(misc_reg); 5014172Ssaidi@eecs.umich.edu } 5024172Ssaidi@eecs.umich.edu 5036221Snate@binkert.org MiscReg 5046221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 5052SN/A { 5069384SAndreas.Sandberg@arm.com return isa->readMiscReg(misc_reg, tc); 5072SN/A } 5082SN/A 5096221Snate@binkert.org void 5106221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 5112SN/A { 5129384SAndreas.Sandberg@arm.com return isa->setMiscRegNoEffect(misc_reg, val); 5132SN/A } 5142SN/A 5156221Snate@binkert.org void 5166221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 5172SN/A { 5189384SAndreas.Sandberg@arm.com return isa->setMiscReg(misc_reg, val, tc); 5196313Sgblack@eecs.umich.edu } 5206313Sgblack@eecs.umich.edu 52112106SRekai.GonzalezAlberquilla@arm.com RegId 52212106SRekai.GonzalezAlberquilla@arm.com flattenRegId(const RegId& regId) const 5236313Sgblack@eecs.umich.edu { 52412106SRekai.GonzalezAlberquilla@arm.com return isa->flattenRegId(regId); 52510033SAli.Saidi@ARM.com } 52610033SAli.Saidi@ARM.com 5272190SN/A unsigned readStCondFailures() { return storeCondFailures; } 5282190SN/A 5292190SN/A void setStCondFailures(unsigned sc_failures) 5302190SN/A { storeCondFailures = sc_failures; } 5312190SN/A 53211877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) 5332SN/A { 53411877Sbrandon.potter@amd.com process->syscall(callnum, tc, fault); 5352SN/A } 5369426SAndreas.Sandberg@ARM.com 5379426SAndreas.Sandberg@ARM.com uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } 5389426SAndreas.Sandberg@ARM.com void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } 5399426SAndreas.Sandberg@ARM.com 5409426SAndreas.Sandberg@ARM.com FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; } 5419426SAndreas.Sandberg@ARM.com void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; } 5429426SAndreas.Sandberg@ARM.com 5439426SAndreas.Sandberg@ARM.com FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; } 5449426SAndreas.Sandberg@ARM.com void setFloatRegBitsFlat(int idx, FloatRegBits val) { 5459426SAndreas.Sandberg@ARM.com floatRegs.i[idx] = val; 5469426SAndreas.Sandberg@ARM.com } 5479426SAndreas.Sandberg@ARM.com 54812109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecRegFlat(const RegIndex& reg) const 54912109SRekai.GonzalezAlberquilla@arm.com { 55012109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg]; 55112109SRekai.GonzalezAlberquilla@arm.com } 55212109SRekai.GonzalezAlberquilla@arm.com 55312109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecRegFlat(const RegIndex& reg) 55412109SRekai.GonzalezAlberquilla@arm.com { 55512109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg]; 55612109SRekai.GonzalezAlberquilla@arm.com } 55712109SRekai.GonzalezAlberquilla@arm.com 55812109SRekai.GonzalezAlberquilla@arm.com void setVecRegFlat(const RegIndex& reg, const VecRegContainer& val) 55912109SRekai.GonzalezAlberquilla@arm.com { 56012109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg] = val; 56112109SRekai.GonzalezAlberquilla@arm.com } 56212109SRekai.GonzalezAlberquilla@arm.com 56312109SRekai.GonzalezAlberquilla@arm.com template <typename T> 56412109SRekai.GonzalezAlberquilla@arm.com VecLaneT<T, true> readVecLaneFlat(const RegIndex& reg, int lId) const 56512109SRekai.GonzalezAlberquilla@arm.com { 56612109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg].laneView<T>(lId); 56712109SRekai.GonzalezAlberquilla@arm.com } 56812109SRekai.GonzalezAlberquilla@arm.com 56912109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 57012109SRekai.GonzalezAlberquilla@arm.com void setVecLaneFlat(const RegIndex& reg, int lId, const LD& val) 57112109SRekai.GonzalezAlberquilla@arm.com { 57212109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; 57312109SRekai.GonzalezAlberquilla@arm.com } 57412109SRekai.GonzalezAlberquilla@arm.com 57512109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElemFlat(const RegIndex& reg, 57612109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elemIndex) const 57712109SRekai.GonzalezAlberquilla@arm.com { 57812109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; 57912109SRekai.GonzalezAlberquilla@arm.com } 58012109SRekai.GonzalezAlberquilla@arm.com 58112109SRekai.GonzalezAlberquilla@arm.com void setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex, 58212109SRekai.GonzalezAlberquilla@arm.com const VecElem val) 58312109SRekai.GonzalezAlberquilla@arm.com { 58412109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 58512109SRekai.GonzalezAlberquilla@arm.com } 58612109SRekai.GonzalezAlberquilla@arm.com 5879920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 5889920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 5899920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 5909920Syasuko.eckert@amd.com#else 5919920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) 5929920Syasuko.eckert@amd.com { panic("readCCRegFlat w/no CC regs!\n"); } 5939920Syasuko.eckert@amd.com 5949920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) 5959920Syasuko.eckert@amd.com { panic("setCCRegFlat w/no CC regs!\n"); } 5969920Syasuko.eckert@amd.com#endif 5972SN/A}; 5982SN/A 5992SN/A 6002190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 601