simple_thread.hh revision 11877
12SN/A/* 210033SAli.Saidi@ARM.com * Copyright (c) 2011-2012 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 412665SN/A * Authors: Steve Reinhardt 422665SN/A * Nathan Binkert 432SN/A */ 442SN/A 452683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 462683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 472SN/A 489020Sgblack@eecs.umich.edu#include "arch/decoder.hh" 496313Sgblack@eecs.umich.edu#include "arch/isa.hh" 502190SN/A#include "arch/isa_traits.hh" 516329Sgblack@eecs.umich.edu#include "arch/registers.hh" 524997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 536316Sgblack@eecs.umich.edu#include "arch/types.hh" 546216Snate@binkert.org#include "base/types.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 562680SN/A#include "cpu/thread_context.hh" 572683Sktlim@umich.edu#include "cpu/thread_state.hh" 589920Syasuko.eckert@amd.com#include "debug/CCRegs.hh" 598232Snate@binkert.org#include "debug/FloatRegs.hh" 608232Snate@binkert.org#include "debug/IntRegs.hh" 618777Sgblack@eecs.umich.edu#include "mem/page_table.hh" 622395SN/A#include "mem/request.hh" 632190SN/A#include "sim/byteswap.hh" 642188SN/A#include "sim/eventq.hh" 658777Sgblack@eecs.umich.edu#include "sim/process.hh" 66217SN/A#include "sim/serialize.hh" 678777Sgblack@eecs.umich.edu#include "sim/system.hh" 682SN/A 692SN/Aclass BaseCPU; 708887Sgeoffrey.blake@arm.comclass CheckerCPU; 711070SN/A 721917SN/Aclass FunctionProfile; 731917SN/Aclass ProfileNode; 742521SN/A 753548Sgblack@eecs.umich.edunamespace TheISA { 763548Sgblack@eecs.umich.edu namespace Kernel { 773548Sgblack@eecs.umich.edu class Statistics; 788902Sandreas.hansson@arm.com } 798902Sandreas.hansson@arm.com} 802330SN/A 812683Sktlim@umich.edu/** 822683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 832683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 842683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 852683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 862683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 872683Sktlim@umich.edu * the objects needed for simple functional execution, including a 882683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 892683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 902683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 912683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 922683Sktlim@umich.edu * all the necessary state for full architecture-level functional 932683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 942683Sktlim@umich.edu * examples. 952683Sktlim@umich.edu */ 962SN/A 972683Sktlim@umich.educlass SimpleThread : public ThreadState 982SN/A{ 992107SN/A protected: 1002107SN/A typedef TheISA::MachInst MachInst; 1012159SN/A typedef TheISA::MiscReg MiscReg; 1022455SN/A typedef TheISA::FloatReg FloatReg; 1032455SN/A typedef TheISA::FloatRegBits FloatRegBits; 1049920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 1052SN/A public: 1062680SN/A typedef ThreadContext::Status Status; 1072SN/A 1082190SN/A protected: 1096315Sgblack@eecs.umich.edu union { 1106315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1116315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1126315Sgblack@eecs.umich.edu } floatRegs; 1136316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 1149920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 1159920Syasuko.eckert@amd.com TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 1169920Syasuko.eckert@amd.com#endif 1179384SAndreas.Sandberg@arm.com TheISA::ISA *const isa; // one "instance" of the current ISA. 1182SN/A 1197720Sgblack@eecs.umich.edu TheISA::PCState _pcState; 1206324Sgblack@eecs.umich.edu 1217597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1227597Sminkyu.jeong@arm.com bool predicate; 1237597Sminkyu.jeong@arm.com 1242190SN/A public: 1258357Sksewell@umich.edu std::string name() const 1268357Sksewell@umich.edu { 1278735Sandreas.hanson@arm.com return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 1288357Sksewell@umich.edu } 1298357Sksewell@umich.edu 1302683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1312188SN/A 1322378SN/A System *system; 1332400SN/A 1346022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1356022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1362SN/A 1379020Sgblack@eecs.umich.edu TheISA::Decoder decoder; 1388541Sgblack@eecs.umich.edu 1392683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1408793Sgblack@eecs.umich.edu // FS 1412683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1429384SAndreas.Sandberg@arm.com TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa, 1432683Sktlim@umich.edu bool use_kernel_stats = true); 1448793Sgblack@eecs.umich.edu // SE 1458820Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1469384SAndreas.Sandberg@arm.com Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb, 1479384SAndreas.Sandberg@arm.com TheISA::ISA *_isa); 1482862Sktlim@umich.edu 1492683Sktlim@umich.edu virtual ~SimpleThread(); 1502SN/A 1512680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 152180SN/A 1532SN/A void regStats(const std::string &name); 1542SN/A 1552862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1562862Sktlim@umich.edu 15711168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 15811168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1599461Snilay@cs.wisc.edu void startup(); 160217SN/A 1612683Sktlim@umich.edu /*************************************************************** 1622683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1635891Sgblack@eecs.umich.edu * state. 1642683Sktlim@umich.edu **************************************************************/ 1652190SN/A 1662683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1672683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1682683Sktlim@umich.edu * CPU. 1692683Sktlim@umich.edu */ 1702680SN/A ThreadContext *getTC() { return tc; } 1712190SN/A 1725358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1735358Sgblack@eecs.umich.edu { 1745358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1755358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1765358Sgblack@eecs.umich.edu } 1775358Sgblack@eecs.umich.edu 1785358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1795358Sgblack@eecs.umich.edu { 1805358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1815358Sgblack@eecs.umich.edu } 1825358Sgblack@eecs.umich.edu 1835358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1845358Sgblack@eecs.umich.edu { 1855358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1865358Sgblack@eecs.umich.edu } 1875358Sgblack@eecs.umich.edu 1882683Sktlim@umich.edu void dumpFuncProfile(); 1892521SN/A 1905702Ssaidi@eecs.umich.edu Fault hwrei(); 1915702Ssaidi@eecs.umich.edu 1925702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1935702Ssaidi@eecs.umich.edu 1942683Sktlim@umich.edu /******************************************* 1952683Sktlim@umich.edu * ThreadContext interface functions. 1962683Sktlim@umich.edu ******************************************/ 1972683Sktlim@umich.edu 1988735Sandreas.hanson@arm.com BaseCPU *getCpuPtr() { return baseCpu; } 1992683Sktlim@umich.edu 2006022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 2012683Sktlim@umich.edu 2026022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 2032683Sktlim@umich.edu 2048887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return NULL; } 2058733Sgeoffrey.blake@arm.com 2069020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return &decoder; } 2078541Sgblack@eecs.umich.edu 2084997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2094997Sgblack@eecs.umich.edu 2102683Sktlim@umich.edu Status status() const { return _status; } 2112683Sktlim@umich.edu 2122683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2132683Sktlim@umich.edu 21410407Smitch.hayenga@arm.com /// Set the status to Active. 21510407Smitch.hayenga@arm.com void activate(); 2162683Sktlim@umich.edu 2172683Sktlim@umich.edu /// Set the status to Suspended. 2182683Sktlim@umich.edu void suspend(); 2192683Sktlim@umich.edu 2202683Sktlim@umich.edu /// Set the status to Halted. 2212683Sktlim@umich.edu void halt(); 2222683Sktlim@umich.edu 2232683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2242190SN/A 2256315Sgblack@eecs.umich.edu void clearArchRegs() 2266315Sgblack@eecs.umich.edu { 2277720Sgblack@eecs.umich.edu _pcState = 0; 2286316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 2296315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2309920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 2319920Syasuko.eckert@amd.com memset(ccRegs, 0, sizeof(ccRegs)); 2329920Syasuko.eckert@amd.com#endif 2339384SAndreas.Sandberg@arm.com isa->clear(); 2346315Sgblack@eecs.umich.edu } 2352190SN/A 2362SN/A // 2372SN/A // New accessors for new decoder. 2382SN/A // 2392SN/A uint64_t readIntReg(int reg_idx) 2402SN/A { 2419384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 2426323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2439426SAndreas.Sandberg@ARM.com uint64_t regVal(readIntRegFlat(flatIndex)); 2447601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2457601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 2466418Sgblack@eecs.umich.edu return regVal; 2472SN/A } 2482SN/A 2492455SN/A FloatReg readFloatReg(int reg_idx) 2502SN/A { 2519384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 2526323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2539426SAndreas.Sandberg@ARM.com FloatReg regVal(readFloatRegFlat(flatIndex)); 2547601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 2557601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 2567341Sgblack@eecs.umich.edu return regVal; 2572SN/A } 2582SN/A 2592455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2602455SN/A { 2619384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 2626323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2639426SAndreas.Sandberg@ARM.com FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); 2647601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 2657601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 2667341Sgblack@eecs.umich.edu return regVal; 2672SN/A } 2682SN/A 2699920Syasuko.eckert@amd.com CCReg readCCReg(int reg_idx) 2709920Syasuko.eckert@amd.com { 2719920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 2729920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 27310338SCurtis.Dunham@arm.com assert(0 <= flatIndex); 2749920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 2759920Syasuko.eckert@amd.com uint64_t regVal(readCCRegFlat(flatIndex)); 2769920Syasuko.eckert@amd.com DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 2779920Syasuko.eckert@amd.com reg_idx, flatIndex, regVal); 2789920Syasuko.eckert@amd.com return regVal; 2799920Syasuko.eckert@amd.com#else 2809920Syasuko.eckert@amd.com panic("Tried to read a CC register."); 2819920Syasuko.eckert@amd.com return 0; 2829920Syasuko.eckert@amd.com#endif 2839920Syasuko.eckert@amd.com } 2849920Syasuko.eckert@amd.com 2852SN/A void setIntReg(int reg_idx, uint64_t val) 2862SN/A { 2879384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 2886323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2897601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 2907601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 2919426SAndreas.Sandberg@ARM.com setIntRegFlat(flatIndex, val); 2922SN/A } 2932SN/A 2942455SN/A void setFloatReg(int reg_idx, FloatReg val) 2952SN/A { 2969384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 2976323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2989426SAndreas.Sandberg@ARM.com setFloatRegFlat(flatIndex, val); 2997601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 3007601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 3012SN/A } 3022SN/A 3032455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3042455SN/A { 3059384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 3066323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 3078733Sgeoffrey.blake@arm.com // XXX: Fix array out of bounds compiler error for gem5.fast 3088733Sgeoffrey.blake@arm.com // when checkercpu enabled 3098733Sgeoffrey.blake@arm.com if (flatIndex < TheISA::NumFloatRegs) 3109426SAndreas.Sandberg@ARM.com setFloatRegBitsFlat(flatIndex, val); 3117601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 3127601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 3132SN/A } 3142SN/A 3159920Syasuko.eckert@amd.com void setCCReg(int reg_idx, CCReg val) 3169920Syasuko.eckert@amd.com { 3179920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 3189920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 3199920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 3209920Syasuko.eckert@amd.com DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 3219920Syasuko.eckert@amd.com reg_idx, flatIndex, val); 3229920Syasuko.eckert@amd.com setCCRegFlat(flatIndex, val); 3239920Syasuko.eckert@amd.com#else 3249920Syasuko.eckert@amd.com panic("Tried to set a CC register."); 3259920Syasuko.eckert@amd.com#endif 3269920Syasuko.eckert@amd.com } 3279920Syasuko.eckert@amd.com 3287720Sgblack@eecs.umich.edu TheISA::PCState 3297720Sgblack@eecs.umich.edu pcState() 3302SN/A { 3317720Sgblack@eecs.umich.edu return _pcState; 3322SN/A } 3332SN/A 3347720Sgblack@eecs.umich.edu void 3357720Sgblack@eecs.umich.edu pcState(const TheISA::PCState &val) 3362190SN/A { 3377720Sgblack@eecs.umich.edu _pcState = val; 3382190SN/A } 3392190SN/A 3408733Sgeoffrey.blake@arm.com void 3418733Sgeoffrey.blake@arm.com pcStateNoRecord(const TheISA::PCState &val) 3428733Sgeoffrey.blake@arm.com { 3438733Sgeoffrey.blake@arm.com _pcState = val; 3448733Sgeoffrey.blake@arm.com } 3458733Sgeoffrey.blake@arm.com 3467720Sgblack@eecs.umich.edu Addr 3477720Sgblack@eecs.umich.edu instAddr() 3483276Sgblack@eecs.umich.edu { 3497720Sgblack@eecs.umich.edu return _pcState.instAddr(); 3503276Sgblack@eecs.umich.edu } 3513276Sgblack@eecs.umich.edu 3527720Sgblack@eecs.umich.edu Addr 3537720Sgblack@eecs.umich.edu nextInstAddr() 3543276Sgblack@eecs.umich.edu { 3557720Sgblack@eecs.umich.edu return _pcState.nextInstAddr(); 3563276Sgblack@eecs.umich.edu } 3573276Sgblack@eecs.umich.edu 3587720Sgblack@eecs.umich.edu MicroPC 3597720Sgblack@eecs.umich.edu microPC() 3602190SN/A { 3617720Sgblack@eecs.umich.edu return _pcState.microPC(); 3622251SN/A } 3632251SN/A 3647597Sminkyu.jeong@arm.com bool readPredicate() 3657597Sminkyu.jeong@arm.com { 3667597Sminkyu.jeong@arm.com return predicate; 3677597Sminkyu.jeong@arm.com } 3687597Sminkyu.jeong@arm.com 3697597Sminkyu.jeong@arm.com void setPredicate(bool val) 3707597Sminkyu.jeong@arm.com { 3717597Sminkyu.jeong@arm.com predicate = val; 3727597Sminkyu.jeong@arm.com } 3737597Sminkyu.jeong@arm.com 3746221Snate@binkert.org MiscReg 37510698Sandreas.hansson@arm.com readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const 3764172Ssaidi@eecs.umich.edu { 3779384SAndreas.Sandberg@arm.com return isa->readMiscRegNoEffect(misc_reg); 3784172Ssaidi@eecs.umich.edu } 3794172Ssaidi@eecs.umich.edu 3806221Snate@binkert.org MiscReg 3816221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 3822SN/A { 3839384SAndreas.Sandberg@arm.com return isa->readMiscReg(misc_reg, tc); 3842SN/A } 3852SN/A 3866221Snate@binkert.org void 3876221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3882SN/A { 3899384SAndreas.Sandberg@arm.com return isa->setMiscRegNoEffect(misc_reg, val); 3902SN/A } 3912SN/A 3926221Snate@binkert.org void 3936221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3942SN/A { 3959384SAndreas.Sandberg@arm.com return isa->setMiscReg(misc_reg, val, tc); 3966313Sgblack@eecs.umich.edu } 3976313Sgblack@eecs.umich.edu 3986313Sgblack@eecs.umich.edu int 3996313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 4006313Sgblack@eecs.umich.edu { 4019384SAndreas.Sandberg@arm.com return isa->flattenIntIndex(reg); 4026313Sgblack@eecs.umich.edu } 4036313Sgblack@eecs.umich.edu 4046313Sgblack@eecs.umich.edu int 4056313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 4066313Sgblack@eecs.umich.edu { 4079384SAndreas.Sandberg@arm.com return isa->flattenFloatIndex(reg); 4082SN/A } 4092SN/A 4109920Syasuko.eckert@amd.com int 4119920Syasuko.eckert@amd.com flattenCCIndex(int reg) 4129920Syasuko.eckert@amd.com { 4139920Syasuko.eckert@amd.com return isa->flattenCCIndex(reg); 4149920Syasuko.eckert@amd.com } 4159920Syasuko.eckert@amd.com 41610033SAli.Saidi@ARM.com int 41710033SAli.Saidi@ARM.com flattenMiscIndex(int reg) 41810033SAli.Saidi@ARM.com { 41910033SAli.Saidi@ARM.com return isa->flattenMiscIndex(reg); 42010033SAli.Saidi@ARM.com } 42110033SAli.Saidi@ARM.com 4222190SN/A unsigned readStCondFailures() { return storeCondFailures; } 4232190SN/A 4242190SN/A void setStCondFailures(unsigned sc_failures) 4252190SN/A { storeCondFailures = sc_failures; } 4262190SN/A 42711877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) 4282SN/A { 42911877Sbrandon.potter@amd.com process->syscall(callnum, tc, fault); 4302SN/A } 4319426SAndreas.Sandberg@ARM.com 4329426SAndreas.Sandberg@ARM.com uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } 4339426SAndreas.Sandberg@ARM.com void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } 4349426SAndreas.Sandberg@ARM.com 4359426SAndreas.Sandberg@ARM.com FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; } 4369426SAndreas.Sandberg@ARM.com void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; } 4379426SAndreas.Sandberg@ARM.com 4389426SAndreas.Sandberg@ARM.com FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; } 4399426SAndreas.Sandberg@ARM.com void setFloatRegBitsFlat(int idx, FloatRegBits val) { 4409426SAndreas.Sandberg@ARM.com floatRegs.i[idx] = val; 4419426SAndreas.Sandberg@ARM.com } 4429426SAndreas.Sandberg@ARM.com 4439920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 4449920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 4459920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 4469920Syasuko.eckert@amd.com#else 4479920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) 4489920Syasuko.eckert@amd.com { panic("readCCRegFlat w/no CC regs!\n"); } 4499920Syasuko.eckert@amd.com 4509920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) 4519920Syasuko.eckert@amd.com { panic("setCCRegFlat w/no CC regs!\n"); } 4529920Syasuko.eckert@amd.com#endif 4532SN/A}; 4542SN/A 4552SN/A 4562190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 457