simple_thread.hh revision 10338
12SN/A/* 210033SAli.Saidi@ARM.com * Copyright (c) 2011-2012 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 412665SN/A * Authors: Steve Reinhardt 422665SN/A * Nathan Binkert 432SN/A */ 442SN/A 452683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 462683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 472SN/A 489020Sgblack@eecs.umich.edu#include "arch/decoder.hh" 496313Sgblack@eecs.umich.edu#include "arch/isa.hh" 502190SN/A#include "arch/isa_traits.hh" 516329Sgblack@eecs.umich.edu#include "arch/registers.hh" 524997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 536316Sgblack@eecs.umich.edu#include "arch/types.hh" 546216Snate@binkert.org#include "base/types.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 562680SN/A#include "cpu/thread_context.hh" 572683Sktlim@umich.edu#include "cpu/thread_state.hh" 589920Syasuko.eckert@amd.com#include "debug/CCRegs.hh" 598232Snate@binkert.org#include "debug/FloatRegs.hh" 608232Snate@binkert.org#include "debug/IntRegs.hh" 618777Sgblack@eecs.umich.edu#include "mem/page_table.hh" 622395SN/A#include "mem/request.hh" 632190SN/A#include "sim/byteswap.hh" 642188SN/A#include "sim/eventq.hh" 658777Sgblack@eecs.umich.edu#include "sim/process.hh" 66217SN/A#include "sim/serialize.hh" 678777Sgblack@eecs.umich.edu#include "sim/system.hh" 682SN/A 692SN/Aclass BaseCPU; 708887Sgeoffrey.blake@arm.comclass CheckerCPU; 711070SN/A 721917SN/Aclass FunctionProfile; 731917SN/Aclass ProfileNode; 742521SN/A 753548Sgblack@eecs.umich.edunamespace TheISA { 763548Sgblack@eecs.umich.edu namespace Kernel { 773548Sgblack@eecs.umich.edu class Statistics; 788902Sandreas.hansson@arm.com } 798902Sandreas.hansson@arm.com} 802330SN/A 812683Sktlim@umich.edu/** 822683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 832683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 842683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 852683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 862683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 872683Sktlim@umich.edu * the objects needed for simple functional execution, including a 882683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 892683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 902683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 912683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 922683Sktlim@umich.edu * all the necessary state for full architecture-level functional 932683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 942683Sktlim@umich.edu * examples. 952683Sktlim@umich.edu */ 962SN/A 972683Sktlim@umich.educlass SimpleThread : public ThreadState 982SN/A{ 992107SN/A protected: 1002107SN/A typedef TheISA::MachInst MachInst; 1012159SN/A typedef TheISA::MiscReg MiscReg; 1022455SN/A typedef TheISA::FloatReg FloatReg; 1032455SN/A typedef TheISA::FloatRegBits FloatRegBits; 1049920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 1052SN/A public: 1062680SN/A typedef ThreadContext::Status Status; 1072SN/A 1082190SN/A protected: 1096315Sgblack@eecs.umich.edu union { 1106315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1116315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1126315Sgblack@eecs.umich.edu } floatRegs; 1136316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 1149920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 1159920Syasuko.eckert@amd.com TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 1169920Syasuko.eckert@amd.com#endif 1179384SAndreas.Sandberg@arm.com TheISA::ISA *const isa; // one "instance" of the current ISA. 1182SN/A 1197720Sgblack@eecs.umich.edu TheISA::PCState _pcState; 1206324Sgblack@eecs.umich.edu 1217597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1227597Sminkyu.jeong@arm.com bool predicate; 1237597Sminkyu.jeong@arm.com 1242190SN/A public: 1258357Sksewell@umich.edu std::string name() const 1268357Sksewell@umich.edu { 1278735Sandreas.hanson@arm.com return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 1288357Sksewell@umich.edu } 1298357Sksewell@umich.edu 1302683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1312188SN/A 1322378SN/A System *system; 1332400SN/A 1346022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1356022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1362SN/A 1379020Sgblack@eecs.umich.edu TheISA::Decoder decoder; 1388541Sgblack@eecs.umich.edu 1392683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1408793Sgblack@eecs.umich.edu // FS 1412683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1429384SAndreas.Sandberg@arm.com TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa, 1432683Sktlim@umich.edu bool use_kernel_stats = true); 1448793Sgblack@eecs.umich.edu // SE 1458820Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1469384SAndreas.Sandberg@arm.com Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb, 1479384SAndreas.Sandberg@arm.com TheISA::ISA *_isa); 1482862Sktlim@umich.edu 1492683Sktlim@umich.edu virtual ~SimpleThread(); 1502SN/A 1512680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 152180SN/A 1532SN/A void regStats(const std::string &name); 1542SN/A 1552862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1562862Sktlim@umich.edu 157217SN/A void serialize(std::ostream &os); 158237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 1599461Snilay@cs.wisc.edu void startup(); 160217SN/A 1612683Sktlim@umich.edu /*************************************************************** 1622683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1635891Sgblack@eecs.umich.edu * state. 1642683Sktlim@umich.edu **************************************************************/ 1652190SN/A 1662683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1672683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1682683Sktlim@umich.edu * CPU. 1692683Sktlim@umich.edu */ 1702680SN/A ThreadContext *getTC() { return tc; } 1712190SN/A 1725358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1735358Sgblack@eecs.umich.edu { 1745358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1755358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1765358Sgblack@eecs.umich.edu } 1775358Sgblack@eecs.umich.edu 1785358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1795358Sgblack@eecs.umich.edu { 1805358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1815358Sgblack@eecs.umich.edu } 1825358Sgblack@eecs.umich.edu 1835358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1845358Sgblack@eecs.umich.edu { 1855358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1865358Sgblack@eecs.umich.edu } 1875358Sgblack@eecs.umich.edu 1882683Sktlim@umich.edu void dumpFuncProfile(); 1892521SN/A 1905702Ssaidi@eecs.umich.edu Fault hwrei(); 1915702Ssaidi@eecs.umich.edu 1925702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1935702Ssaidi@eecs.umich.edu 1942683Sktlim@umich.edu /******************************************* 1952683Sktlim@umich.edu * ThreadContext interface functions. 1962683Sktlim@umich.edu ******************************************/ 1972683Sktlim@umich.edu 1988735Sandreas.hanson@arm.com BaseCPU *getCpuPtr() { return baseCpu; } 1992683Sktlim@umich.edu 2006022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 2012683Sktlim@umich.edu 2026022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 2032683Sktlim@umich.edu 2048887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return NULL; } 2058733Sgeoffrey.blake@arm.com 2069020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return &decoder; } 2078541Sgblack@eecs.umich.edu 2084997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2094997Sgblack@eecs.umich.edu 2102683Sktlim@umich.edu Status status() const { return _status; } 2112683Sktlim@umich.edu 2122683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2132683Sktlim@umich.edu 2142683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2152683Sktlim@umich.edu /// cycles to wait before beginning execution. 2169180Sandreas.hansson@arm.com void activate(Cycles delay = Cycles(1)); 2172683Sktlim@umich.edu 2182683Sktlim@umich.edu /// Set the status to Suspended. 2192683Sktlim@umich.edu void suspend(); 2202683Sktlim@umich.edu 2212683Sktlim@umich.edu /// Set the status to Halted. 2222683Sktlim@umich.edu void halt(); 2232683Sktlim@umich.edu 2242SN/A virtual bool misspeculating(); 2252SN/A 2262683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2272190SN/A 2286315Sgblack@eecs.umich.edu void clearArchRegs() 2296315Sgblack@eecs.umich.edu { 2307720Sgblack@eecs.umich.edu _pcState = 0; 2316316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 2326315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2339920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 2349920Syasuko.eckert@amd.com memset(ccRegs, 0, sizeof(ccRegs)); 2359920Syasuko.eckert@amd.com#endif 2369384SAndreas.Sandberg@arm.com isa->clear(); 2376315Sgblack@eecs.umich.edu } 2382190SN/A 2392SN/A // 2402SN/A // New accessors for new decoder. 2412SN/A // 2422SN/A uint64_t readIntReg(int reg_idx) 2432SN/A { 2449384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 2456323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2469426SAndreas.Sandberg@ARM.com uint64_t regVal(readIntRegFlat(flatIndex)); 2477601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2487601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 2496418Sgblack@eecs.umich.edu return regVal; 2502SN/A } 2512SN/A 2522455SN/A FloatReg readFloatReg(int reg_idx) 2532SN/A { 2549384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 2556323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2569426SAndreas.Sandberg@ARM.com FloatReg regVal(readFloatRegFlat(flatIndex)); 2577601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 2587601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 2597341Sgblack@eecs.umich.edu return regVal; 2602SN/A } 2612SN/A 2622455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2632455SN/A { 2649384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 2656323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2669426SAndreas.Sandberg@ARM.com FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); 2677601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 2687601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 2697341Sgblack@eecs.umich.edu return regVal; 2702SN/A } 2712SN/A 2729920Syasuko.eckert@amd.com CCReg readCCReg(int reg_idx) 2739920Syasuko.eckert@amd.com { 2749920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 2759920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 27610338SCurtis.Dunham@arm.com assert(0 <= flatIndex); 2779920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 2789920Syasuko.eckert@amd.com uint64_t regVal(readCCRegFlat(flatIndex)); 2799920Syasuko.eckert@amd.com DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 2809920Syasuko.eckert@amd.com reg_idx, flatIndex, regVal); 2819920Syasuko.eckert@amd.com return regVal; 2829920Syasuko.eckert@amd.com#else 2839920Syasuko.eckert@amd.com panic("Tried to read a CC register."); 2849920Syasuko.eckert@amd.com return 0; 2859920Syasuko.eckert@amd.com#endif 2869920Syasuko.eckert@amd.com } 2879920Syasuko.eckert@amd.com 2882SN/A void setIntReg(int reg_idx, uint64_t val) 2892SN/A { 2909384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 2916323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2927601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 2937601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 2949426SAndreas.Sandberg@ARM.com setIntRegFlat(flatIndex, val); 2952SN/A } 2962SN/A 2972455SN/A void setFloatReg(int reg_idx, FloatReg val) 2982SN/A { 2999384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 3006323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 3019426SAndreas.Sandberg@ARM.com setFloatRegFlat(flatIndex, val); 3027601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 3037601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 3042SN/A } 3052SN/A 3062455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3072455SN/A { 3089384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 3096323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 3108733Sgeoffrey.blake@arm.com // XXX: Fix array out of bounds compiler error for gem5.fast 3118733Sgeoffrey.blake@arm.com // when checkercpu enabled 3128733Sgeoffrey.blake@arm.com if (flatIndex < TheISA::NumFloatRegs) 3139426SAndreas.Sandberg@ARM.com setFloatRegBitsFlat(flatIndex, val); 3147601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 3157601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 3162SN/A } 3172SN/A 3189920Syasuko.eckert@amd.com void setCCReg(int reg_idx, CCReg val) 3199920Syasuko.eckert@amd.com { 3209920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 3219920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 3229920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 3239920Syasuko.eckert@amd.com DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 3249920Syasuko.eckert@amd.com reg_idx, flatIndex, val); 3259920Syasuko.eckert@amd.com setCCRegFlat(flatIndex, val); 3269920Syasuko.eckert@amd.com#else 3279920Syasuko.eckert@amd.com panic("Tried to set a CC register."); 3289920Syasuko.eckert@amd.com#endif 3299920Syasuko.eckert@amd.com } 3309920Syasuko.eckert@amd.com 3317720Sgblack@eecs.umich.edu TheISA::PCState 3327720Sgblack@eecs.umich.edu pcState() 3332SN/A { 3347720Sgblack@eecs.umich.edu return _pcState; 3352SN/A } 3362SN/A 3377720Sgblack@eecs.umich.edu void 3387720Sgblack@eecs.umich.edu pcState(const TheISA::PCState &val) 3392190SN/A { 3407720Sgblack@eecs.umich.edu _pcState = val; 3412190SN/A } 3422190SN/A 3438733Sgeoffrey.blake@arm.com void 3448733Sgeoffrey.blake@arm.com pcStateNoRecord(const TheISA::PCState &val) 3458733Sgeoffrey.blake@arm.com { 3468733Sgeoffrey.blake@arm.com _pcState = val; 3478733Sgeoffrey.blake@arm.com } 3488733Sgeoffrey.blake@arm.com 3497720Sgblack@eecs.umich.edu Addr 3507720Sgblack@eecs.umich.edu instAddr() 3513276Sgblack@eecs.umich.edu { 3527720Sgblack@eecs.umich.edu return _pcState.instAddr(); 3533276Sgblack@eecs.umich.edu } 3543276Sgblack@eecs.umich.edu 3557720Sgblack@eecs.umich.edu Addr 3567720Sgblack@eecs.umich.edu nextInstAddr() 3573276Sgblack@eecs.umich.edu { 3587720Sgblack@eecs.umich.edu return _pcState.nextInstAddr(); 3593276Sgblack@eecs.umich.edu } 3603276Sgblack@eecs.umich.edu 3617720Sgblack@eecs.umich.edu MicroPC 3627720Sgblack@eecs.umich.edu microPC() 3632190SN/A { 3647720Sgblack@eecs.umich.edu return _pcState.microPC(); 3652251SN/A } 3662251SN/A 3677597Sminkyu.jeong@arm.com bool readPredicate() 3687597Sminkyu.jeong@arm.com { 3697597Sminkyu.jeong@arm.com return predicate; 3707597Sminkyu.jeong@arm.com } 3717597Sminkyu.jeong@arm.com 3727597Sminkyu.jeong@arm.com void setPredicate(bool val) 3737597Sminkyu.jeong@arm.com { 3747597Sminkyu.jeong@arm.com predicate = val; 3757597Sminkyu.jeong@arm.com } 3767597Sminkyu.jeong@arm.com 3776221Snate@binkert.org MiscReg 3786221Snate@binkert.org readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 3794172Ssaidi@eecs.umich.edu { 3809384SAndreas.Sandberg@arm.com return isa->readMiscRegNoEffect(misc_reg); 3814172Ssaidi@eecs.umich.edu } 3824172Ssaidi@eecs.umich.edu 3836221Snate@binkert.org MiscReg 3846221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 3852SN/A { 3869384SAndreas.Sandberg@arm.com return isa->readMiscReg(misc_reg, tc); 3872SN/A } 3882SN/A 3896221Snate@binkert.org void 3906221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3912SN/A { 3929384SAndreas.Sandberg@arm.com return isa->setMiscRegNoEffect(misc_reg, val); 3932SN/A } 3942SN/A 3956221Snate@binkert.org void 3966221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3972SN/A { 3989384SAndreas.Sandberg@arm.com return isa->setMiscReg(misc_reg, val, tc); 3996313Sgblack@eecs.umich.edu } 4006313Sgblack@eecs.umich.edu 4016313Sgblack@eecs.umich.edu int 4026313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 4036313Sgblack@eecs.umich.edu { 4049384SAndreas.Sandberg@arm.com return isa->flattenIntIndex(reg); 4056313Sgblack@eecs.umich.edu } 4066313Sgblack@eecs.umich.edu 4076313Sgblack@eecs.umich.edu int 4086313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 4096313Sgblack@eecs.umich.edu { 4109384SAndreas.Sandberg@arm.com return isa->flattenFloatIndex(reg); 4112SN/A } 4122SN/A 4139920Syasuko.eckert@amd.com int 4149920Syasuko.eckert@amd.com flattenCCIndex(int reg) 4159920Syasuko.eckert@amd.com { 4169920Syasuko.eckert@amd.com return isa->flattenCCIndex(reg); 4179920Syasuko.eckert@amd.com } 4189920Syasuko.eckert@amd.com 41910033SAli.Saidi@ARM.com int 42010033SAli.Saidi@ARM.com flattenMiscIndex(int reg) 42110033SAli.Saidi@ARM.com { 42210033SAli.Saidi@ARM.com return isa->flattenMiscIndex(reg); 42310033SAli.Saidi@ARM.com } 42410033SAli.Saidi@ARM.com 4252190SN/A unsigned readStCondFailures() { return storeCondFailures; } 4262190SN/A 4272190SN/A void setStCondFailures(unsigned sc_failures) 4282190SN/A { storeCondFailures = sc_failures; } 4292190SN/A 4302561SN/A void syscall(int64_t callnum) 4312SN/A { 4322680SN/A process->syscall(callnum, tc); 4332SN/A } 4349426SAndreas.Sandberg@ARM.com 4359426SAndreas.Sandberg@ARM.com uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } 4369426SAndreas.Sandberg@ARM.com void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } 4379426SAndreas.Sandberg@ARM.com 4389426SAndreas.Sandberg@ARM.com FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; } 4399426SAndreas.Sandberg@ARM.com void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; } 4409426SAndreas.Sandberg@ARM.com 4419426SAndreas.Sandberg@ARM.com FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; } 4429426SAndreas.Sandberg@ARM.com void setFloatRegBitsFlat(int idx, FloatRegBits val) { 4439426SAndreas.Sandberg@ARM.com floatRegs.i[idx] = val; 4449426SAndreas.Sandberg@ARM.com } 4459426SAndreas.Sandberg@ARM.com 4469920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 4479920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 4489920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 4499920Syasuko.eckert@amd.com#else 4509920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) 4519920Syasuko.eckert@amd.com { panic("readCCRegFlat w/no CC regs!\n"); } 4529920Syasuko.eckert@amd.com 4539920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) 4549920Syasuko.eckert@amd.com { panic("setCCRegFlat w/no CC regs!\n"); } 4559920Syasuko.eckert@amd.com#endif 4562SN/A}; 4572SN/A 4582SN/A 4592SN/A// for non-speculative execution context, spec_mode is always false 4602SN/Ainline bool 4612683Sktlim@umich.eduSimpleThread::misspeculating() 4622SN/A{ 4632SN/A return false; 4642SN/A} 4652SN/A 4662190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 467