simple_thread.cc revision 9384:877293183bdf
12SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2001-2006 The Regents of The University of Michigan 38707Sandreas.hansson@arm.com * All rights reserved. 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68707Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78707Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88707Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98707Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108707Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118707Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128707Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138707Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 141762SN/A * this software without specific prior written permission. 157897Shestness@cs.utexas.edu * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A * 282SN/A * Authors: Steve Reinhardt 292SN/A * Nathan Binkert 302SN/A * Lisa Hsu 312SN/A * Kevin Lim 322SN/A */ 332SN/A 342SN/A#include <string> 352SN/A 362SN/A#include "arch/isa_traits.hh" 372SN/A#include "arch/kernel_stats.hh" 382SN/A#include "arch/stacktrace.hh" 392SN/A#include "arch/utility.hh" 402665Ssaidi@eecs.umich.edu#include "base/callback.hh" 412665Ssaidi@eecs.umich.edu#include "base/cprintf.hh" 422665Ssaidi@eecs.umich.edu#include "base/output.hh" 437897Shestness@cs.utexas.edu#include "base/trace.hh" 442SN/A#include "config/the_isa.hh" 452SN/A#include "cpu/base.hh" 461388SN/A#include "cpu/profile.hh" 478229Snate@binkert.org#include "cpu/quiesce_event.hh" 482SN/A#include "cpu/simple_thread.hh" 492SN/A#include "cpu/thread_context.hh" 507781SAli.Saidi@ARM.com#include "mem/fs_translating_port_proxy.hh" 518229Snate@binkert.org#include "mem/se_translating_port_proxy.hh" 521191SN/A#include "params/BaseCPU.hh" 531191SN/A#include "sim/full_system.hh" 541388SN/A#include "sim/process.hh" 555529Snate@binkert.org#include "sim/serialize.hh" 568733Sgeoffrey.blake@arm.com#include "sim/sim_exit.hh" 571717SN/A#include "sim/system.hh" 582651Ssaidi@eecs.umich.edu 598229Snate@binkert.orgusing namespace std; 602680Sktlim@umich.edu 618232Snate@binkert.org// constructor 625529Snate@binkert.orgSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 638779Sgblack@eecs.umich.edu Process *_process, TheISA::TLB *_itb, 642190SN/A TheISA::TLB *_dtb, TheISA::ISA *_isa) 6556SN/A : ThreadState(_cpu, _thread_num, _process), isa(_isa), system(_sys), 668229Snate@binkert.org itb(_itb), dtb(_dtb) 672190SN/A{ 682SN/A clearArchRegs(); 698733Sgeoffrey.blake@arm.com tc = new ProxyThreadContext<SimpleThread>(this); 708733Sgeoffrey.blake@arm.com} 718733Sgeoffrey.blake@arm.com 728733Sgeoffrey.blake@arm.comSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 732359SN/A TheISA::TLB *_itb, TheISA::TLB *_dtb, 742359SN/A TheISA::ISA *_isa, bool use_kernel_stats) 752359SN/A : ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb), 762SN/A dtb(_dtb) 772SN/A{ 782SN/A tc = new ProxyThreadContext<SimpleThread>(this); 792SN/A 802SN/A quiesceEvent = new EndQuiesceEvent(tc); 812SN/A 822SN/A clearArchRegs(); 832SN/A 842SN/A if (baseCpu->params()->profile) { 855606Snate@binkert.org profile = new FunctionProfile(system->kernelSymtab); 866144Sksewell@umich.edu Callback *cb = 876144Sksewell@umich.edu new MakeCallback<SimpleThread, 883126Sktlim@umich.edu &SimpleThread::dumpFuncProfile>(this); 896144Sksewell@umich.edu registerExitCallback(cb); 907823Ssteve.reinhardt@amd.com } 913126Sktlim@umich.edu 923126Sktlim@umich.edu // let's fill with a dummy node for now so we don't get a segfault 932356SN/A // on the first cycle when there's no node available. 942356SN/A static ProfileNode dummyNode; 952356SN/A profileNode = &dummyNode; 968834Satgutier@umich.edu profilePC = 3; 972356SN/A 986144Sksewell@umich.edu if (use_kernel_stats) 992367SN/A kernelStats = new TheISA::Kernel::Statistics(system); 1006144Sksewell@umich.edu} 1016144Sksewell@umich.edu 1026144Sksewell@umich.eduSimpleThread::SimpleThread() 1032356SN/A : ThreadState(NULL, -1, NULL), isa(NULL) 1042367SN/A{ 1056144Sksewell@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1067823Ssteve.reinhardt@amd.com} 1076144Sksewell@umich.edu 1082367SN/ASimpleThread::~SimpleThread() 1092356SN/A{ 1106144Sksewell@umich.edu delete tc; 1116144Sksewell@umich.edu} 1127823Ssteve.reinhardt@amd.com 1132356SN/Avoid 1142356SN/ASimpleThread::takeOverFrom(ThreadContext *oldContext) 1152356SN/A{ 1165336Shines@cs.fsu.edu // some things should already be set up 1172356SN/A if (FullSystem) 1184873Sstever@eecs.umich.edu assert(system == oldContext->getSystemPtr()); 1192356SN/A assert(process == oldContext->getProcessPtr()); 1202356SN/A 1211400SN/A copyState(oldContext); 1225712Shsul@eecs.umich.edu if (FullSystem) { 1238832SAli.Saidi@ARM.com EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 1248832SAli.Saidi@ARM.com if (quiesce) { 1255712Shsul@eecs.umich.edu // Point the quiesce event's TC at this TC so that it wakes up 1266221Snate@binkert.org // the proper CPU. 1273661Srdreslin@umich.edu quiesce->tc = tc; 1282SN/A } 1297823Ssteve.reinhardt@amd.com if (quiesceEvent) { 1301062SN/A quiesceEvent->tc = tc; 1315712Shsul@eecs.umich.edu } 1325712Shsul@eecs.umich.edu 1335712Shsul@eecs.umich.edu TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); 1345712Shsul@eecs.umich.edu if (stats) { 1355712Shsul@eecs.umich.edu kernelStats = stats; 1362SN/A } 1372SN/A } 1382SN/A 1395712Shsul@eecs.umich.edu storeCondFailures = 0; 1405712Shsul@eecs.umich.edu 1416221Snate@binkert.org oldContext->setStatus(ThreadContext::Halted); 1426221Snate@binkert.org} 1432SN/A 1442SN/Avoid 1456221Snate@binkert.orgSimpleThread::copyTC(ThreadContext *context) 1466221Snate@binkert.org{ 1476221Snate@binkert.org copyState(context); 1486221Snate@binkert.org 1492SN/A if (FullSystem) { 1502SN/A EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 1512SN/A if (quiesce) { 1522SN/A quiesceEvent = quiesce; 1535606Snate@binkert.org } 1545606Snate@binkert.org TheISA::Kernel::Statistics *stats = context->getKernelStats(); 1556221Snate@binkert.org if (stats) { 1565606Snate@binkert.org kernelStats = stats; 1576221Snate@binkert.org } 1585606Snate@binkert.org } 1595606Snate@binkert.org} 1602SN/A 1611400SN/Avoid 1625606Snate@binkert.orgSimpleThread::copyState(ThreadContext *oldContext) 1635606Snate@binkert.org{ 1642SN/A // copy over functional state 1652SN/A _status = oldContext->status(); 1662SN/A copyArchRegs(oldContext); 1672SN/A if (FullSystem) 1686221Snate@binkert.org funcExeInst = oldContext->readFuncExeInst(); 1696221Snate@binkert.org 1705606Snate@binkert.org _threadId = oldContext->threadId(); 1716670Shsul@eecs.umich.edu _contextId = oldContext->contextId(); 1725606Snate@binkert.org} 1732SN/A 1742SN/Avoid 175124SN/ASimpleThread::serialize(ostream &os) 1766221Snate@binkert.org{ 1776221Snate@binkert.org ThreadState::serialize(os); 1786221Snate@binkert.org SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 179124SN/A SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 180124SN/A _pcState.serialize(os); 181124SN/A // thread_num and cpu_id are deterministic from the config 182124SN/A 1835606Snate@binkert.org // 1845606Snate@binkert.org // Now must serialize all the ISA dependent state 1856221Snate@binkert.org // 1865606Snate@binkert.org isa->serialize(baseCpu, os); 1876221Snate@binkert.org} 1885606Snate@binkert.org 1895606Snate@binkert.org 190124SN/Avoid 1911400SN/ASimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 1925606Snate@binkert.org{ 193124SN/A ThreadState::unserialize(cp, section); 194124SN/A UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 195124SN/A UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 196124SN/A _pcState.unserialize(cp, section); 1976221Snate@binkert.org // thread_num and cpu_id are deterministic from the config 1986221Snate@binkert.org 1995606Snate@binkert.org // 2006221Snate@binkert.org // Now must unserialize all the ISA dependent state 2015606Snate@binkert.org // 202124SN/A isa->unserialize(baseCpu, cp, section); 203124SN/A} 2041191SN/A 2055529Snate@binkert.orgvoid 2068634Schris.emmons@arm.comSimpleThread::dumpFuncProfile() 2078634Schris.emmons@arm.com{ 2088634Schris.emmons@arm.com std::ostream *os = simout.create(csprintf("profile.%s.dat", 2098634Schris.emmons@arm.com baseCpu->name())); 2108634Schris.emmons@arm.com profile->dump(tc, *os); 2111191SN/A} 2125529Snate@binkert.org 2131191SN/Avoid 2145529Snate@binkert.orgSimpleThread::activate(Cycles delay) 2151191SN/A{ 2161191SN/A if (status() == ThreadContext::Active) 2175606Snate@binkert.org return; 2185606Snate@binkert.org 2195606Snate@binkert.org lastActivate = curTick(); 2201191SN/A 2211191SN/A// if (status() == ThreadContext::Unallocated) { 2228733Sgeoffrey.blake@arm.com// cpu->activateWhenReady(_threadId); 2238733Sgeoffrey.blake@arm.com// return; 2248733Sgeoffrey.blake@arm.com// } 2258733Sgeoffrey.blake@arm.com 2265810Sgblack@eecs.umich.edu _status = ThreadContext::Active; 2278779Sgblack@eecs.umich.edu 2288779Sgblack@eecs.umich.edu // status() == Suspended 2298779Sgblack@eecs.umich.edu baseCpu->activateContext(_threadId, delay); 2308779Sgblack@eecs.umich.edu} 2318779Sgblack@eecs.umich.edu 2325529Snate@binkert.orgvoid 2331917SN/ASimpleThread::suspend() 2341191SN/A{ 2351191SN/A if (status() == ThreadContext::Suspended) 2361191SN/A return; 2371191SN/A 2381191SN/A lastActivate = curTick(); 2391191SN/A lastSuspend = curTick(); 2401191SN/A _status = ThreadContext::Suspended; 2411191SN/A baseCpu->suspendContext(_threadId); 2421191SN/A} 2431191SN/A 2441191SN/A 2451129SN/Avoid 2461129SN/ASimpleThread::halt() 2471129SN/A{ 2485529Snate@binkert.org if (status() == ThreadContext::Halted) 2492680Sktlim@umich.edu return; 2501129SN/A 251180SN/A _status = ThreadContext::Halted; 2522SN/A baseCpu->haltContext(_threadId); 2531917SN/A} 2541917SN/A 2558779Sgblack@eecs.umich.edu 2568779Sgblack@eecs.umich.eduvoid 2578779Sgblack@eecs.umich.eduSimpleThread::regStats(const string &name) 2588779Sgblack@eecs.umich.edu{ 2592356SN/A if (FullSystem && kernelStats) 2605529Snate@binkert.org kernelStats->regStats(name + ".kern"); 2615606Snate@binkert.org} 2626144Sksewell@umich.edu 2638607Sgblack@eecs.umich.eduvoid 2642356SN/ASimpleThread::copyArchRegs(ThreadContext *src_tc) 2651917SN/A{ 2661917SN/A TheISA::copyRegs(src_tc, tc); 2671917SN/A} 2681917SN/A 2692SN/A