simple_thread.cc revision 9180:ee8d7a51651d 
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 *          Lisa Hsu
31 *          Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "arch/kernel_stats.hh"
38#include "arch/stacktrace.hh"
39#include "arch/utility.hh"
40#include "base/callback.hh"
41#include "base/cprintf.hh"
42#include "base/output.hh"
43#include "base/trace.hh"
44#include "config/the_isa.hh"
45#include "cpu/base.hh"
46#include "cpu/profile.hh"
47#include "cpu/quiesce_event.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/thread_context.hh"
50#include "mem/fs_translating_port_proxy.hh"
51#include "mem/se_translating_port_proxy.hh"
52#include "params/BaseCPU.hh"
53#include "sim/full_system.hh"
54#include "sim/process.hh"
55#include "sim/serialize.hh"
56#include "sim/sim_exit.hh"
57#include "sim/system.hh"
58
59using namespace std;
60
61// constructor
62SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
63                           Process *_process, TheISA::TLB *_itb,
64                           TheISA::TLB *_dtb)
65    : ThreadState(_cpu, _thread_num, _process), system(_sys), itb(_itb),
66      dtb(_dtb), decoder(NULL)
67{
68    clearArchRegs();
69    tc = new ProxyThreadContext<SimpleThread>(this);
70}
71SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
72                           TheISA::TLB *_itb, TheISA::TLB *_dtb,
73                           bool use_kernel_stats)
74    : ThreadState(_cpu, _thread_num, NULL), system(_sys), itb(_itb), dtb(_dtb),
75      decoder(NULL)
76{
77    tc = new ProxyThreadContext<SimpleThread>(this);
78
79    quiesceEvent = new EndQuiesceEvent(tc);
80
81    clearArchRegs();
82
83    if (baseCpu->params()->profile) {
84        profile = new FunctionProfile(system->kernelSymtab);
85        Callback *cb =
86            new MakeCallback<SimpleThread,
87            &SimpleThread::dumpFuncProfile>(this);
88        registerExitCallback(cb);
89    }
90
91    // let's fill with a dummy node for now so we don't get a segfault
92    // on the first cycle when there's no node available.
93    static ProfileNode dummyNode;
94    profileNode = &dummyNode;
95    profilePC = 3;
96
97    if (use_kernel_stats)
98        kernelStats = new TheISA::Kernel::Statistics(system);
99}
100
101SimpleThread::SimpleThread()
102    : ThreadState(NULL, -1, NULL), decoder(NULL)
103{
104    tc = new ProxyThreadContext<SimpleThread>(this);
105}
106
107SimpleThread::~SimpleThread()
108{
109    delete tc;
110}
111
112void
113SimpleThread::takeOverFrom(ThreadContext *oldContext)
114{
115    // some things should already be set up
116    if (FullSystem)
117        assert(system == oldContext->getSystemPtr());
118    assert(process == oldContext->getProcessPtr());
119
120    copyState(oldContext);
121    if (FullSystem) {
122        EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
123        if (quiesce) {
124            // Point the quiesce event's TC at this TC so that it wakes up
125            // the proper CPU.
126            quiesce->tc = tc;
127        }
128        if (quiesceEvent) {
129            quiesceEvent->tc = tc;
130        }
131
132        TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
133        if (stats) {
134            kernelStats = stats;
135        }
136    }
137
138    storeCondFailures = 0;
139
140    oldContext->setStatus(ThreadContext::Halted);
141}
142
143void
144SimpleThread::copyTC(ThreadContext *context)
145{
146    copyState(context);
147
148    if (FullSystem) {
149        EndQuiesceEvent *quiesce = context->getQuiesceEvent();
150        if (quiesce) {
151            quiesceEvent = quiesce;
152        }
153        TheISA::Kernel::Statistics *stats = context->getKernelStats();
154        if (stats) {
155            kernelStats = stats;
156        }
157    }
158}
159
160void
161SimpleThread::copyState(ThreadContext *oldContext)
162{
163    // copy over functional state
164    _status = oldContext->status();
165    copyArchRegs(oldContext);
166    if (FullSystem)
167        funcExeInst = oldContext->readFuncExeInst();
168
169    _threadId = oldContext->threadId();
170    _contextId = oldContext->contextId();
171}
172
173void
174SimpleThread::serialize(ostream &os)
175{
176    ThreadState::serialize(os);
177    SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
178    SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
179    _pcState.serialize(os);
180    // thread_num and cpu_id are deterministic from the config
181
182    //
183    // Now must serialize all the ISA dependent state
184    //
185    isa.serialize(baseCpu, os);
186}
187
188
189void
190SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
191{
192    ThreadState::unserialize(cp, section);
193    UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
194    UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
195    _pcState.unserialize(cp, section);
196    // thread_num and cpu_id are deterministic from the config
197
198    //
199    // Now must unserialize all the ISA dependent state
200    //
201    isa.unserialize(baseCpu, cp, section);
202}
203
204void
205SimpleThread::dumpFuncProfile()
206{
207    std::ostream *os = simout.create(csprintf("profile.%s.dat",
208                                              baseCpu->name()));
209    profile->dump(tc, *os);
210}
211
212void
213SimpleThread::activate(Cycles delay)
214{
215    if (status() == ThreadContext::Active)
216        return;
217
218    lastActivate = curTick();
219
220//    if (status() == ThreadContext::Unallocated) {
221//      cpu->activateWhenReady(_threadId);
222//      return;
223//   }
224
225    _status = ThreadContext::Active;
226
227    // status() == Suspended
228    baseCpu->activateContext(_threadId, delay);
229}
230
231void
232SimpleThread::suspend()
233{
234    if (status() == ThreadContext::Suspended)
235        return;
236
237    lastActivate = curTick();
238    lastSuspend = curTick();
239    _status = ThreadContext::Suspended;
240    baseCpu->suspendContext(_threadId);
241}
242
243
244void
245SimpleThread::halt()
246{
247    if (status() == ThreadContext::Halted)
248        return;
249
250    _status = ThreadContext::Halted;
251    baseCpu->haltContext(_threadId);
252}
253
254
255void
256SimpleThread::regStats(const string &name)
257{
258    if (FullSystem && kernelStats)
259        kernelStats->regStats(name + ".kern");
260}
261
262void
263SimpleThread::copyArchRegs(ThreadContext *src_tc)
264{
265    TheISA::copyRegs(src_tc, tc);
266}
267
268